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git01.mediatek.com / filogic / uboot / cdc7ed3a93db92a264f0a6154693563a0c037f15 / . / arch / arm / mach-socfpga / include / mach
tree: 40ae3cff549de283de4d239cf18dd1da8dbcefce [path history] [tgz]
  1. base_addr_a10.h
  2. base_addr_ac5.h
  3. base_addr_s10.h
  4. boot0.h
  5. clock_manager.h
  6. clock_manager_agilex.h
  7. clock_manager_arria10.h
  8. clock_manager_gen5.h
  9. clock_manager_s10.h
  10. clock_manager_soc64.h
  11. firewall.h
  12. fpga_manager.h
  13. fpga_manager_arria10.h
  14. fpga_manager_gen5.h
  15. freeze_controller.h
  16. gpio.h
  17. handoff_s10.h
  18. mailbox_s10.h
  19. misc.h
  20. nic301.h
  21. pinmux.h
  22. reset_manager.h
  23. reset_manager_arria10.h
  24. reset_manager_gen5.h
  25. reset_manager_soc64.h
  26. scan_manager.h
  27. scu.h
  28. sdram.h
  29. sdram_arria10.h
  30. sdram_gen5.h
  31. system_manager.h
  32. system_manager_arria10.h
  33. system_manager_gen5.h
  34. system_manager_soc64.h
  35. timer.h