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filogic
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ca22e962963d7507dfec6b22e14d80e0f2961980
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.
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arch
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xtensa
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cpu
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Makefile
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#
# (C) Copyright 2007 - 2013 Tensilica, Inc.
# (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj
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y
=
cpu
.
o exceptions
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o
extra
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y
=
start
.
o