// SPDX-License-Identifier: GPL-2.0 | |
/* | |
* Copyright (C) 2019 MediaTek Inc. | |
* Author: Sam Shih <sam.shih@mediatek.com> | |
*/ | |
#include <common.h> | |
#include <fdtdec.h> | |
#include <init.h> | |
#include <asm/armv8/mmu.h> | |
#include <asm/cache.h> | |
int print_cpuinfo(void) | |
{ | |
printf("CPU: MediaTek MT7622\n"); | |
return 0; | |
} | |
int dram_init(void) | |
{ | |
int ret; | |
ret = fdtdec_setup_memory_banksize(); | |
if (ret) | |
return ret; | |
return fdtdec_setup_mem_size_base(); | |
} | |
void reset_cpu(void) | |
{ | |
psci_system_reset(); | |
} | |
static struct mm_region mt7622_mem_map[] = { | |
{ | |
/* DDR */ | |
.virt = 0x40000000UL, | |
.phys = 0x40000000UL, | |
.size = 0x40000000UL, | |
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, | |
}, { | |
.virt = 0x00000000UL, | |
.phys = 0x00000000UL, | |
.size = 0x40000000UL, | |
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
PTE_BLOCK_NON_SHARE | | |
PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
}, { | |
0, | |
} | |
}; | |
struct mm_region *mem_map = mt7622_mem_map; |