| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2020 Toradex |
| */ |
| |
| #include <common.h> |
| #include <command.h> |
| #include <image.h> |
| #include <init.h> |
| #include <log.h> |
| #include <asm/arch/clock.h> |
| #include <asm/arch/ddr.h> |
| #include <asm/arch/imx8mm_pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/global_data.h> |
| #include <asm/io.h> |
| #include <asm/mach-imx/boot_mode.h> |
| #include <asm/mach-imx/iomux-v3.h> |
| #include <cpu_func.h> |
| #include <dm/device.h> |
| #include <dm/device-internal.h> |
| #include <dm/uclass.h> |
| #include <dm/uclass-internal.h> |
| #include <hang.h> |
| #include <i2c.h> |
| #include <power/pca9450.h> |
| #include <power/pmic.h> |
| #include <spl.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define I2C_PMIC_BUS_ID 1 |
| |
| int spl_board_boot_device(enum boot_device boot_dev_spl) |
| { |
| switch (boot_dev_spl) { |
| case MMC1_BOOT: |
| return BOOT_DEVICE_MMC1; |
| case SD2_BOOT: |
| case MMC2_BOOT: |
| return BOOT_DEVICE_MMC2; |
| case SD3_BOOT: |
| case MMC3_BOOT: |
| return BOOT_DEVICE_MMC1; |
| case USB_BOOT: |
| return BOOT_DEVICE_BOARD; |
| default: |
| return BOOT_DEVICE_NONE; |
| } |
| } |
| |
| void spl_dram_init(void) |
| { |
| ddr_init(&dram_timing); |
| } |
| |
| void spl_board_init(void) |
| { |
| /* Serial download mode */ |
| if (is_usb_boot()) { |
| puts("Back to ROM, SDP\n"); |
| restore_boot_params(); |
| } |
| puts("Normal Boot\n"); |
| } |
| |
| #ifdef CONFIG_SPL_LOAD_FIT |
| int board_fit_config_name_match(const char *name) |
| { |
| /* Just empty function now - can't decide what to choose */ |
| debug("%s: %s\n", __func__, name); |
| |
| return 0; |
| } |
| #endif |
| |
| #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) |
| #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) |
| |
| /* Verdin UART_3, Console/Debug UART */ |
| static iomux_v3_cfg_t const uart_pads[] = { |
| IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const wdog_pads[] = { |
| IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| }; |
| |
| __weak void board_early_init(void) |
| { |
| struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| |
| init_uart_clk(0); |
| |
| imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| |
| set_wdog_reset(wdog); |
| |
| imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
| } |
| |
| int power_init_board(void) |
| { |
| struct udevice *dev; |
| int ret; |
| |
| if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) { |
| ret = pmic_get("pmic", &dev); |
| if (ret == -ENODEV) { |
| puts("No pmic found\n"); |
| return ret; |
| } |
| |
| if (ret != 0) |
| return ret; |
| |
| /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */ |
| pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); |
| |
| /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */ |
| pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c); |
| |
| /* set WDOG_B_CFG to cold reset */ |
| pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); |
| |
| pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); |
| |
| return 0; |
| } |
| |
| return 0; |
| } |
| |
| void board_init_f(ulong dummy) |
| { |
| struct udevice *dev; |
| int ret; |
| |
| arch_cpu_init(); |
| |
| board_early_init(); |
| |
| timer_init(); |
| |
| preloader_console_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| ret = spl_early_init(); |
| if (ret) { |
| debug("spl_early_init() failed: %d\n", ret); |
| hang(); |
| } |
| |
| ret = uclass_get_device_by_name(UCLASS_CLK, |
| "clock-controller@30380000", |
| &dev); |
| if (ret < 0) { |
| printf("Failed to find clock node. Check device tree\n"); |
| hang(); |
| } |
| |
| enable_tzc380(); |
| |
| power_init_board(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| board_init_r(NULL, 0); |
| } |