| // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11 |
| * Some assumptions are made: |
| * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8 |
| * (sgmii for DPMAC 12, 13, 14, 16, 17, 18) |
| #include "fsl-lx2160a-qds.dtsi" |
| phy-handle = <&sgmii_phy7_2>; |
| phy-connection-type = "sgmii"; |
| phy-handle = <&sgmii_phy7_3>; |
| phy-connection-type = "sgmii"; |
| phy-handle = <&sgmii_phy7_4>; |
| phy-connection-type = "sgmii"; |
| phy-handle = <&sgmii_phy8_2>; |
| phy-connection-type = "sgmii"; |
| phy-handle = <&sgmii_phy8_3>; |
| phy-connection-type = "sgmii"; |
| phy-handle = <&sgmii_phy8_4>; |
| phy-connection-type = "sgmii"; |
| sgmii_phy7_2: ethernet-phy@1d { |
| sgmii_phy7_3: ethernet-phy@1e { |
| sgmii_phy7_4: ethernet-phy@1f { |
| sgmii_phy8_2: ethernet-phy@1d { |
| sgmii_phy8_3: ethernet-phy@1e { |
| sgmii_phy8_4: ethernet-phy@1f { |