| // SPDX-License-Identifier: GPL-2.0-or-later |
| /* |
| * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH |
| * Author: Teresa Remmet <t.remmet@phytec.de> |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/net/ti-dp83867.h> |
| #include "imx8mm.dtsi" |
| |
| / { |
| model = "PHYTEC phyCORE-i.MX8MM"; |
| compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; |
| |
| chosen { |
| stdout-path = &uart3; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| startup-delay-us = <100>; |
| off-on-delay-us = <12000>; |
| }; |
| }; |
| |
| /* ethernet */ |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| phy-reset-duration = <1>; |
| phy-reset-post-delay = <1>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0x0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; |
| enet-phy-lane-no-swap; |
| }; |
| }; |
| }; |
| |
| /* SPI nor flash */ |
| &flexspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexspi0>; |
| status = "okay"; |
| |
| flash0: norflash@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| spi-max-frequency = <80000000>; |
| spi-tx-bus-width = <4>; |
| spi-rx-bus-width = <4>; |
| }; |
| }; |
| |
| /* i2c eeprom */ |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| /* M24C32-D */ |
| i2c_eeprom: eeprom@51 { |
| compatible = "atmel,24c32"; |
| reg = <0x51>; |
| u-boot,i2c-offset-len = <2>; |
| }; |
| |
| /* M24C32-D Identification page */ |
| i2c_eeprom_id: eeprom@59 { |
| compatible = "atmel,24c32"; |
| reg = <0x59>; |
| u-boot,i2c-offset-len = <2>; |
| }; |
| }; |
| |
| /* debug console */ |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| status = "okay"; |
| }; |
| |
| /* sd-card */ |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| bus-width = <4>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| /* eMMC */ |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| /* watchdog */ |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 |
| MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 |
| >; |
| }; |
| |
| pinctrl_flexspi0: flexspi0grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 |
| MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
| MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
| MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
| MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
| MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1grp-gpio { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 |
| MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 |
| MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3grp100mhz { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3grp200mhz { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |