global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/README b/README
index 5ab042a..b095937 100644
--- a/README
+++ b/README
@@ -1441,7 +1441,7 @@
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_SDRAM_BASE:
+- CFG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE:
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 4c696cb..d97a578 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -476,9 +476,9 @@
static void arc_ioc_setup(void)
{
/* IOC Aperture start is equal to DDR start */
- unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+ unsigned int ap_base = CFG_SYS_SDRAM_BASE;
/* IOC Aperture size is equal to DDR size */
- long ap_size = CONFIG_SYS_SDRAM_SIZE;
+ long ap_size = CFG_SYS_SDRAM_SIZE;
/* Unsupported configuration. See [ NOTE 2 ] for more details. */
if (!slc_exists())
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 6b21520..1567857 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -20,7 +20,7 @@
timer_init();
gd->cpu_clk = get_board_sys_clk();
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
cache_init();
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index b4d113d..954fa5f 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -29,7 +29,7 @@
*/
static void __secure ls1_save_ddr_head(void)
{
- const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+ const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ef71e2c..bbaa91f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1441,7 +1441,7 @@
}
#endif
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
@@ -1571,7 +1571,7 @@
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
- CONFIG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE,
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1579,7 +1579,7 @@
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
- CONFIG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi
index 328ba90..d84c10c 100644
--- a/arch/arm/dts/rockchip-optee.dtsi
+++ b/arch/arm/dts/rockchip-optee.dtsi
@@ -32,8 +32,8 @@
arch = "arm";
os = "tee";
compression = "none";
- load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
- entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
+ load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+ entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext {
filename = "tee.bin";
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 3542434..2141a45 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -583,7 +583,7 @@
(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
- (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+ (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
index 4733c07..c63c27d 100644
--- a/arch/arm/include/asm/iproc-common/configs.h
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -12,6 +12,6 @@
#define CONFIG_IPROC
/* Memory Info */
-#define CONFIG_SYS_SDRAM_BASE 0x61000000
+#define CFG_SYS_SDRAM_BASE 0x61000000
#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c
index aca2002..bae1027 100644
--- a/arch/arm/mach-aspeed/ast2500/board_common.c
+++ b/arch/arm/mach-aspeed/ast2500/board_common.c
@@ -31,7 +31,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c
index 82ff219..dc6cdc3 100644
--- a/arch/arm/mach-aspeed/ast2600/board_common.c
+++ b/arch/arm/mach-aspeed/ast2600/board_common.c
@@ -54,7 +54,7 @@
int i = 0, rc;
struct udevice *dev;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
while (1) {
rc = uclass_get_device(UCLASS_MISC, i++, &dev);
diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index 57e51c8..3b91a0c 100644
--- a/arch/arm/mach-at91/arm920t/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S
@@ -114,38 +114,38 @@
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM1
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM1
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
+ .word CFG_SYS_SDRAM
+ .word CFG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
index c51eee2..ecfe589 100644
--- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
@@ -201,38 +201,38 @@
.word CONFIG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL1
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL6
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL7
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL8
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL9
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL2
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL3
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL4
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL5
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL6
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL7
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL8
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL10
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL11
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL12
+ .word CFG_SYS_SDRAM_BASE
+ .word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index 73fdd1f..42078b3 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -26,14 +26,14 @@
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index fa867f2..cad8ccc 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -236,7 +236,7 @@
* better have similar timings, since there's only a single adjustment that is
* shared by both chips).
*/
-const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
/* Test pattern with which RAM will be tested */
static const unsigned int test_pattern[] = {
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a486328..8050406 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -178,7 +178,7 @@
int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
- if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 802cb0e..5d95fb8 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -373,7 +373,7 @@
int i;
for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
- if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index 699a3dc..2ba3245 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c
@@ -172,7 +172,7 @@
* Get actual RAM size, so we can adjust DDR row size for <512M
* memories
*/
- ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
+ ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
if (ram_size < SZ_512M) {
mem_ddr.rowaddr = 14;
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c
index e9d7874..38ead8a 100644
--- a/arch/arm/mach-imx/mx6/opos6ul.c
+++ b/arch/arm/mach-imx/mx6/opos6ul.c
@@ -44,7 +44,7 @@
int board_init(void)
{
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec();
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 6b8f411..cb9801b 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -349,7 +349,7 @@
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
return 0;
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 227706e..d5e1f8e 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -561,7 +561,7 @@
void spl_enable_dcache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
+ phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
dram_init();
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c
index 3d2ff67..2aec962 100644
--- a/arch/arm/mach-k3/r5_mpu.c
+++ b/arch/arm/mach-k3/r5_mpu.c
@@ -24,7 +24,7 @@
O_I_WB_RD_WR_ALLOC, REGION_8MB},
/* U-Boot's code area marking it as WB and Write allocate */
- {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_2GB},
/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 53117c2..ea7d0b9 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -318,7 +318,7 @@
}
ddr3_ecc_init_range(base);
- ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
+ ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c
index 5d837e0..988b057 100644
--- a/arch/arm/mach-mediatek/mt7623/init.c
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -25,7 +25,7 @@
{
u32 i;
- if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) &&
((size_t)preloader_param % sizeof(size_t) == 0) &&
preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
preloader_param->dram_rank_num <=
@@ -35,7 +35,7 @@
for (i = 0; i < preloader_param->dram_rank_num; i++)
gd->ram_size += preloader_param->dram_rank_size[i];
} else {
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SZ_2G);
}
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c
index a895506..d8b10f0 100644
--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c
@@ -14,7 +14,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}
diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c
index cf89e63..fb74b2f 100644
--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -14,7 +14,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c
index cc7f979..8204d96 100644
--- a/arch/arm/mach-mvebu/alleycat5/cpu.c
+++ b/arch/arm/mach-mvebu/alleycat5/cpu.c
@@ -21,8 +21,8 @@
static struct mm_region ac5_mem_map[] = {
{
/* RAM */
- .phys = CONFIG_SYS_SDRAM_BASE,
- .virt = CONFIG_SYS_SDRAM_BASE,
+ .phys = CFG_SYS_SDRAM_BASE,
+ .virt = CFG_SYS_SDRAM_BASE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
@@ -102,7 +102,7 @@
/*
* Config single DRAM bank
*/
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index e3098a7..2c94f89 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -32,7 +32,7 @@
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
+ unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
return (gd->ram_top > top) ? top : gd->ram_top;
}
diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c
index bab375e..6c801bf 100644
--- a/arch/arm/mach-mvebu/armada8k/dram.c
+++ b/arch/arm/mach-mvebu/armada8k/dram.c
@@ -38,7 +38,7 @@
*/
phys_size_t max_bank0_size = SZ_4G - SZ_1G;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size <= max_bank0_size) {
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 44d5214..86755d6 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -72,14 +72,14 @@
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
@@ -520,7 +520,7 @@
sdram_init();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
}
#endif
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c
index 312f868..a6a97af 100644
--- a/arch/arm/mach-omap2/emif-common.c
+++ b/arch/arm/mach-omap2/emif-common.c
@@ -389,7 +389,7 @@
/* Set region1 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
- rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -400,7 +400,7 @@
/* Set region2 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
- rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -1340,7 +1340,7 @@
mapped_size = 0;
section_cnt = 3;
- sys_addr = CONFIG_SYS_SDRAM_BASE;
+ sys_addr = CFG_SYS_SDRAM_BASE;
emif1_size = get_emif_mem_size(EMIF1_BASE);
emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
@@ -1568,7 +1568,7 @@
size_prog = log_2_n_round_down(size_prog);
size_prog = (1 << size_prog);
- size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
size_prog);
/* Compare with the size programmed */
if (size_detect != size_prog) {
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 0551bc1..0f9b915 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -198,11 +198,11 @@
*/
if (sec_mem_start == 0)
sec_mem_start =
- (CONFIG_SYS_SDRAM_BASE + (
+ (CFG_SYS_SDRAM_BASE + (
#if defined(CONFIG_OMAP54XX)
omap_sdram_size()
#else
- get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE)
#endif
- sec_mem_size));
diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
index 4baef2e..f0f46f2 100644
--- a/arch/arm/mach-owl/soc.c
+++ b/arch/arm/mach-owl/soc.c
@@ -50,7 +50,7 @@
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 12f1d7e..e086c47 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -37,7 +37,7 @@
int dram_init_banksize(void)
{
- size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
+ size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE),
(unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
@@ -48,26 +48,26 @@
#ifdef CONFIG_SPL_OPTEE_IMAGE
struct tos_parameter_t *tos_parameter;
- tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
+ tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
- - CONFIG_SYS_SDRAM_BASE;
+ - CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
} else {
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
}
#else
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#endif
#endif
@@ -207,7 +207,7 @@
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+ unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return (gd->ram_top > top) ? top : gd->ram_top;
}
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index b49006c..09e0919 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -46,7 +46,7 @@
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 2c87319..cdf2750 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -33,11 +33,11 @@
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ writel(0, CFG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */
- return readl(CONFIG_SYS_SDRAM_BASE) ==
- readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
+ return readl(CFG_SYS_SDRAM_BASE) ==
+ readl((ulong)CFG_SYS_SDRAM_BASE + offset);
}
#endif
diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
index 56c2d55..3aa3ce7 100644
--- a/arch/arm/mach-sunxi/dram_suniv.c
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -175,9 +175,9 @@
u32 k = 0;
for (k = 0; k < 32; k++)
- writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
+ writel(k, CFG_SYS_SDRAM_BASE + 4 * k);
for (k = 0; k < 32; k++) {
- if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
+ if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k)
return 0;
}
return 1;
@@ -266,11 +266,11 @@
dram_para_setup(para);
dram_scan_readpipe(para);
for (i = 0; i < 32; i++) {
- *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
- *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
+ *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
+ *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
}
for (i = 0; i < 32; i++) {
- val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
+ val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i));
if (val1 == 0x22)
count++;
}
@@ -283,11 +283,11 @@
para->row_width = rowflag;
dram_para_setup(para);
if (colflag == 10) {
- addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
- addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
+ addr1 = CFG_SYS_SDRAM_BASE + 0x400000;
+ addr2 = CFG_SYS_SDRAM_BASE + 0xc00000;
} else {
- addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
- addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
+ addr1 = CFG_SYS_SDRAM_BASE + 0x200000;
+ addr2 = CFG_SYS_SDRAM_BASE + 0x600000;
}
for (i = 0; i < 32; i++) {
*((u8 *)(addr1 + i)) = 0x33;
@@ -319,7 +319,7 @@
static void simple_dram_check(void)
{
- volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
+ volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE;
int i;
for (i = 0; i < 0x40; i++)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 9107b11..4af5922 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -711,7 +711,7 @@
*/
static void mctl_r40_detect_rank_count(struct dram_para *para)
{
- ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
+ ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE +
mctl_calc_rank_size(¶->ranks[0]);
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
@@ -744,10 +744,10 @@
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
{
- mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]);
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]);
if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
- mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
+ mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]);
}
}
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 82d3d33..54bbd8a 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -370,7 +370,7 @@
/* fall back to default DRAM bank size computation */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI
@@ -412,5 +412,5 @@
/* fall back to default usable RAM computation */
- return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
+ return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index ac595ee..3b6518c 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -54,7 +54,7 @@
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
-#if (CONFIG_SYS_SDRAM_BASE == 0)
+#if (CFG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c
index e298579..dac2229 100644
--- a/arch/m68k/cpu/mcf532x/speed.c
+++ b/arch/m68k/cpu/mcf532x/speed.c
@@ -239,7 +239,7 @@
* software workaround for SDRAM opeartion after exiting LIMP
* mode errata
*/
- out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
+ out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE);
#endif
/* wait for DQS logic to relock */
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index f2eb6fc..672aa0b 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -338,9 +338,9 @@
#ifdef CONFIG_PCI
#define CFG_SYS_PCI_BAR0 (0x40000000)
-#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
-#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M547x */
diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c
index 0c2c1a9..28fe803 100644
--- a/arch/m68k/lib/traps.c
+++ b/arch/m68k/lib/traps.c
@@ -62,7 +62,7 @@
int arch_initr_trap(void)
{
- trap_init(CONFIG_SYS_SDRAM_BASE);
+ trap_init(CFG_SYS_SDRAM_BASE);
return 0;
}
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index 7577fdd..7a682f2 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -135,7 +135,7 @@
int arch_initr_trap(void)
{
- trap_init(CONFIG_SYS_SDRAM_BASE);
+ trap_init(CFG_SYS_SDRAM_BASE);
return 0;
}
diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
index cff98b0..15d1eff 100644
--- a/arch/mips/mach-jz47xx/jz4780/jz4780.c
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c
@@ -78,7 +78,7 @@
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
- return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
+ return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024);
}
int print_cpuinfo(void)
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 5bc3100..d484eb92 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -17,16 +17,16 @@
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
+#if CFG_SYS_SDRAM_SIZE <= SZ_64M
#define MSCC_RAM_TLB_SIZE SZ_64M
#define MSCC_ATTRIB2 MMU_REGIO_INVAL
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_128M
#define MSCC_RAM_TLB_SIZE SZ_64M
#define MSCC_ATTRIB2 MMU_REGIO_RW
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_256M
#define MSCC_RAM_TLB_SIZE SZ_256M
#define MSCC_ATTRIB2 MMU_REGIO_INVAL
-#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
+#elif CFG_SYS_SDRAM_SIZE <= SZ_512M
#define MSCC_RAM_TLB_SIZE SZ_256M
#define MSCC_ATTRIB2 MMU_REGIO_RW
#else
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index c53a420..f7fbd33 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -67,6 +67,6 @@
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
index d52eabb..75fb3ca 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -13,7 +13,7 @@
#include <mach/common.h>
#define MIPS_VCOREIII_MEMORY_DDR3
-#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE
+#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */
diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S
index 3cad356..6b9f253 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/start.S
+++ b/arch/mips/mach-mtmips/mt7621/spl/start.S
@@ -18,7 +18,7 @@
#include "dram.h"
#ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c
index 9c5789b..85cb084 100644
--- a/arch/mips/mach-octeon/dram.c
+++ b/arch/mips/mach-octeon/dram.c
@@ -81,7 +81,7 @@
{
if (IS_ENABLED(CONFIG_RAM_OCTEON)) {
/* Map a maximum of 256MiB - return not size but address */
- return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size,
+ return CFG_SYS_SDRAM_BASE + min(gd->ram_size,
UBOOT_RAM_SIZE_MAX);
} else {
return gd->ram_top;
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c
index 4dd9c10..8554450 100644
--- a/arch/nios2/cpu/cpu.c
+++ b/arch/nios2/cpu/cpu.c
@@ -73,7 +73,7 @@
if (ret)
return ret;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#ifndef CONFIG_ROM_STUBS
copy_exception_trampoline();
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index e12043b..6d1c6b0 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -288,7 +288,7 @@
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+ ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index b0363c9..6acd31d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -424,7 +424,7 @@
defined(CONFIG_ARCH_QEMU_E500)
gd->ram_size = fsl_ddr_sdram_size();
#else
- gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
return 0;
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index f109ecb..44f8ed8 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -195,7 +195,7 @@
/* use last 4K of mapped memory */
bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
- CONFIG_SYS_SDRAM_BASE - 4096;
+ CFG_SYS_SDRAM_BASE - 4096;
if (pagesize)
*pagesize = 4096;
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
index d917e9d..71496ab 100644
--- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -16,7 +16,7 @@
int j;
tbl->start_addr[i] =
- (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
+ (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE);
tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 8ae8d8a..1df0822 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -126,7 +126,7 @@
#ifdef DEBUG
if (((u64)bootmap_base + bootm_size) >
- (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size))
+ (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size))
puts("WARNING: bootm_low + bootm_size exceed total memory\n");
if ((bootmap_base + bootm_size) > get_effective_memsize())
puts("WARNING: bootm_low + bootm_size exceed eff. memory\n");
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index a681e47..dd7978c 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -448,7 +448,7 @@
{
state = &main_state;
- state->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ state->ram_size = CFG_SYS_SDRAM_SIZE;
state->ram_buf = os_malloc(state->ram_size);
if (!state->ram_buf) {
printf("Out of memory\n");
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 2051207..88b57bf 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -25,7 +25,7 @@
};
memory {
- reg = <0 CONFIG_SYS_SDRAM_SIZE>;
+ reg = <0 CFG_SYS_SDRAM_SIZE>;
};
reserved-memory {
diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts
index 3eb0457..a9cd790 100644
--- a/arch/sandbox/dts/sandbox64.dts
+++ b/arch/sandbox/dts/sandbox64.dts
@@ -21,7 +21,7 @@
};
memory {
- reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>;
+ reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>;
};
reserved-memory {
diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 85ee547..d360eea 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -18,7 +18,7 @@
MEMORY
{
- ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE
+ ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE
}
ENTRY(_start)
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index 3fa093a..b31fa6d 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -11,8 +11,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c
index a5fad6c..b205e5e 100644
--- a/arch/sh/lib/bootm.c
+++ b/arch/sh/lib/bootm.c
@@ -88,7 +88,7 @@
set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
set_sh_linux_param((unsigned long)param + INITRD_START,
- GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+ GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE));
set_sh_linux_param((unsigned long)param + INITRD_SIZE,
images->rd_end - images->rd_start);
}
diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c
index a09e103..98d9753 100644
--- a/arch/xtensa/cpu/cpu.c
+++ b/arch/xtensa/cpu/cpu.c
@@ -45,7 +45,7 @@
int arch_cpu_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
index c8dc186..36945bb 100644
--- a/board/BuR/brppt1/board.c
+++ b/board/BuR/brppt1/board.c
@@ -150,7 +150,7 @@
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index 2b08930..f9a37e7 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -40,8 +40,8 @@
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
asm (" nop");
-#ifdef CONFIG_SYS_SDRAM_BASE0
- MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
+#ifdef CFG_SYS_SDRAM_BASE0
+ MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)|
MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
MCFSDRAMC_DACR_PS_32;
asm (" nop");
@@ -54,7 +54,7 @@
for (i = 0; i < 10; i++)
asm (" nop");
- *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
+ *(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
asm (" nop");
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
asm (" nop");
@@ -65,12 +65,12 @@
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
asm (" nop");
/* write SDRAM mode register */
- *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
+ *(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
asm (" nop");
- size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
+ size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024;
#endif
-#ifdef CONFIG_SYS_SDRAM_BASE1xx
- MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+#ifdef CFG_SYS_SDRAM_BASE1xx
+ MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
@@ -79,15 +79,15 @@
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
- *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+ *(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
- *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
- size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+ *(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+ size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
gd->ram_size = size;
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index ff1c4cb..a52a032 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -139,7 +139,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
index 619cd6c..0c4f8e0 100644
--- a/board/Marvell/mvebu_alleycat-5/board.c
+++ b/board/Marvell/mvebu_alleycat-5/board.c
@@ -7,7 +7,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index c6ecc32..45fe3e5 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -80,7 +80,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c
index 77c7dd7..a8899af 100644
--- a/board/Marvell/mvebu_armada-8k/board.c
+++ b/board/Marvell/mvebu_armada-8k/board.c
@@ -150,7 +150,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c
index 059ebf8..2246535 100644
--- a/board/Marvell/octeontx/board.c
+++ b/board/Marvell/octeontx/board.c
@@ -63,7 +63,7 @@
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
- gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();
return 0;
diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c
index 63aa2d6..e7899f4 100644
--- a/board/Marvell/octeontx2/board.c
+++ b/board/Marvell/octeontx2/board.c
@@ -105,7 +105,7 @@
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
- gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
index 953e9db..3d20cfb 100644
--- a/board/Marvell/octeontx2_cn913x/board.c
+++ b/board/Marvell/octeontx2_cn913x/board.c
@@ -34,7 +34,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 4959a7f..ad02cf1 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -137,7 +137,7 @@
int dram_init (void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
@@ -160,12 +160,12 @@
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
0x01000000 << sdram_shift);
}
#else
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index 1c83019..763131c 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -73,7 +73,7 @@
int dram_init(void)
{
gd->ram_size =
- get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+ get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
index 3e2f79a..43563c4 100644
--- a/board/astro/mcf5373l/mcf5373l.c
+++ b/board/astro/mcf5373l/mcf5373l.c
@@ -39,12 +39,12 @@
* GPIO configuration for bus should be set correctly from reset,
* so we do not care! First, set up address space: at this point,
* we should be running from internal SRAM;
- * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+ * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM,
* and do not care where it is
*/
- __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+ __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
&sdp->cs0);
- __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+ __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
&sdp->cs1);
/*
* I am not sure from the data sheet, but it seems burst length
@@ -72,7 +72,7 @@
*/
__raw_writel(0x71462C00, &sdp->ctrl);
/* Dummy write to start SDRAM */
- writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0, CFG_SYS_SDRAM_BASE);
#endif
/*
@@ -82,8 +82,8 @@
* (Do not rely on the SDCS register(s) being set to 0x00000000
* during reset as stated in the data sheet.)
*/
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- 0x80000000 - CONFIG_SYS_SDRAM_BASE);
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ 0x80000000 - CFG_SYS_SDRAM_BASE);
return 0;
}
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index d2c6ada..b8e02f4 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -81,7 +81,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9260ek_nand_hw_init();
@@ -92,8 +92,8 @@
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 2992353..eab3a13 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -156,7 +156,7 @@
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
#endif
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init();
@@ -176,8 +176,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index b2b7093..15f20b6 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -95,7 +95,7 @@
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
@@ -108,8 +108,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 2f3a772..f53c1cf 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -168,7 +168,7 @@
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9m10g45ek_nand_hw_init();
@@ -181,8 +181,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 5468519..a3e294c 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -99,7 +99,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
at91sam9n12ek_nand_hw_init();
@@ -114,8 +114,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index bca7c8d..11725f7 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -93,7 +93,7 @@
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9rlek_nand_hw_init();
@@ -104,7 +104,7 @@
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 817aa2f..ab666b6 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -115,7 +115,7 @@
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9x5ek_nand_hw_init();
@@ -129,8 +129,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c
index 786de18..a3e35f3 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -120,7 +120,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
sam9x60ek_nand_hw_init();
@@ -130,7 +130,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index 6524867..6e41017 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -65,7 +65,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -84,8 +84,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c
index 0207770..fabe492 100644
--- a/board/atmel/sama5d2_icp/sama5d2_icp.c
+++ b/board/atmel/sama5d2_icp/sama5d2_icp.c
@@ -54,7 +54,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -63,8 +63,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
index 16e9183..854715e 100644
--- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
+++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
@@ -115,7 +115,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -130,8 +130,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index a778f26..ce73a80 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -94,7 +94,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d3_xplained_nand_hw_init();
@@ -110,8 +110,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 008f1db..660a6b9 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -147,7 +147,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d3xek_nand_hw_init();
@@ -166,8 +166,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 4058594..780aba1 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -121,7 +121,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d4_xplained_nand_hw_init();
@@ -135,8 +135,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index ef5a8a0..2226906 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -107,7 +107,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init();
@@ -121,8 +121,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c
index 7d83e76..295fd07 100644
--- a/board/atmel/sama7g5ek/sama7g5ek.c
+++ b/board/atmel/sama7g5ek/sama7g5ek.c
@@ -67,7 +67,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
board_leds_init();
@@ -76,7 +76,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index 35c74ba..9b42299 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -307,7 +307,7 @@
gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
ret = gurnard_nand_hw_init();
@@ -407,8 +407,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index bdf8d06..c31e2c8 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -182,7 +182,7 @@
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index a7a9775..e3a9c00 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -449,7 +449,7 @@
if (read_eeprom() < 0)
puts("EEPROM Content Invalid.\n");
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index 6064eb4..e91fa40 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c
@@ -26,7 +26,7 @@
* Address of boot parameters passed to kernel
* Use default offset 0x100
*/
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
@@ -36,14 +36,14 @@
*/
int dram_init(void)
{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
index c89ad0b..3d31776 100644
--- a/board/calao/usb_a9263/usb_a9263.c
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -95,7 +95,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
usb_a9263_nand_hw_init();
@@ -111,8 +111,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
index 3e24188..69a9df9 100644
--- a/board/cobra5272/cobra5272.c
+++ b/board/cobra5272/cobra5272.c
@@ -28,7 +28,7 @@
/* Dummy write to start SDRAM */
*((volatile unsigned long *) 0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c
index bcfe1bf..5df378a 100644
--- a/board/compulab/cm_t43/cm_t43.c
+++ b/board/compulab/cm_t43/cm_t43.c
@@ -45,7 +45,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
set_i2c_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c
index e67bf81..a6223a4 100644
--- a/board/compulab/cm_t43/spl.c
+++ b/board/compulab/cm_t43/spl.c
@@ -119,7 +119,7 @@
unsigned long ram_size;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
- ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x80000000 ||
ram_size == 0x40000000 ||
ram_size == 0x20000000)
@@ -127,7 +127,7 @@
ddr3_emif_regs.sdram_config = 0x638453B2;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
- ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x08000000)
return;
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
index c20e871..e95e04a 100644
--- a/board/cssi/MCR3000/MCR3000.c
+++ b/board/cssi/MCR3000/MCR3000.c
@@ -114,7 +114,7 @@
out_be32(&memctl->memc_mcr, 0x80002038);
udelay(200);
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SDRAM_MAX_SIZE);
return 0;
diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
index 72cf46c..2b03e48 100644
--- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
+++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
@@ -29,13 +29,13 @@
int
board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000;
return 0;
}
int
dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M);
return 0;
}
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 1054837..648d77f 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -286,7 +286,7 @@
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index a5d79d8..913c2ea 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -85,8 +85,8 @@
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
@@ -135,7 +135,7 @@
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Set adress of boot parameters. */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Initialize UARTs and power management. */
ethernut5_power_init();
#ifdef CONFIG_CMD_NAND
diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c
index 16237e2..3df3e41 100644
--- a/board/emulation/qemu-arm/qemu-arm.c
+++ b/board/emulation/qemu-arm/qemu-arm.c
@@ -126,7 +126,7 @@
{
*err = 0;
/* QEMU loads a generated DTB for us at the start of RAM. */
- return (void *)CONFIG_SYS_SDRAM_BASE;
+ return (void *)CFG_SYS_SDRAM_BASE;
}
void enable_caches(void)
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index 98043b0..2304e9e 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -264,7 +264,7 @@
meesc_ethercat_hw_init();
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
meesc_nand_hw_init();
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index f5bed6c..46ffd81 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -61,7 +61,7 @@
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
- dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+ dst = (u64 *)CFG_SYS_SDRAM_BASE;
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst++ = *src++;
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index 71922aa..d3323b9 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -50,7 +50,7 @@
/* get the address of ddr date from SPARECR3 */
src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
- dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
+ dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst-- = *src--;
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index bc37c55..f2b8750 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -102,7 +102,7 @@
else
gd->ram_size = SYS_SDRAM_SIZE_512;
#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
}
return 0;
@@ -139,7 +139,7 @@
gd->ram_size = SYS_SDRAM_SIZE_512;
}
#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
mmdc_init(&mparam);
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 3f70fbc..f17a6c1 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -66,7 +66,7 @@
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -90,7 +90,7 @@
};
mmdc_init(&mparam);
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 456609d..62c935e 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -113,7 +113,7 @@
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -140,7 +140,7 @@
mmdc_init(&mparam);
#endif
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 66fe151..4e70acc 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -192,7 +192,7 @@
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index 4325439..d144f25 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -47,7 +47,7 @@
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 33027ad..8b74d45 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -162,7 +162,7 @@
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 7bfb455..6125c9e 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -29,7 +29,7 @@
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,35 +37,35 @@
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
- out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index e7c7a94..44161a0 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -44,7 +44,7 @@
GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
GPIO_PAR_SDRAM_SDCS(3));
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -61,7 +61,7 @@
/* Initialize DACR0 */
out_be32(&sdram->dacr0,
- SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
SDRAMC_DARCn_PS_32);
asm("nop");
@@ -80,7 +80,7 @@
}
/* Write to this block to initiate precharge */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
@@ -95,7 +95,7 @@
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index 48c0079..efff055 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -86,7 +86,7 @@
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 85f5f0c..179a2a2 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -47,7 +47,7 @@
__asm__("nop");
/* Initialize DMR0 */
- dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+ dramsize = (CFG_SYS_SDRAM_SIZE << 20);
temp = (dramsize - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, temp | 1);
__asm__("nop");
@@ -57,7 +57,7 @@
__asm__("nop");
/* Write to this block to initiate precharge */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
mb();
__asm__("nop");
@@ -74,7 +74,7 @@
mbar_readLong(MCFSIM_DACR0) | 0x0040);
__asm__("nop");
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
mb();
}
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 9580cf2..3c20a23 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -30,7 +30,7 @@
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 1c4fb72..00fa35c 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -35,7 +35,7 @@
out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
- out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE);
out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
@@ -49,34 +49,34 @@
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
setbits_be32(&sdp->sdmr,
MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
out_be32(&sdp->sdmr, 0x058d0000);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
@@ -91,7 +91,7 @@
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3));
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index e1ea9b3..53e0f20 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -21,7 +21,7 @@
{
u32 dramsize, i, dramclk;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -40,7 +40,7 @@
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
- | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+ | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
@@ -62,7 +62,7 @@
}
/* Write to this block to initiate precharge */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
@@ -79,7 +79,7 @@
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 8a7d8ca..0de36a7 100644
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README
@@ -106,7 +106,7 @@
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index c9f8935..76ebc0a 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -29,7 +29,7 @@
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,35 +37,35 @@
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
- out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index 7a75b04..b278dbf 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -29,7 +29,7 @@
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,30 +37,30 @@
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index bba5420..bfbcd5d 100644
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README
@@ -105,7 +105,7 @@
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index cfa5ca4..0e9eec3 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -29,7 +29,7 @@
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,30 +37,30 @@
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 2650d30..85d43cc 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -97,10 +97,10 @@
int fixed_sdram(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
+ u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -127,7 +127,7 @@
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
- return CONFIG_SYS_SDRAM_SIZE >> 20;
+ return CFG_SYS_SDRAM_SIZE >> 20;
}
#endif /*!CONFIG_SYS_SPD_EEPROM */
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 46095ac..86364ac 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -30,7 +30,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 038e673..f896fd7 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -244,7 +244,7 @@
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c
index 70e4dfc..9541972 100644
--- a/board/friendlyarm/nanopi2/board.c
+++ b/board/friendlyarm/nanopi2/board.c
@@ -507,7 +507,7 @@
/* u-boot dram initialize */
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -518,10 +518,10 @@
unsigned int reg_val = readl(SCR_USER_SIG6_READ);
/* set global data memory */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
/* Number of Row: 14 bits */
if ((reg_val >> 28) == 14)
diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c
index c6eb11e..d9dfb25 100644
--- a/board/gardena/smart-gateway-at91sam/board.c
+++ b/board/gardena/smart-gateway-at91sam/board.c
@@ -45,15 +45,15 @@
int board_init(void)
{
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 47b8804..4889a6a 100644
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c
@@ -34,11 +34,11 @@
static long fixed_sdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
+ u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_SDRAM_BASE & 0xfffff000);
+ CFG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -66,7 +66,7 @@
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+ return get_ram_size(CFG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index 6423c1e..b472ca5 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c
@@ -95,7 +95,7 @@
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index 5b245cb..8532225 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c
@@ -27,7 +27,7 @@
{
DECLARE_GLOBAL_DATA_PTR;
- if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+ if (gd->ram_top < CFG_SYS_SDRAM_BASE) {
/* 2GB wrapped around to 0 */
return CKSEG0ADDR(256 << 20);
}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index bed2497..aa910bf 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -118,7 +118,7 @@
/* setup basic address decode */
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
- li t2, -CONFIG_SYS_SDRAM_SIZE
+ li t2, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -168,7 +168,7 @@
sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_SDRAM_SIZE
+ li t1, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 9853a0b..4a72ab5 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -94,7 +94,7 @@
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
index 6a83637..7122692 100644
--- a/board/imgtec/xilfpga/xilfpga.c
+++ b/board/imgtec/xilfpga/xilfpga.c
@@ -19,7 +19,7 @@
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+ gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
return 0;
}
diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index 7dbb3a9..f3a0de3 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c
@@ -412,7 +412,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30);
return 0;
}
diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c
index 02ae7df..5462a3d 100644
--- a/board/isee/igep003x/board.c
+++ b/board/isee/igep003x/board.c
@@ -185,7 +185,7 @@
*/
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index c8138dc..0252ada 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -52,7 +52,7 @@
char envval[16];
char *p;
- pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+ pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
sprintf(envval, "0x%x", pnvramaddr);
env_set("pnvramaddr", envval);
@@ -65,7 +65,7 @@
CONFIG_KM_PNVRAM) / 0x400;
env_set_ulong("pram", pram);
- varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
+ varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
sprintf(envval, "0x%x", varaddr);
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 6a7b848..ddd8f7a 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -142,10 +142,10 @@
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+ msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
enable_addr_trans();
msize /= (1024 * 1024);
- if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
+ if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++)
@@ -169,7 +169,7 @@
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
+ CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c
index 4ec60f1..556d39d 100644
--- a/board/keymile/pg-wcom-ls102xa/ddr.c
+++ b/board/keymile/pg-wcom-ls102xa/ddr.c
@@ -84,7 +84,7 @@
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
index 3719bcf..1a7fa3f 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
@@ -184,7 +184,7 @@
{
/* Define only 1MiB range for mem_regions at the middle of the RAM */
/* For 1GiB range mem_regions takes approx. 4min */
- *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
+ *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
*size = 1 << 20;
return 0;
}
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index d47c7b5..b3c176d 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c
@@ -164,7 +164,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if !CONFIG_IS_ENABLED(DM_SPI)
vinco_spi0_hw_init();
@@ -188,8 +188,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c
index 0504d61..ff233e9 100644
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -14,7 +14,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c
index 755e879..ec10f77 100644
--- a/board/mediatek/mt7623/mt7623_rfb.c
+++ b/board/mediatek/mt7623/mt7623_rfb.c
@@ -12,7 +12,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c
index d1bca6d..55f7696 100644
--- a/board/mediatek/mt7629/mt7629_rfb.c
+++ b/board/mediatek/mt7629/mt7629_rfb.c
@@ -11,7 +11,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c
index fce5de6..2490b15 100644
--- a/board/mediatek/mt8518/mt8518_ap1.c
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -14,7 +14,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
debug("gd->fdt_blob is %p\n", gd->fdt_blob);
return 0;
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
index 6abf08b..84b95be 100644
--- a/board/mscc/jr2/jr2.c
+++ b/board/mscc/jr2/jr2.c
@@ -28,7 +28,7 @@
ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index 76e3f2e..48170b3 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -29,7 +29,7 @@
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 2a75ec2..f261346 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -77,7 +77,7 @@
ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
index 87e7907..99d5f5b 100644
--- a/board/mscc/serval/serval.c
+++ b/board/mscc/serval/serval.c
@@ -22,7 +22,7 @@
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c
index bd8c7e8..4999316 100644
--- a/board/mscc/servalt/servalt.c
+++ b/board/mscc/servalt/servalt.c
@@ -22,7 +22,7 @@
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}
diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
index d97ebd0..e84dd25 100644
--- a/board/phytec/phycore_am335x_r2/board.c
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -166,7 +166,7 @@
0);
/* Detect memory physically present */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
/* Reconfigure memory for actual detected size */
@@ -269,7 +269,7 @@
*/
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c
index 4fbe1e5..75d2636 100644
--- a/board/phytium/pomelo/pomelo.c
+++ b/board/phytium/pomelo/pomelo.c
@@ -24,7 +24,7 @@
ddr_init();
gd->mem_clk = 0;
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
sec_init();
debug("PBF relocate done\n");
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 3b60afc..85fbaf0 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -70,7 +70,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index a365269..ea09057 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -312,7 +312,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 6197e54..2d1435a 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -78,7 +78,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c
index 199ec4a..f609e4f 100644
--- a/board/renesas/grpeach/grpeach.c
+++ b/board/renesas/grpeach/grpeach.c
@@ -20,7 +20,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+ gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0;
}
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 87607df..c3ebcd3 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -80,7 +80,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 8e24ac0..1437875 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -89,7 +89,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index 1a3a4c1..db1fb4b 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c
@@ -78,7 +78,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 4558070..6ecebfe 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -71,7 +71,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");
diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 56bdb34..f069ecc 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -88,7 +88,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
cpld_init();
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 23b55e3..c56582a 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -126,7 +126,7 @@
/* arch number of AT91SAM9M10G45EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
pm9g45_nand_hw_init();
@@ -141,15 +141,15 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 5320c1f..a992dc6 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -46,7 +46,7 @@
u32 addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
}
return 0;
@@ -64,7 +64,7 @@
u32 addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
gd->bd->bi_dram[i].start = addr;
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 943b498..16ce5cb 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -122,7 +122,7 @@
unsigned long addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
}
return 0;
@@ -134,7 +134,7 @@
unsigned long addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
gd->bd->bi_dram[i].start = addr;
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 4c655df..8b953f9 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -115,7 +115,7 @@
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -173,7 +173,7 @@
int init_addr_map(void)
{
if (IS_ENABLED(CONFIG_ADDR_MAP))
- addrmap_set_entry(0, 0, CONFIG_SYS_SDRAM_SIZE, 0);
+ addrmap_set_entry(0, 0, CFG_SYS_SDRAM_SIZE, 0);
return 0;
}
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 85025f2..2efede6 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -85,7 +85,7 @@
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR);
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index d876280..569b86d 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -262,7 +262,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* we have to request the gpios again after relocation */
corvus_request_gpio();
@@ -287,8 +287,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index b965ae9..8f4b0ea 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -146,7 +146,7 @@
dram_init();
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
/* Bank 1 declares the memory available in the DDR high region */
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index ce6c877..3d0f734 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -167,7 +167,7 @@
#endif
/* Adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
smartweb_nand_hw_init();
smartweb_macb_hw_init();
@@ -177,8 +177,8 @@
int dram_init(void)
{
gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ (void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 47d3f6a..1eee972 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -185,8 +185,8 @@
sdramc_configure(AT91_SDRAMC_NC_10);
/* Do memtest for 128MB */
- ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
/*
* If 32MB or 16MB should be supported check also for
@@ -306,7 +306,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
taurus_request_gpio();
#ifdef CONFIG_CMD_NAND
@@ -326,8 +326,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
index a218278..79e492f 100644
--- a/board/sipeed/maix/maix.c
+++ b/board/sipeed/maix/maix.c
@@ -11,7 +11,7 @@
phys_size_t get_effective_memsize(void)
{
- return CONFIG_SYS_SDRAM_SIZE;
+ return CFG_SYS_SDRAM_SIZE;
}
static int sram_init(void)
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 04527cf..ad49999 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -51,11 +51,11 @@
asm ("sync; isync; msync");
udelay(1000);
- if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
+ if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) {
/*
* OK, size detected -> all done
*/
- return CONFIG_SYS_SDRAM_SIZE<<20;
+ return CFG_SYS_SDRAM_SIZE<<20;
}
return 0; /* nothing found ! */
diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c
index 2299227..b3f9550 100644
--- a/board/softing/vining_fpga/socfpga.c
+++ b/board/softing/vining_fpga/socfpga.c
@@ -30,7 +30,7 @@
status_led_set(2, CONFIG_LED_STATUS_ON);
/* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
if (!ret)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 8e80ca6..7c44379 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -107,7 +107,7 @@
{
u32 max_size = imx_ddr_size();
- gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE,
(u32)max_size);
return 0;
@@ -288,7 +288,7 @@
int ret = 0;
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_VIDEO_IPUV3
ret = setup_display();
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index beab4e9..5426fc4 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -88,7 +88,7 @@
*/
out_be32(&dc->dacr0, 0x00003304);
- dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+ dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
out_be32(&dc->dmr0, dramsize|1);
/* issue a PRECHARGE ALL */
@@ -102,8 +102,8 @@
out_be32(&dc->dacr0, 0x0000b344);
out_be32((u32 *)0x00000c00, 0xbeaddeed);
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c
index d48da48..475e3ed 100644
--- a/board/sysam/stmark2/stmark2.c
+++ b/board/sysam/stmark2/stmark2.c
@@ -35,7 +35,7 @@
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
gd->ram_size = dramsize;
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 3a447ca..8d9eedb 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -144,7 +144,7 @@
int board_init(void)
{
/* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index b7ddc3b..839a692 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -238,7 +238,7 @@
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b97fedd..9e58281 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -704,7 +704,7 @@
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 529129e..d0b7a14 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -639,7 +639,7 @@
u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
modena_init0_bw_integer, modena_init0_watermark_0;
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
/*
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index cfc825e..652c40f 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -661,7 +661,7 @@
int board_init(void)
{
gpmc_init();
- gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+ gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0;
}
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 34ec391..b266ccb 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -75,13 +75,13 @@
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index a854d61..1c00e25 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -644,7 +644,7 @@
ram_size = board_ti_get_emif_size();
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
if (ram_size > CONFIG_MAX_MEM_MAPPED) {
gd->bd->bi_dram[1].start = 0x200000000;
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index d6e431e..d4e672a 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -71,13 +71,13 @@
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index e09adc8..4d28582 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -60,13 +60,13 @@
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 51e8de4..34818736 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -46,7 +46,7 @@
ddr3_size = ddr3_init();
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
if (!(board_is_k2g_ice() || board_is_k2g_i1()))
@@ -71,7 +71,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
@@ -120,7 +120,7 @@
/* adjust memory start address for LPAE */
if (lpae) {
- start[0] -= CONFIG_SYS_SDRAM_BASE;
+ start[0] -= CFG_SYS_SDRAM_BASE;
start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
}
@@ -174,11 +174,11 @@
"linux,initrd-end", NULL);
if (prop1 && prop2) {
initrd_start = __be64_to_cpu(*prop1);
- initrd_start -= CONFIG_SYS_SDRAM_BASE;
+ initrd_start -= CFG_SYS_SDRAM_BASE;
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be64_to_cpu(*prop2);
- initrd_end -= CONFIG_SYS_SDRAM_BASE;
+ initrd_end -= CFG_SYS_SDRAM_BASE;
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
@@ -221,7 +221,7 @@
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
- *reserve_start -= CONFIG_SYS_SDRAM_BASE;
+ *reserve_start -= CFG_SYS_SDRAM_BASE;
*reserve_start +=
CONFIG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index 2d42af6..8c70835 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -27,7 +27,7 @@
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
index 9d4ffb0..efef855 100644
--- a/board/timll/devkit3250/devkit3250.c
+++ b/board/timll/devkit3250/devkit3250.c
@@ -56,7 +56,7 @@
int board_init(void)
{
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_SYS_FLASH_CFI
/* Use 16-bit memory interface for NOR Flash */
@@ -76,8 +76,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 96d0185..3c7cfa3 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -79,7 +79,7 @@
int dram_init(void)
{
/* use the DDR controllers configured size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
(ulong)imx_ddr_size());
return 0;
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 475250d..65e0e9a 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -73,7 +73,7 @@
int dram_init(void)
{
/* use the DDR controllers configured size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
(ulong)imx_ddr_size());
return 0;
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 07fe454..f335d5b 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -266,7 +266,7 @@
hw_watchdog_init();
#endif
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c
index 5d12f84..c8e791a 100644
--- a/board/work-microwave/work_92105/work_92105.c
+++ b/board/work-microwave/work_92105/work_92105.c
@@ -67,15 +67,15 @@
{
reset_periph();
/* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 17ee541..df4c457 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -105,7 +105,7 @@
return board_late_init_xilinx();
}
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
@@ -123,8 +123,8 @@
#else
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
zynq_ddrc_init();
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 579708d..e3f70c4 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -236,7 +236,7 @@
return ret;
}
-#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
int ret;
@@ -261,7 +261,7 @@
#else
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
mem_map_fill();
@@ -271,8 +271,8 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/boot/image-board.c b/boot/image-board.c
index 34d1e5f..8813be5 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -116,8 +116,8 @@
return tmp;
}
-#if defined(CONFIG_SYS_SDRAM_BASE)
- return CONFIG_SYS_SDRAM_BASE;
+#if defined(CFG_SYS_SDRAM_BASE)
+ return CFG_SYS_SDRAM_BASE;
#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV)
return gd->bd->bi_dram[0].start;
#else
diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c
index aaaedfe..bbd406f 100644
--- a/cmd/ti/ddr3.c
+++ b/cmd/ti/ddr3.c
@@ -20,7 +20,7 @@
#ifdef CONFIG_ARCH_KEYSTONE
#include <asm/arch/ddr3.h>
-#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
+#define DDR_MIN_ADDR CFG_SYS_SDRAM_BASE
#define STACKSIZE (512 << 10) /* 512 KiB */
#define DDR_REMAP_ADDR 0x80000000
@@ -247,9 +247,9 @@
/* Check in ecc address range 1 */
if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
- + CONFIG_SYS_SDRAM_BASE;
+ + CFG_SYS_SDRAM_BASE;
end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
- CONFIG_SYS_SDRAM_BASE;
+ CFG_SYS_SDRAM_BASE;
if ((addr >= start_addr) && (addr <= end_addr))
/* addr within ecc address range 1 */
return 1;
@@ -259,9 +259,9 @@
if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
range = readl(&emif->emif_ecc_address_range_2);
start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
- + CONFIG_SYS_SDRAM_BASE;
+ + CFG_SYS_SDRAM_BASE;
end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
- CONFIG_SYS_SDRAM_BASE;
+ CFG_SYS_SDRAM_BASE;
if ((addr >= start_addr) && (addr <= end_addr))
/* addr within ecc address range 2 */
return 1;
@@ -309,11 +309,11 @@
start_addr = hextoul(argv[2], NULL);
end_addr = hextoul(argv[3], NULL);
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
+ if ((start_addr < CFG_SYS_SDRAM_BASE) ||
+ (start_addr > (CFG_SYS_SDRAM_BASE +
get_effective_memsize() - 1)) ||
- (end_addr < CONFIG_SYS_SDRAM_BASE) ||
- (end_addr > (CONFIG_SYS_SDRAM_BASE +
+ (end_addr < CFG_SYS_SDRAM_BASE) ||
+ (end_addr > (CFG_SYS_SDRAM_BASE +
get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
puts("Invalid start or end address!\n");
return cmd_usage(cmdtp);
diff --git a/common/board_f.c b/common/board_f.c
index e6117a7..aab1130 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -329,12 +329,12 @@
/* Get the top of usable RAM */
__weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
-#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
+#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
/*
* Detect whether we have so much RAM that it goes past the end of our
* 32-bit address space. If so, clip the usable RAM so it doesn't.
*/
- if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
+ if (gd->ram_top < CFG_SYS_SDRAM_BASE)
/*
* Will wrap back to top of 32-bit space when reservations
* are made.
@@ -369,8 +369,8 @@
*/
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
#endif
-#ifdef CONFIG_SYS_SDRAM_BASE
- gd->ram_base = CONFIG_SYS_SDRAM_BASE;
+#ifdef CFG_SYS_SDRAM_BASE
+ gd->ram_base = CFG_SYS_SDRAM_BASE;
#endif
gd->ram_top = gd->ram_base + get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 15806df..584503e 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -142,21 +142,21 @@
cache-related registers config
CONFIG_SYS_CACHE_ACRX:
cache-related registers config
-CONFIG_SYS_SDRAM_BASE:
+CFG_SYS_SDRAM_BASE:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_SIZE:
+CFG_SYS_SDRAM_SIZE:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_BASEX:
+CFG_SYS_SDRAM_BASEX:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG1:
+CFG_SYS_SDRAM_CFG1:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG2:
+CFG_SYS_SDRAM_CFG2:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CTRL:
+CFG_SYS_SDRAM_CTRL:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_MODE:
+CFG_SYS_SDRAM_MODE:
SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_EMOD:
+CFG_SYS_SDRAM_EMOD:
SDRAM config for SDRAM controller-specific registers, please
see arch/m68k/cpu/<specific_cpu>/start.S files to see how
these options are used.
diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst
index 35defb0..34a75e7 100644
--- a/doc/arch/nios2.rst
+++ b/doc/arch/nios2.rst
@@ -96,8 +96,8 @@
.. code-block:: c
- #define CONFIG_SYS_SDRAM_BASE 0xc8000000
- #define CONFIG_SYS_SDRAM_SIZE 0x08000000
+ #define CFG_SYS_SDRAM_BASE 0xc8000000
+ #define CFG_SYS_SDRAM_SIZE 0x08000000
You will need to change the environment variables location and setting,
too. You may change other configs to fit your board.
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 5e8fb7a..9dada5e 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -130,7 +130,7 @@
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 3c1f7a1..f8d1468 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -230,7 +230,7 @@
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index fcff223..4975dbb 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -30,7 +30,7 @@
*/
#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
-#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
#else
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 0f2dc24..1c4a1ca 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -162,7 +162,7 @@
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index a14c766..c40cd76 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h
@@ -19,10 +19,10 @@
#define FAR_END_DIMM_ADDR 0x50
#define MAX_DIMM_ADDR 0x60
-#ifndef CONFIG_SYS_SDRAM_SIZE
+#ifndef CFG_SYS_SDRAM_SIZE
#define SDRAM_CS_SIZE 0xFFFFFFF
#else
-#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1)
+#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1)
#endif
#define SDRAM_CS_BASE 0x0
#define SDRAM_DIMM_SIZE 0x80000000
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 22f4995..a3b662f 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -60,7 +60,7 @@
instead of a physical address (e.g. on MIPS). The PCI core will then remap
the virtual memory base address to a physical address when adding the PCI
region of type PCI_REGION_SYS_MEMORY.
- This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
+ This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
being used as virtual address.
config PCI_SRIOV
diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c
index dc11402..b81eb35 100644
--- a/drivers/pci/pci-rcar-gen2.c
+++ b/drivers/pci/pci-rcar-gen2.c
@@ -191,7 +191,7 @@
/* AHB-PCI Bridge Communication Registers */
writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
- writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
+ writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
@@ -204,7 +204,7 @@
/* PCI Configuration Registers for AHBPCI */
devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
- writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
+ writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index d514c04..c1be56c 100644
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c
@@ -158,9 +158,9 @@
/* Set up target memory mappings (for external DMA access) */
/* Map both P0 and P2 range to Area 3 RAM for ease of use */
- p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
- p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
- p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
+ p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
+ p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
+ p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
p4_out(0, SH7751_PCILSR1);
p4_out(0, SH7751_PCILAR1);
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 99891dc..a0b82c7 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -459,9 +459,9 @@
}
/* Set the BAR base and size towards DDR */
- bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
+ bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
- writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
+ writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
reg = ((size >> 20) - 1) << 12;
writel(size, regs_base + RESIZABLE_BAR_CTL0);
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index a527741..b7f692f 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -14,11 +14,11 @@
#include <asm/arch-ls102xa/svr.h>
#ifndef CFG_SYS_PCI_MEMORY_BUS
-#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE
#endif
#ifndef CFG_SYS_PCI_MEMORY_PHYS
-#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE
#endif
#ifndef CFG_SYS_PCI_MEMORY_SIZE
diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c
index 141b19b..dc466a8 100644
--- a/drivers/ram/aspeed/sdram_ast2500.c
+++ b/drivers/ram/aspeed/sdram_ast2500.c
@@ -203,7 +203,7 @@
u32 test_pattern = 0xdeadbeef;
u32 cap_param = SDRAM_CONF_CAP_1024M;
u32 refresh_timing_param = DDR4_TRFC;
- const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+ const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
ram_size >>= 1) {
@@ -231,7 +231,7 @@
((refresh_timing_param & SDRAM_AC_TRFC_MASK)
<< SDRAM_AC_TRFC_SHIFT));
- info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config,
(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 5d42608..a2d7ca8 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -838,7 +838,7 @@
u32 test_pattern = 0xdeadbeef;
u32 cap_param = SDRAM_CONF_CAP_2048M;
u32 refresh_timing_param = DDR4_TRFC;
- const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
+ const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
ram_size >>= 1) {
@@ -866,7 +866,7 @@
((refresh_timing_param & SDRAM_AC_TRFC_MASK)
<< SDRAM_AC_TRFC_SHIFT));
- info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK,
@@ -1015,7 +1015,7 @@
break;
}
- info->info.base = CONFIG_SYS_SDRAM_BASE;
+ info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
if (0 == (conf & SDRAM_CONF_ECC_SETUP))
diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c
index d12a3b4..1737fda 100644
--- a/drivers/ram/mediatek/ddr3-mt7629.c
+++ b/drivers/ram/mediatek/ddr3-mt7629.c
@@ -243,17 +243,17 @@
* and it has maximum addressing region
*/
- writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE);
+ writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE);
- if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN)
+ if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN)
return -EINVAL;
for (step = 0; step < 5; step++) {
- writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE +
+ writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE +
(WALKING_STEP << step));
- start = readl(CONFIG_SYS_SDRAM_BASE);
- test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step));
+ start = readl(CFG_SYS_SDRAM_BASE);
+ test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step));
if ((test != ~WALKING_PATTERN) || test == start)
break;
}
@@ -727,7 +727,7 @@
struct mtk_ddr3_priv *priv = dev_get_priv(dev);
u32 val = readl(priv->emi + EMI_CONA);
- info->base = CONFIG_SYS_SDRAM_BASE;
+ info->base = CFG_SYS_SDRAM_BASE;
switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) {
case 0:
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index 42daf06..bb21078 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -2687,7 +2687,7 @@
if (!mem_mbytes)
return -ENODEV;
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = MB(mem_mbytes);
/*
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 69c454a..6929a7e 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -617,12 +617,12 @@
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + params->chan.bw - 1));
writel(test_pattern, addr);
if ((readl(addr) == test_pattern) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
@@ -637,11 +637,11 @@
/* Detect row*/
for (row = 16; row >= 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(test_pattern, addr);
if ((readl(addr) == test_pattern) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c
index b3e7421..ec46ba5 100644
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -220,12 +220,12 @@
u32 bw = cap_info->bw;
for (col = coltmp; col >= 9; col -= 1) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (col + bw - 1ul)));
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -245,12 +245,12 @@
u32 bk;
u32 bw = cap_info->bw;
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (coltmp + bktmp + bw - 1ul)));
- writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0, CFG_SYS_SDRAM_BASE);
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
bk = 3;
else
bk = 2;
@@ -268,12 +268,12 @@
u32 dbw;
u32 bw = cap_info->bw;
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (coltmp + bw + 1ul)));
- writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0, CFG_SYS_SDRAM_BASE);
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
dbw = 0;
else
dbw = 1;
@@ -337,12 +337,12 @@
void __iomem *test_addr;
for (row = rowtmp; row > 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (row + bktmp + coltmp + bw - 1ul)));
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
@@ -363,8 +363,8 @@
u32 row = cap_info->cs0_row;
void __iomem *test_addr, *test_addr1;
- test_addr = CONFIG_SYS_SDRAM_BASE;
- test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = CFG_SYS_SDRAM_BASE;
+ test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
writel(0, test_addr);
@@ -421,15 +421,15 @@
/* detect cs1 row */
for (row = cap_info->cs0_row; row > 12; row--) {
- test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
+ test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
cs0_cap +
(1ul << (row + bktmp + coltmp + bw - 1ul)));
- writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
+ writel(0, CFG_SYS_SDRAM_BASE + cs0_cap);
writel(PATTERN, test_addr);
if (((readl(test_addr) & byte_mask) ==
(PATTERN & byte_mask)) &&
- ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
+ ((readl(CFG_SYS_SDRAM_BASE + cs0_cap) &
byte_mask) == 0)) {
break;
}
diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c
index c024a0c..98b2593 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -726,7 +726,7 @@
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: grf=%p\n", __func__, priv->pmugrf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c
index 832154e..a2425f2 100644
--- a/drivers/ram/rockchip/sdram_rk3066.c
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -616,12 +616,12 @@
/* Detect col. */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -638,11 +638,11 @@
rk3066_dmc_move_to_access_state(chan);
/* Detect row, max 15, min13 for rk3066 */
for (row = 16; row >= 13; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
@@ -854,7 +854,7 @@
if (ret)
return ret;
} else {
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
}
diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c
index 16cfbf9..ded6539 100644
--- a/drivers/ram/rockchip/sdram_rk3128.c
+++ b/drivers/ram/rockchip/sdram_rk3128.c
@@ -23,7 +23,7 @@
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[1]);
diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c
index be8ba44..272b1b2 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c
@@ -638,12 +638,12 @@
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -660,11 +660,11 @@
move_to_access_state(chan);
/* Detect row, max 15,min13 in rk3188*/
for (row = 16; row >= 13; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
@@ -919,7 +919,7 @@
if (ret)
return ret;
#else
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index cd4234f..1b204fb 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -636,12 +636,12 @@
writel(3, &axi_bus->ddrconf);
move_to_access_state(dram->chan[0].pctl);
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -656,11 +656,11 @@
/* Detect row*/
for (row = 16; row >= 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 11) {
@@ -672,11 +672,11 @@
sdram_params->ch[0].cs0_row = row;
}
/* cs detect */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30));
- writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4);
- if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ writel(0, CFG_SYS_SDRAM_BASE);
+ writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30));
+ writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4);
+ if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
sdram_params->ch[0].rank = 2;
else
sdram_params->ch[0].rank = 1;
@@ -813,7 +813,7 @@
if (ret)
return ret;
#else
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
#endif
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index 227a3cc..83778ad 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -684,12 +684,12 @@
/* Detect col */
for (col = 11; col >= 9; col--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE +
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -705,11 +705,11 @@
move_to_access_state(chan);
/* Detect row*/
for (row = 16; row >= 12; row--) {
- writel(0, CONFIG_SYS_SDRAM_BASE);
- addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(0, CFG_SYS_SDRAM_BASE);
+ addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
- (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ (readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 11) {
@@ -1087,7 +1087,7 @@
if (ret)
return ret;
#else
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c
index 44d7d8a..10828e8 100644
--- a/drivers/ram/rockchip/sdram_rk3308.c
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -21,7 +21,7 @@
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
return 0;
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c
index 9c6798f..b511c6b 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c
@@ -580,7 +580,7 @@
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
#endif
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index cbf502b..136e4ed 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -3151,7 +3151,7 @@
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
#endif
diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c
index 0ac4b54..f661615 100644
--- a/drivers/ram/rockchip/sdram_rk3568.c
+++ b/drivers/ram/rockchip/sdram_rk3568.c
@@ -21,7 +21,7 @@
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c
index 130b73d..60525f2 100644
--- a/drivers/usb/host/ehci-rmobile.c
+++ b/drivers/usb/host/ehci-rmobile.c
@@ -90,7 +90,7 @@
/* AHB-PCI Bridge Communication Registers */
writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
- writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
+ writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win1_ctr);
writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win2_ctr);
@@ -103,7 +103,7 @@
writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
&ahbcom_pci->ahbpci_win1_ctr);
writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
- writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
+ writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
writel(0xf0000000, &ahbconf_pci->win2_basead);
writel(SERREN | PERREN | MASTEREN | MEMEN,
&ahbconf_pci->cmnd_sts);
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index 2ee6212..9110a48 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -385,7 +385,7 @@
(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
- writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
+ writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
writel(mode->xres * 4, &de_fe->ch0_stride);
writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
@@ -1222,7 +1222,7 @@
EFI_RESERVED_MEMORY_TYPE);
#endif
- fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE;
+ fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE;
if (overscan_offset) {
fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000);
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 719caf7..3a4fbc6 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -30,8 +30,8 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
-#define CONFIG_SYS_SDRAM_BASE 0xc8000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0xc8000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index ad7bd13..ab88918 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -26,8 +26,8 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
-#define CONFIG_SYS_SDRAM_BASE 0xD0000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0xD0000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 25c3f22..6dfa3dd 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -60,22 +60,22 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
-#define CONFIG_SYS_SDRAM_EMOD 0x80010000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x43711630
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1002000
+#define CFG_SYS_SDRAM_EMOD 0x80010000
+#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
@@ -100,8 +100,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index f200d70..e28662c 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -70,10 +70,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
@@ -81,7 +81,7 @@
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -109,8 +109,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 9ff66d7..f1da278 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -52,10 +52,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
@@ -67,7 +67,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -90,8 +90,8 @@
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index f7bfe59..bd3c57d 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -77,17 +77,17 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
@@ -117,8 +117,8 @@
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index dcd8365..7c3bc03 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -71,10 +71,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
/*
@@ -82,7 +82,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
@@ -100,8 +100,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 9012794..4eb4abe 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -73,10 +73,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/*
@@ -84,7 +84,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -101,8 +101,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 925d26e..eda3944 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -72,10 +72,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
@@ -85,7 +85,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -105,8 +105,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 79a4e61..159993a 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -74,22 +74,22 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x80010000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x43711630
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1092000
+#define CFG_SYS_SDRAM_EMOD 0x80010000
+#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -118,8 +118,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index fc21af5..d7ece63 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -68,22 +68,22 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x53722730
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x018D0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x53722730
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1092000
+#define CFG_SYS_SDRAM_EMOD 0x40010000
+#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -117,8 +117,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index f7c09a2..b2fc692 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -70,22 +70,22 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x53722730
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x018D0000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_CFG1 0x53722730
+#define CFG_SYS_SDRAM_CFG2 0x56670000
+#define CFG_SYS_SDRAM_CTRL 0xE1092000
+#define CFG_SYS_SDRAM_EMOD 0x40010000
+#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -117,8 +117,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index a5518d3..2e7140c 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h
@@ -62,8 +62,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
-/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
+#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 0e70b28..d9627e3 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -59,7 +59,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
@@ -69,7 +69,7 @@
/*
* Manually set up DDR parameters
*/
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
+#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index c59a376..6a51149 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -40,7 +40,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f87e759..21491b9 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -110,9 +110,9 @@
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
-#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
+#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 8c7b877..d7e06d2 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -69,10 +69,10 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* Local Bus Definitions
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index 824190a..417b9ae 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -7,7 +7,7 @@
#define _CONFIG_SBX81LIFKW_H
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index e67da1f..87b6822 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -7,7 +7,7 @@
#define _CONFIG_SBX81LIFXCAT_H
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 154b2f1..616387f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -116,12 +116,12 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
-#define CONFIG_SYS_SDRAM_SIZE 2048
+#define CFG_SYS_SDRAM_SIZE 2048
#endif
/*
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 847cf65..37dfe32 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -88,11 +88,11 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b49c264..8f56de4 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -86,8 +86,8 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index aae41a3..e9db4a2 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -81,8 +81,8 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 9dc45e3..cc86c9d 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -62,7 +62,7 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
@@ -154,7 +154,7 @@
#define SPD_EEPROM_ADDRESS2 0x54
#define SPD_EEPROM_ADDRESS3 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index 78201ad..57f3f37 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -13,7 +13,7 @@
#include <environment/ti/mmc.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 1409407..25c71f0 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -16,7 +16,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 0345160..0307426 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -15,7 +15,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 2bda66f..eba78d3 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -33,8 +33,8 @@
/* size of internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 650140b..63c7dfc 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 3114cf0..865aad2 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
diff --git a/include/configs/ap152.h b/include/configs/ap152.h
index f067445..0464a69 100644
--- a/include/configs/ap152.h
+++ b/include/configs/ap152.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index e2e491b..cf23837 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -63,7 +63,7 @@
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 30d32d2..356d4c3 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -106,7 +106,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index f7deba4..ed32e77 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -6,9 +6,9 @@
#ifndef __CONFIG_ARBEL_H
#define __CONFIG_ARBEL_H
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 35e8840..90cf470 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -406,7 +406,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
index 5c90058..cbd0d6c 100644
--- a/include/configs/aspeed-common.h
+++ b/include/configs/aspeed-common.h
@@ -14,7 +14,7 @@
/* Misc CPU related */
-#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
+#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 58635df..b142ea3 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -57,7 +57,7 @@
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
-#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
@@ -158,7 +158,7 @@
* (Set up by the startup code)
* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/*
* Chipselect bank definitions
@@ -195,8 +195,8 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+ (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
@@ -213,8 +213,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 574bfe3..0d76f41 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -31,8 +31,8 @@
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#ifdef CONFIG_AT91SAM9XE
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 2c785ad..dcc1cca 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -17,8 +17,8 @@
#include <asm/hardware.h>
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index bba8574..aefa9fc 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -23,8 +23,8 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
@@ -100,22 +100,22 @@
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 3ce264a..08cfee1 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -15,8 +15,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x70000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0x70000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 5e3ded2..76f87c1 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -14,8 +14,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* DataFlash */
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index b79c8ba..e1111b6 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -17,8 +17,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 40ea4ed..eb1d1ad 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -20,8 +20,8 @@
*/
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* DataFlash */
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index e3b6956..83ac87b 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -28,7 +28,7 @@
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
/*
* Serial console configuration
diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h
index 1932713..6d82712 100644
--- a/include/configs/axs10x.h
+++ b/include/configs/axs10x.h
@@ -20,8 +20,8 @@
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_512M
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_512M
/*
* UART configuration
diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h
index d0c46a2..b02ed1b 100644
--- a/include/configs/bcm947622.h
+++ b/include/configs/bcm947622.h
@@ -6,7 +6,7 @@
#ifndef __BCM947622_H
#define __BCM947622_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define COUNTER_FREQUENCY 50000000
#endif
diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h
index 1346ace..246feb6 100644
--- a/include/configs/bcm94908.h
+++ b/include/configs/bcm94908.h
@@ -6,6 +6,6 @@
#ifndef __BCM94908_H
#define __BCM94908_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h
index f3d17dd..c428b1a 100644
--- a/include/configs/bcm94912.h
+++ b/include/configs/bcm94912.h
@@ -6,6 +6,6 @@
#ifndef __BCM94912_H
#define __BCM94912_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h
index 361569a..f1b68ba 100644
--- a/include/configs/bcm963138.h
+++ b/include/configs/bcm963138.h
@@ -6,7 +6,7 @@
#ifndef __BCM963138_H
#define __BCM963138_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_HZ_CLOCK 500000000
#endif
diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h
index edbdfc3..90dfa98 100644
--- a/include/configs/bcm963146.h
+++ b/include/configs/bcm963146.h
@@ -6,6 +6,6 @@
#ifndef __BCM963146_H
#define __BCM963146_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h
index 5a24ccc..54f6750 100644
--- a/include/configs/bcm963148.h
+++ b/include/configs/bcm963148.h
@@ -6,6 +6,6 @@
#ifndef __BCM963148_H
#define __BCM963148_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h
index b15c411..2fdd22d 100644
--- a/include/configs/bcm963158.h
+++ b/include/configs/bcm963158.h
@@ -6,6 +6,6 @@
#ifndef __BCM963158_H
#define __BCM963158_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h
index b25f6a1..32fc4a5 100644
--- a/include/configs/bcm963178.h
+++ b/include/configs/bcm963178.h
@@ -6,6 +6,6 @@
#ifndef __BCM963178_H
#define __BCM963178_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h
index c8f3267..c69d177 100644
--- a/include/configs/bcm96756.h
+++ b/include/configs/bcm96756.h
@@ -6,6 +6,6 @@
#ifndef __BCM96756_H
#define __BCM96756_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h
index 5d9e87b..37d2d91 100644
--- a/include/configs/bcm96813.h
+++ b/include/configs/bcm96813.h
@@ -6,6 +6,6 @@
#ifndef __BCM96813_H
#define __BCM96813_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h
index 1d6d5d6..581fd55 100644
--- a/include/configs/bcm96846.h
+++ b/include/configs/bcm96846.h
@@ -6,6 +6,6 @@
#ifndef __BCM96846_H
#define __BCM96846_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h
index 6e420f2..3fb1ab9 100644
--- a/include/configs/bcm96855.h
+++ b/include/configs/bcm96855.h
@@ -6,6 +6,6 @@
#ifndef __BCM96855_H
#define __BCM96855_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h
index a7ae71e..5f5af32 100644
--- a/include/configs/bcm96856.h
+++ b/include/configs/bcm96856.h
@@ -6,6 +6,6 @@
#ifndef __BCM96856_H
#define __BCM96856_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h
index 4e584b4..9a0d89a 100644
--- a/include/configs/bcm96858.h
+++ b/include/configs/bcm96858.h
@@ -6,6 +6,6 @@
#ifndef __BCM96858_H
#define __BCM96858_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h
index 3e23e94..7702d1f 100644
--- a/include/configs/bcm96878.h
+++ b/include/configs/bcm96878.h
@@ -6,6 +6,6 @@
#ifndef __BCM96878_H
#define __BCM96878_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#endif
diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h
index 76189a4..b546988 100644
--- a/include/configs/bcm_ns3.h
+++ b/include/configs/bcm_ns3.h
@@ -15,7 +15,7 @@
#define V2M_BASE 0x80000000
#define PHYS_SDRAM_1 V2M_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* Initial SP before reloaction is placed at end of first DRAM bank,
diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h
index 9f51b9c..9769a71 100644
--- a/include/configs/bcmstb.h
+++ b/include/configs/bcmstb.h
@@ -81,7 +81,7 @@
* MiB. However, BOLT can be configured to allow loading larger
* initramfs images, in which case this limitation is eliminated.
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
/*
diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h
index 829e816..556bfa0 100644
--- a/include/configs/bitmain_antminer_s9.h
+++ b/include/configs/bitmain_antminer_s9.h
@@ -6,8 +6,8 @@
#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
#define __CONFIG_BITMAIN_ANTMINER_S9_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"pxefile_addr_r=0x2000000\0" \
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index ca2bc19..a075a5b 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -199,7 +199,7 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (SZ_512M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h
index c328f41..e40f110 100644
--- a/include/configs/bmips_bcm3380.h
+++ b/include/configs/bmips_bcm3380.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
index d16d50e..508317f 100644
--- a/include/configs/bmips_bcm6318.h
+++ b/include/configs/bmips_bcm6318.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
index f69c46b..c5bda16 100644
--- a/include/configs/bmips_bcm63268.h
+++ b/include/configs/bmips_bcm63268.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index acd021e..32397c2 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h
index fa9e5f0..18c9972 100644
--- a/include/configs/bmips_bcm6338.h
+++ b/include/configs/bmips_bcm6338.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
index bcf5c87..f8d7148 100644
--- a/include/configs/bmips_bcm6348.h
+++ b/include/configs/bmips_bcm6348.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
index e31b8bc..d564a32 100644
--- a/include/configs/bmips_bcm6358.h
+++ b/include/configs/bmips_bcm6358.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
index 6e707d3..f982a43 100644
--- a/include/configs/bmips_bcm6362.h
+++ b/include/configs/bmips_bcm6362.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
index bb72c8c..11d623c 100644
--- a/include/configs/bmips_bcm6368.h
+++ b/include/configs/bmips_bcm6368.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h
index a1c992b..30965c8 100644
--- a/include/configs/bmips_bcm6838.h
+++ b/include/configs/bmips_bcm6838.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
diff --git a/include/configs/boston.h b/include/configs/boston.h
index a09e831..0033a7f 100644
--- a/include/configs/boston.h
+++ b/include/configs/boston.h
@@ -22,9 +22,9 @@
* Memory map
*/
#ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+# define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#else
-# define CONFIG_SYS_SDRAM_BASE 0x80000000
+# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
index bdedf7e..78b2000 100644
--- a/include/configs/brppt2.h
+++ b/include/configs/brppt2.h
@@ -76,7 +76,7 @@
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 1bf6baf..f1734aa 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -45,7 +45,7 @@
* always, even when we have more. We always start at 0x80000000,
* and we place the initial stack pointer in our SRAM.
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/*
* Our platforms make use of SPL to initalize the hardware (primarily
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index c4110f8..474ad69 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -92,7 +92,7 @@
/* On CCP board, USDHC1 is for eMMC */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
/* DDR3 board total DDR is 1 GB */
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index c395384..6f2b824 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -111,7 +111,7 @@
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index b7511ad..f268dfd 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h
@@ -11,7 +11,7 @@
/* Memory configuration */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
+#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index fc45e59..eb899c4 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -82,7 +82,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 2544362..47c4aac 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -21,7 +21,7 @@
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 52000b5..65b9074 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -30,7 +30,7 @@
*/
#define CONFIG_SYS_CLK 66000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
@@ -152,9 +152,9 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
*-------------------------------------------------------------------------
@@ -162,7 +162,7 @@
*-----------------------------------------------------------------------
*/
-/* #define CONFIG_SYS_SDRAM_SIZE 16 */
+/* #define CFG_SYS_SDRAM_SIZE 16 */
/*
*-----------------------------------------------------------------------
@@ -186,8 +186,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index afe8bad..ca8445a 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -116,7 +116,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index d641fbf..6002d8d 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -96,7 +96,7 @@
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CFG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 68d923c..14278e9 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -100,7 +100,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index f9bf849..c080955 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -160,7 +160,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 0f6f99d..1128307 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -85,7 +85,7 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
index 8e0230c..8aec52d 100644
--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
@@ -22,7 +22,7 @@
#define PHYS_SDRAM_1 (V2M_BASE)
#define PHYS_SDRAM_1_SIZE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0)
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 9d44e67..c7a3e47 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -32,8 +32,8 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 4f0188d..e2e1cfe 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -166,7 +166,7 @@
/* Load U-Boot Image From MMC */
/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index b944d50..b16f3d4 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -42,7 +42,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 5244b9c..c473f3d 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -15,8 +15,8 @@
/*
* Memory configurations
*/
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_64M
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_64M
/*
* DMA
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index e694dd7..ddc436d 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -72,7 +72,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 0e5ecab..0a7428b 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -283,7 +283,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
index c37b4c6..daf7ecd 100644
--- a/include/configs/dragonboard410c.h
+++ b/include/configs/dragonboard410c.h
@@ -17,7 +17,7 @@
#define PHYS_SDRAM_1 0x80000000
/* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */
#define PHYS_SDRAM_1_SIZE SZ_1G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h
index 1fa5d05..31cd853 100644
--- a/include/configs/dragonboard820c.h
+++ b/include/configs/dragonboard820c.h
@@ -19,7 +19,7 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0x5ea4ffff
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#include <config_distro_bootcmd.h>
diff --git a/include/configs/durian.h b/include/configs/durian.h
index 8f0e8be..001596c 100644
--- a/include/configs/durian.h
+++ b/include/configs/durian.h
@@ -11,7 +11,7 @@
/* Sdram Bank #1 Address */
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x7B000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* BOOT */
diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h
index 1d65529..fc1c2ae 100644
--- a/include/configs/ea-lpc3250devkitv2.h
+++ b/include/configs/ea-lpc3250devkitv2.h
@@ -13,7 +13,7 @@
/*
* RAM
*/
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
/*
* cmd
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 80a820c..80de73d 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -66,13 +66,13 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE0 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE0 0x00000000
+#define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
+#define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0
+#define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0
/*
* For booting Linux, the board info and command line data
@@ -103,8 +103,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index 16d2648..d24bc56 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -50,7 +50,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index a4891dd..e39bb94 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -27,7 +27,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h
index 60fab04..c2b921e 100644
--- a/include/configs/emsdp.h
+++ b/include/configs/emsdp.h
@@ -8,8 +8,8 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_16M
+#define CFG_SYS_SDRAM_BASE 0x10000000
+#define CFG_SYS_SDRAM_SIZE SZ_16M
/*
* Environment
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
index 2f067a4..b4f14a9 100644
--- a/include/configs/espresso7420.h
+++ b/include/configs/espresso7420.h
@@ -10,7 +10,7 @@
#include <configs/exynos7420-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index f19e12d..97a8ffb 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -26,8 +26,8 @@
#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
/* 128MB SDRAM in 1 bank */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE (128 << 20)
/* 512kB on-chip NOR flash */
# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 44f5cb1..dd322c2 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -29,21 +29,21 @@
#define CONFIG_RD_LVL
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
/* SPI */
diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h
index 8e2f135..cc0cf5e 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -9,7 +9,7 @@
#ifndef __CONFIG_5250_H
#define __CONFIG_5250_H
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
index a8bef86..cff910c 100644
--- a/include/configs/exynos7420-common.h
+++ b/include/configs/exynos7420-common.h
@@ -23,21 +23,21 @@
/* select serial console configuration */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
/* Configuration of ENV Blocks */
diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h
index b05846d..68c36dc 100644
--- a/include/configs/exynos78x0-common.h
+++ b/include/configs/exynos78x0-common.h
@@ -21,32 +21,32 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
#ifndef MEM_LAYOUT_ENV_SETTINGS
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index ba09831..f5353ec 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -18,8 +18,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */
#define CFG_SYS_NAND_BASE 0x40000000
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
index a1400eb..a755714 100644
--- a/include/configs/gardena-smart-gateway-mt7688.h
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -7,7 +7,7 @@
#define __CONFIG_GARDENA_SMART_GATEWAY_H
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
index fa6f0e6..6cdfe8c 100644
--- a/include/configs/gazerbeam.h
+++ b/include/configs/gazerbeam.h
@@ -12,9 +12,9 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */
+#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE
/*
* Memory test
diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h
index c862f15..85ceaf8 100644
--- a/include/configs/ge_b1x5v2.h
+++ b/include/configs/ge_b1x5v2.h
@@ -37,7 +37,7 @@
/* Memory */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index d519384..1dba2e9 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -94,7 +94,7 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index d2138c2..dd6b22d 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -13,8 +13,8 @@
/* Miscellaneous */
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 645ca16..fe00272 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -53,7 +53,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/gxp.h b/include/configs/gxp.h
index e3c97b2..2b0b048 100644
--- a/include/configs/gxp.h
+++ b/include/configs/gxp.h
@@ -10,6 +10,6 @@
#ifndef _GXP_H_
#define _GXP_H_
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index a7d21a7..0d281a3 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -14,7 +14,7 @@
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x20000000\0" \
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 18c1e83..775f166 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -24,7 +24,7 @@
/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
index 973df8e..914c3ad 100644
--- a/include/configs/hikey960.h
+++ b/include/configs/hikey960.h
@@ -16,7 +16,7 @@
#define PHYS_SDRAM_1 0x00000000
#define PHYS_SDRAM_1_SIZE 0xC0000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
index 1d7b171..fcb2dec 100644
--- a/include/configs/hsdk-4xd.h
+++ b/include/configs/hsdk-4xd.h
@@ -22,8 +22,8 @@
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
* UART configuration
diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
index 9e092e1..0ae9352 100644
--- a/include/configs/hsdk.h
+++ b/include/configs/hsdk.h
@@ -21,8 +21,8 @@
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_1G
/*
* UART configuration
diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h
index 1fc45f9..f1ca28b 100644
--- a/include/configs/imgtec_xilfpga.h
+++ b/include/configs/imgtec_xilfpga.h
@@ -21,8 +21,8 @@
*/
/* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
/*----------------------------------------------------------------------
* Commands
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 974dff8..594aa4f 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -130,5 +130,5 @@
"upd=run load update\0" \
/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#endif /* __IMX27LITE_COMMON_CONFIG_H */
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index b8eb5c8..d4e2583 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -109,7 +109,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 6b822e7..1b08c5e 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -105,7 +105,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h
index f7f8f33..a074df5 100644
--- a/include/configs/imx6dl-mamoj.h
+++ b/include/configs/imx6dl-mamoj.h
@@ -55,7 +55,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 15171d7..855af29 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h
@@ -85,7 +85,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h
index 70b4b84..0a688af 100644
--- a/include/configs/imx6ulz_smm_m2.h
+++ b/include/configs/imx6ulz_smm_m2.h
@@ -63,7 +63,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index c6db5e9..e5118f1 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -69,7 +69,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index 917d567..e62f9c5 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -127,7 +127,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 8e08899..143da00 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -74,7 +74,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index dd9f93f..c766930 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -21,7 +21,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index f1d1c1c..9937071 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -57,7 +57,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index 9cdba70..cd47d84 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -41,7 +41,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 0653563..58e165c 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -32,7 +32,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 0ae3da1..f532c10 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -78,7 +78,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h
index d6959ac..415248e 100644
--- a/include/configs/imx8mn_bsh_smm_s2_common.h
+++ b/include/configs/imx8mn_bsh_smm_s2_common.h
@@ -26,7 +26,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 9c75e3e..8857bc7 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -49,7 +49,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index a484d91..628bb58 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -46,7 +46,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index d5252ab..a169be3 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -26,7 +26,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index bf87825..62bcef5 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -14,7 +14,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 1b533e2..d394762 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -55,7 +55,7 @@
/* Totally 2GB DDR */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h
index 7986d20..3e995c9 100644
--- a/include/configs/imx8mp_icore_mx8mp.h
+++ b/include/configs/imx8mp_icore_mx8mp.h
@@ -56,7 +56,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 8f2b474..1943a24 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -136,7 +136,7 @@
/* Totally 6GB or 4G DDR */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index b1c213c..7d36058 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -26,7 +26,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index 4b2107e..271376c 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -50,7 +50,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 2d4c8d7..672a9fa 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -56,7 +56,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index 1905e53..dd354b0 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -88,7 +88,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 7f6d59d..f1f907f 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -103,7 +103,7 @@
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
index 67f19bc..fe27ac3 100644
--- a/include/configs/imx8qm_rom7720.h
+++ b/include/configs/imx8qm_rom7720.h
@@ -108,7 +108,7 @@
*/
#define CFG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 567351f..19f1dba 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -103,7 +103,7 @@
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index 7bf0ce7..592df27 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -54,7 +54,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index b281466..077a4d8 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -127,7 +127,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
index 512e0e6..8d0458d 100644
--- a/include/configs/integrator-common.h
+++ b/include/configs/integrator-common.h
@@ -30,7 +30,7 @@
*/
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* FLASH and environment organization
diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h
index a2e50c3..5a769e0 100644
--- a/include/configs/iot_devkit.h
+++ b/include/configs/iot_devkit.h
@@ -32,12 +32,12 @@
* : :
* : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR
* :
- * Specified explicitly by CONFIG_SYS_SDRAM_BASE
+ * Specified explicitly by CFG_SYS_SDRAM_BASE
*
* NOTES:
* - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down,
- * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing
- * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on
+ * i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing
+ * that CFG_SYS_SDRAM_BASE in which case data won't be really saved on
* stack any longer and values popped from stack will contain garbage
* leading to unexpected behavior, typically but not limited to:
* - "Returning" back to bogus caller function
@@ -50,16 +50,16 @@
#define DCCM_BASE 0x80000000
#define DCCM_SIZE SZ_128K
-#define CONFIG_SYS_SDRAM_BASE DCCM_BASE
-#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE
+#define CFG_SYS_SDRAM_BASE DCCM_BASE
+#define CFG_SYS_SDRAM_SIZE DCCM_SIZE
#define ROM_BASE CONFIG_SYS_MONITOR_BASE
#define ROM_SIZE SZ_256K
#define RAM_DATA_BASE SYS_INIT_SP_ADDR
-#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \
+#define RAM_DATA_SIZE CFG_SYS_SDRAM_SIZE - \
(SYS_INIT_SP_ADDR - \
- CONFIG_SYS_SDRAM_BASE) - \
+ CFG_SYS_SDRAM_BASE) - \
CONFIG_SYS_MALLOC_LEN - \
CONFIG_ENV_SIZE
#endif /* _CONFIG_IOT_DEVKIT_H_ */
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 9f54f25..2a0b0c7 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -16,7 +16,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
/* FLASH Configuration */
#define CONFIG_SYS_FLASH_BASE 0x000000000
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 932d7d3..e690ef9 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -17,7 +17,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
-#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 7d36a25..db1daee 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -7,7 +7,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -17,7 +17,7 @@
/*
* Manually set up DDR parameters
*/
-#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
+#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
/*
* The reserved memory
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index ad9853a..b5913ed 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -20,7 +20,7 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index c8423fd..dbf038c 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -163,10 +163,10 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/******************************************************************************
* (PRAM usage)
diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
index b3e1fc2..e2808ec 100644
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -14,7 +14,7 @@
/* RAM */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
index a2aedef..73b5951 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -17,7 +17,7 @@
/* RAM */
#define PHYS_SDRAM DDR_CSD1_BASE_ADDR
#define PHYS_SDRAM_SIZE (SZ_4G)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index 6acd2f7..9b45281 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -64,7 +64,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 7ed1f15..bbf0761 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -21,7 +21,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/* early stack pointer */
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index c401fd3..967de66 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -67,7 +67,7 @@
#define PHYS_SDRAM_1_SIZE (512 * SZ_1M)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index b0e49ad..de1fc0b 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -86,7 +86,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 1f642fb..bee064c 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -85,7 +85,7 @@
"bootscript=source ${bootscraddr}\0"
/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
diff --git a/include/configs/librem5.h b/include/configs/librem5.h
index dbd7d10..3a2c508 100644
--- a/include/configs/librem5.h
+++ b/include/configs/librem5.h
@@ -82,7 +82,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
index 28372d4..b913450 100644
--- a/include/configs/linkit-smart-7688.h
+++ b/include/configs/linkit-smart-7688.h
@@ -7,7 +7,7 @@
#define __CONFIG_LINKIT_SMART_7688_H
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index 1d51b87..d1ebd99 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -87,7 +87,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 196e024..f0a9e9a 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -9,7 +9,7 @@
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 809f9ae..0712437 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -12,7 +12,7 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 674bcbe..c19ed2f 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -10,7 +10,7 @@
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 9ad3a12..54555b3 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -10,7 +10,7 @@
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
/*
* QIXIS Definitions
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 4f77acd..d74936d 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -10,7 +10,7 @@
#include "ls1012a_common.h"
/* DDR */
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x40000000
/*
* I2C IO expander
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 3579f9c..49a77fd 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -42,7 +42,7 @@
#define SDRAM_CFG_BI 0x00000001
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* Serial Port
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 4566511..1f5a80f 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -20,7 +20,7 @@
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index 1e2db12..4954606 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -57,7 +57,7 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */
#define CFG_SYS_NS16550_CLK get_serial_clock()
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 323feb6..d772249 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -60,7 +60,7 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 587f23b..064c4f0 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -15,7 +15,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
/*
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index df63382..e940dff 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -34,7 +34,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index b09588f..ce254d8 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -34,7 +34,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 2117b08..f8eaee8 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -32,7 +32,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
* SMP Definitinos
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index c79a507..21c097e 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -19,7 +19,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 8b2b747..ad85e2d 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -17,8 +17,8 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
-#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE 0x200000000UL
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 1734f32..cbdb2fa 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -20,7 +20,7 @@
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 2dd34ea..c9aee00 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -22,11 +22,11 @@
*/
#ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+# define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#else
-# define CONFIG_SYS_SDRAM_BASE 0x80000000
+# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
+#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index db84302..5ad945b 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -47,6 +47,6 @@
*/
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+#define CFG_SYS_SDRAM_SIZE SZ_1G
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index f9f0825..8aa3b0c 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -214,7 +214,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h
index c6ce883..2422cbf 100644
--- a/include/configs/meerkat96.h
+++ b/include/configs/meerkat96.h
@@ -17,7 +17,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index cd3910e..2e07886 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -44,8 +44,8 @@
#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 726f33c..6331b76 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -36,7 +36,7 @@
#define STDIN_CFG "serial"
#endif
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
/* ROM USB boot support, auto-execute boot.scr at scriptaddr */
#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \
diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
index 4c7cfac..3def93d 100644
--- a/include/configs/microchip_mpfs_icicle.h
+++ b/include/configs/microchip_mpfs_icicle.h
@@ -9,7 +9,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h
index bd35378..ac5ff92 100644
--- a/include/configs/msc_sm2s_imx8mp.h
+++ b/include/configs/msc_sm2s_imx8mp.h
@@ -49,7 +49,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define PHYS_SDRAM_2 0xc0000000
diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h
index c76e1fc..65cd6f5 100644
--- a/include/configs/mt7620.h
+++ b/include/configs/mt7620.h
@@ -8,7 +8,7 @@
#ifndef __CONFIG_MT7620_H
#define __CONFIG_MT7620_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
index e09e9c8..1211bb4 100644
--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h
@@ -8,7 +8,7 @@
#ifndef __CONFIG_MT7621_H
#define __CONFIG_MT7621_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED 0x1c000000
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
index fd8e30a..e5d60e1 100644
--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h
@@ -15,7 +15,7 @@
/* SPL -> Uboot */
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* Ethernet */
#define CONFIG_IPADDR 192.168.1.1
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index 73093f9..39a7ba7 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
@@ -21,7 +21,7 @@
#define MMC_SUPPORTS_TUNING
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* This is needed for kernel booting */
#define FDT_HIGH "0xac000000"
diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h
index bb12ebf..9c5034f 100644
--- a/include/configs/mt7628.h
+++ b/include/configs/mt7628.h
@@ -8,7 +8,7 @@
#ifndef __CONFIG_MT7628_H
#define __CONFIG_MT7628_H
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index 668dc3c..d330adb 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
@@ -25,7 +25,7 @@
/* UBoot -> Kernel */
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* Ethernet */
#define CONFIG_IPADDR 192.168.1.1
diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h
index 9f26b0b..249f0b9 100644
--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h
@@ -16,6 +16,6 @@
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h
index 4fbd57a..990e411 100644
--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h
@@ -16,6 +16,6 @@
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
/* DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#endif
diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h
index 7cabbef..8a8bc85 100644
--- a/include/configs/mt8518.h
+++ b/include/configs/mt8518.h
@@ -10,8 +10,8 @@
#define __MT8518_H
/* DRAM definition */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* Uboot definition */
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index e870fc8..e45bfd7 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -27,7 +27,7 @@
*/
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
index 41bdfae..9c4038b 100644
--- a/include/configs/mvebu_alleycat-5.h
+++ b/include/configs/mvebu_alleycat-5.h
@@ -9,7 +9,7 @@
#include <asm/arch/soc.h>
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x200000000
+#define CFG_SYS_SDRAM_BASE 0x200000000
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400, 460800, 921600 }
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 6d3cb99..7641b56 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -13,7 +13,7 @@
*/
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 5debd91..358e06f 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -12,7 +12,7 @@
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
/* auto boot */
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index dd303a1..aa3d7a1 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -10,7 +10,7 @@
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Status LED */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 4c05312..f597cdb 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -13,7 +13,7 @@
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environments */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 140f5e9..bc8c893 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -13,7 +13,7 @@
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* UBI and NAND partitioning */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 95afb35..2229980 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -112,7 +112,7 @@
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index 7783563..e84bac6 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -60,7 +60,7 @@
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 3c9b2ad..9e837a3 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -95,7 +95,7 @@
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index b26613a..52ff7b0 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -96,7 +96,7 @@
#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 1db4d6c..3c4ba09 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -85,7 +85,7 @@
#include <config_distro_bootcmd.h>
/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
index a6cefab..9c160c4 100644
--- a/include/configs/mx6memcal.h
+++ b/include/configs/mx6memcal.h
@@ -27,7 +27,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index bc9fab1..711b5a3 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -139,7 +139,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index ca1d077..3c2621d 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -82,7 +82,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index 44a5eef..a3a12ae 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -82,7 +82,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_2G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index a41e428..f0e239f 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -78,7 +78,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index c655671..a0f9c53 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -106,7 +106,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 65f0a5c..8199b4b 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -108,7 +108,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 604923e..827385c 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -102,7 +102,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index af17658..c39b357 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -81,7 +81,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
index 62e8e62..362de48 100644
--- a/include/configs/mx7ulp_com.h
+++ b/include/configs/mx7ulp_com.h
@@ -26,7 +26,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM 0x60000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index e938249..9ef1eea 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -26,7 +26,7 @@
#define PHYS_SDRAM 0x60000000
#define PHYS_SDRAM_SIZE SZ_1G
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index 273f938..cdd1286 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -22,7 +22,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index ec5339d..9d09811 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -90,7 +90,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 2623f99..9ad4f59 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -161,7 +161,7 @@
* FLASH and environment organization
*/
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
@@ -170,7 +170,7 @@
*/
#define SDRAM_SIZE 0x10000000 /* 256 MB */
-#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
+#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE)
#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */
#define KERNEL_OFFSET 0x40000 /* 256 kB */
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 9dc05d8..8d39d75 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -30,7 +30,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index ea407c9..080c659 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -23,7 +23,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/nsim.h b/include/configs/nsim.h
index d469ef8..b930a53 100644
--- a/include/configs/nsim.h
+++ b/include/configs/nsim.h
@@ -13,8 +13,8 @@
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_256M
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_256M
/*
* Console configuration
diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h
index 00f7d87..5ac951a 100644
--- a/include/configs/o4-imx6ull-nano.h
+++ b/include/configs/o4-imx6ull-nano.h
@@ -7,7 +7,7 @@
#include "mx6_common.h"
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h
index 0fa7490..b475354 100644
--- a/include/configs/octeon_common.h
+++ b/include/configs/octeon_common.h
@@ -14,6 +14,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
#endif
-#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#endif /* __OCTEON_COMMON_H__ */
diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h
index ab1eb78..03d1a8e 100644
--- a/include/configs/octeontx2_common.h
+++ b/include/configs/octeontx2_common.h
@@ -10,7 +10,7 @@
/** Maximum size of image supported for bootm (and bootable FIT images) */
/** Memory base address */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
/** Stack starting address */
diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h
index 38f99ab..58275cc 100644
--- a/include/configs/octeontx_common.h
+++ b/include/configs/octeontx_common.h
@@ -36,7 +36,7 @@
/** Maximum size of image supported for bootm (and bootable FIT images) */
/** Memory base address */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE
/** Stack starting address */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index babd3ca..ce8ea58 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -17,9 +17,9 @@
#define CONFIG_SYS_PL310_BASE 0x10502000
#endif
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#include <linux/sizes.h>
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 1564629..d2d7fca 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -10,7 +10,7 @@
#include <configs/exynos5420-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define TZPC_BASE_OFFSET 0x10000
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 2b47d4c..5b0d87a 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -154,7 +154,7 @@
/* defines for SPL */
/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>
diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h
index 3ff8187..5b097e9 100644
--- a/include/configs/openpiton-riscv64.h
+++ b/include/configs/openpiton-riscv64.h
@@ -14,7 +14,7 @@
#include <linux/sizes.h>
/* Environment options */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* ---------------------------------------------------------------------
* Board boot configuration
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index b3cdd2f..53889d6 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -14,7 +14,7 @@
#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 36aaa7c..6633d54 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -11,8 +11,8 @@
#include <configs/exynos4-common.h>
/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Power Down Modes */
diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h
index b0233b9..8d0311c 100644
--- a/include/configs/owl-common.h
+++ b/include/configs/owl-common.h
@@ -11,7 +11,7 @@
#define _OWL_COMMON_CONFIG_H_
/* SDRAM Definitions */
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_BASE 0x0
/* Some commands use this as the default load address */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 6e8ac1b..14d702e 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -125,13 +125,13 @@
#define SPD_EEPROM_ADDRESS 0x52
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
+#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
#else
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
+#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
#endif
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Default settings for DDR3 */
#ifndef CONFIG_TARGET_P2020RDB
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 6267dc7..85cedde 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -34,7 +34,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index e13b5df..f7e36f2 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -36,7 +36,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index a04a03a..586cddf 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -118,7 +118,7 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index 14cbfde..cf705dc 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -15,7 +15,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
index 7a8d3c6..bfc0011 100644
--- a/include/configs/peach-pi.h
+++ b/include/configs/peach-pi.h
@@ -20,7 +20,7 @@
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_POWER_TPS65090_EC
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 2c749ac..09c6b4f 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -20,7 +20,7 @@
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index c98393b..ac68c93 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -64,7 +64,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 49cd9d4..aedaf80 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -63,7 +63,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 4ea16d6..d9abbbc 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -23,7 +23,7 @@
(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
/* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE 0x88000000
+#define CFG_SYS_SDRAM_BASE 0x88000000
/* Memory Test */
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index f95beeb..fc2cab9 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -91,7 +91,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 85772ba..22b4976 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -91,7 +91,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index b3a38d8..f5b9eed 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -93,7 +93,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index 17af19d..91baff9 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -67,7 +67,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index adb2f43..3fbddd9 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -78,22 +78,22 @@
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
@@ -160,6 +160,6 @@
"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
""
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#endif
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 4352a24..c1f6334 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -90,22 +90,22 @@
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
@@ -184,6 +184,6 @@
"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
""
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#endif
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index a7deaa3..4a0a168 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -20,8 +20,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x70000000
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_BASE 0x70000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index 05253d5..365fdd3 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h
@@ -11,7 +11,7 @@
#endif
#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20)
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_BASE 0x0
/* Default environemnt variables */
#define CONFIG_SERVERIP 192.168.0.1
diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h
index 2e20654..1c11685 100644
--- a/include/configs/pomelo.h
+++ b/include/configs/pomelo.h
@@ -9,7 +9,7 @@
#define __POMELO_CONFIG_H__
/* SDRAM Bank #1 start address */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* SIZE of malloc pool */
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index f9decb2..bee1ef6 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -36,7 +36,7 @@
#define DDR_BASE 0x00000000
#define PHYS_SDRAM_1 DDR_BASE
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Console I/O Buffer Size */
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 8b151ef..9937615 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -14,7 +14,7 @@
#define GICD_BASE 0xff131000
#define GICC_BASE 0xff132000
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h
index 535762e..a67af73 100644
--- a/include/configs/qemu-arm.h
+++ b/include/configs/qemu-arm.h
@@ -10,7 +10,7 @@
/* Physical memory map */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* GUIDs for capsule updatable firmware images */
#define QEMU_ARM_UBOOT_IMAGE_GUID \
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 9fc51fd..e7c8109 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -31,7 +31,7 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_HWCONFIG
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index d81e5d6..72f35cc 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -8,7 +8,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 406ee62..f6ee720 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -6,8 +6,8 @@
/* SCIF */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x8C000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE 0x8C000000
+#define CFG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 3a38e06..61b9447 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -17,8 +17,8 @@
/* console */
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
-#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
+#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
+#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
/* Timer */
#define CONFIG_TMU_TIMER
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 7432cff..5853072 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -26,8 +26,8 @@
/* MEMORY */
#define DRAM_RSV_SIZE 0x08000000
-#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
-#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index 6616396..b4c1972 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -10,7 +10,7 @@
#define CONFIG_SYS_HZ_CLOCK 24000000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
index 9297184..99c86ed 100644
--- a/include/configs/rk3066_common.h
+++ b/include/configs/rk3066_common.h
@@ -11,7 +11,7 @@
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (1024UL << 20UL)
#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 12d4bc6..fac27a7 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -14,7 +14,7 @@
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_MAX_SIZE 0x80000000
/* usb mass storage */
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 6fe1b2d..334fb3a 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -13,7 +13,7 @@
/* spl size 32kb sram - 2kb bootrom */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0x80000000
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 4fb86b6..6889ba5 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -12,7 +12,7 @@
#define CONFIG_IRAM_BASE 0x10080000
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE 0x80000000
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 81f16ed..4aa7e04 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -15,7 +15,7 @@
/* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0xfe000000
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index 263d1bd..4b510b1 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -10,7 +10,7 @@
#define CONFIG_IRAM_BASE 0xfff80000
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define SDRAM_BANK_SIZE (2UL << 30)
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index 1e214e4..132b7d0 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -11,7 +11,7 @@
#define CONFIG_IRAM_BASE 0xff090000
/* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define ENV_MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 37e0c1d..92cdc1a 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -11,7 +11,7 @@
#include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_IRAM_BASE 0xff8c0000
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 2f9aee5..78f624d 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -21,7 +21,7 @@
/* RAW SD card / eMMC locations. */
/* FAT sd card locations. */
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf8000000
#ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index 15e8152..d43dc25 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -10,7 +10,7 @@
#define CONFIG_IRAM_BASE 0xfdcc0000
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf0000000
#define ENV_MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index cd8fe8b..2c24944 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -23,7 +23,7 @@
#endif
/* Memory layout */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
/*
* The board really has 256M. However, the VC (VideoCore co-processor) shares
@@ -31,7 +31,7 @@
* smaller amount of RAM is present in order to avoid stomping on the area
* the VC uses.
*/
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CFG_SYS_SDRAM_SIZE SZ_128M
/* Devices */
/* LCD */
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 83c3167..76836ad 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -15,7 +15,7 @@
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
/* rockchip ohci host driver */
diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h
index ae94f0e..e071d4d 100644
--- a/include/configs/s5p4418_nanopi2.h
+++ b/include/configs/s5p4418_nanopi2.h
@@ -18,7 +18,7 @@
/*-----------------------------------------------------------------------
* System memory Configuration
*/
-#define CONFIG_SYS_SDRAM_BASE 0x71000000
+#define CFG_SYS_SDRAM_BASE 0x71000000
/*
* "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in
@@ -55,7 +55,7 @@
* Starting kernel ...
* ...
*/
-#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_SDRAM_SIZE (0xb0000000 - CFG_SYS_SDRAM_BASE)
#define BMP_LOAD_ADDR 0x78000000
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index de4510a..ed891ab 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -14,7 +14,7 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
/* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CFG_SYS_SDRAM_BASE 0x30000000
/* Text Base */
@@ -114,7 +114,7 @@
"dfu_alt_info=" CONFIG_DFU_ALT "\0"
/* Goni has 3 banks of DRAM, but swap the bank */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */
#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 668b526..614d04f 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -14,8 +14,8 @@
/* Keep L2 Cache Disabled */
/* Universal has 2 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h
index afb1e3d..75302bf 100644
--- a/include/configs/sam9x60_curiosity.h
+++ b/include/configs/sam9x60_curiosity.h
@@ -17,7 +17,7 @@
#define CONFIG_USART_ID 0 /* ignored in arm */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */
#endif
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index 7c5bfdb..22813d4 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -23,8 +23,8 @@
*/
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h
index de6c92e..f826eab 100644
--- a/include/configs/sama5d27_wlsom1_ek.h
+++ b/include/configs/sama5d27_wlsom1_ek.h
@@ -16,8 +16,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
/* SPL */
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
index ebdb392..01ed1a3 100644
--- a/include/configs/sama5d2_icp.h
+++ b/include/configs/sama5d2_icp.h
@@ -15,8 +15,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SD_BOOT
/* u-boot env in sd/mmc card */
diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
index 09cc4dd..2e3c1ea 100644
--- a/include/configs/sama5d2_ptc_ek.h
+++ b/include/configs/sama5d2_ptc_ek.h
@@ -16,8 +16,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 1c9af9b..4b13a10 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -24,8 +24,8 @@
#define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index afb9b9a..3f58928 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -31,8 +31,8 @@
#endif
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* SerialFlash */
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index 0daadec..084cb4d 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -12,8 +12,8 @@
#include "at91-sama5_common.h"
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index d59899f..cbc1c0f 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -12,8 +12,8 @@
#include "at91-sama5_common.h"
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h
index 3f905bf..68fa31f 100644
--- a/include/configs/sama7g5ek.h
+++ b/include/configs/sama7g5ek.h
@@ -12,7 +12,7 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x60000000
+#define CFG_SYS_SDRAM_SIZE 0x20000000
#endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 0dcb2eb..5a7f5e1 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -13,8 +13,8 @@
/* Size of our emulated memory */
#define SB_CONCAT(x, y) x ## y
#define SB_TO_UL(s) SB_CONCAT(s, UL)
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE \
+#define CFG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_SIZE \
(SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index c9dd750..31552f4 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -33,7 +33,7 @@
/* Physical Memory Map */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
-#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 2e5592c..5ad2124 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 85fab92..f4b1a16 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -11,7 +11,7 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
index 7159fc3..974531e 100644
--- a/include/configs/sipeed-maix.h
+++ b/include/configs/sipeed-maix.h
@@ -8,8 +8,8 @@
#include <linux/sizes.h>
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_8M
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_SIZE SZ_8M
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 7c8f167..d2bc73a 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -45,8 +45,8 @@
* SDRAM: 1 bank, 64 MB, base address 0x20000000
* Already initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M)
/*
* Perform a SDRAM Memtest from the start of SDRAM
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 12c2e1f..0392530 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -14,7 +14,7 @@
#define CONFIG_SMDK5420 /* which is in a SMDK5420 */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index ba562b2..64963ee 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -16,7 +16,7 @@
/* input clock of PLL: SMDKC100 has 12MHz input clock */
/* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE 0x30000000
+#define CFG_SYS_SDRAM_BASE 0x30000000
/* Text Base */
@@ -77,7 +77,7 @@
*/
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */
/*-----------------------------------------------------------------------
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 0b1f0c5..af0c820 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -11,7 +11,7 @@
#include "exynos4-common.h"
/* High Level Configuration Options */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* Handling Sleep Mode*/
#define S5P_CHECK_SLEEP 0x00000BAD
@@ -23,13 +23,13 @@
/* SMDKV310 has 4 bank of DRAM */
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
/* FLASH and environment organization */
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index faa13c6..44b9109 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -38,7 +38,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 7c35c91..9b1cb37 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -21,8 +21,8 @@
/* CPU */
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 6054fa4..9551680 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -32,7 +32,7 @@
* Memory
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/*
* I2C
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 70a24ed..2656c97 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -38,7 +38,7 @@
* in U-Boot pre-reloc is higher than in SPL.
*/
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* U-Boot general configurations
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 2b2d78b..9403e2f 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -70,7 +70,7 @@
*/
#define PHYS_SDRAM_1 0x0
#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CFG_SYS_SDRAM_BASE 0
/*
* Serial / UART configurations
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index a60ac6d..c628860 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -55,7 +55,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
@@ -73,7 +73,7 @@
#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
#define CONFIG_SYS_DDR_CONFIG 0xC3008000
#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
-#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
+#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */
/*
* Flash on the LocalBus
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index dcb88a3..008aa50 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -53,7 +53,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
index 1e966a2..806323e 100644
--- a/include/configs/stih410-b2260.h
+++ b/include/configs/stih410-b2260.h
@@ -11,7 +11,7 @@
/* ram memory-related information */
#define PHYS_SDRAM_1 0x40000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x3E000000
#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */
diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 07a5bfc..d711149 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -13,7 +13,7 @@
/*
* Configuration of the external SRAM memory used by U-Boot
*/
-#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/*
* For booting Linux, use the first 256 MB of memory, since this is
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index b809f93..f78ce41 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h
@@ -13,7 +13,7 @@
/*
* Configuration of the external SRAM memory used by U-Boot
*/
-#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
/*
* For booting Linux, use the first 256 MB of memory, since this is
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index ba49075..234327e 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -56,10 +56,10 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
#define CONFIG_SYS_DRAM_TEST
@@ -75,8 +75,8 @@
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
+ (CFG_SYS_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -89,8 +89,8 @@
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
CF_CACR_ICINVA | CF_CACR_EUSP)
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 567aa1f..b2dcb60 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -10,7 +10,7 @@
/* ram memory-related information */
#define PHYS_SDRAM_1 0x00000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_1_SIZE 0x00198000
/* user interface */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index cd2a74f..e1a66f5 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -42,13 +42,13 @@
*/
#ifdef CONFIG_MACH_SUN9I
#define SDRAM_OFFSET(x) 0x2##x
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
#elif defined(CONFIG_MACH_SUNIV)
#define SDRAM_OFFSET(x) 0x8##x
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#else
#define SDRAM_OFFSET(x) 0x4##x
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* V3s do not have enough memory to place code at 0x4a000000 */
#endif
@@ -66,7 +66,7 @@
/* FIXME: this may be larger on some SoCs */
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
/* mmc config */
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index 63d897d..daa9bbe 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -11,7 +11,7 @@
/*
* SDRAM (for initialize)
*/
-#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index dd1fe0a..1aba986 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -41,8 +41,8 @@
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 92ee920..cd1309b 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -13,8 +13,8 @@
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_128M
/*
* UART configuration
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 7f19785..2d8bde1 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -13,7 +13,7 @@
/* General configuration */
/* Physical Memory Map */
-#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 92df457..7e764b0 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -40,7 +40,7 @@
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index 655fcb0..76b4963 100644
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -68,6 +68,6 @@
/* Defines for SPL */
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_SYS_SDRAM_SIZE SZ_2G
+#define CFG_SYS_SDRAM_SIZE SZ_2G
#endif /* _CONFIG_THEADORABLE_H */
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index cf2efdb..1f60b9b 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -13,7 +13,7 @@
/* Link Definitions */
/* SMP Spin Table Definitions */
-#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0)
/* PL011 Serial Configuration */
@@ -30,7 +30,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial environment variables */
#define UBOOT_IMG_HEAD_SIZE 0x40
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index fc78077..e5b23d2 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -69,7 +69,7 @@
#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/**
* Platform/Board specific defs
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 1bd2a18..4a7c3d5 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -20,7 +20,7 @@
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/**
* Platform/Board specific defs
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index b289b9e..d54c208 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -64,7 +64,7 @@
* initial stack pointer in our SRAM. Otherwise, we can define
* CONFIG_NR_DRAM_BANKS before including this file.
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* If DM_I2C, enable non-DM I2C support */
diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
index ab6cd06..a609aa3 100644
--- a/include/configs/total_compute.h
+++ b/include/configs/total_compute.h
@@ -23,7 +23,7 @@
/* Top 48MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x03000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define PHYS_SDRAM_2 0x8080000000
#define PHYS_SDRAM_2_SIZE 0x180000000
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 22d783c..1378981 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_SDRAM_BASE 0xa0000000
+#define CFG_SYS_SDRAM_BASE 0xa0000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index a65ebfb..f8e3a2d 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -268,7 +268,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/trats.h b/include/configs/trats.h
index ca31868..23dcf20 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -16,8 +16,8 @@
#endif
/* TRATS has 4 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Tizen - partitions definitions */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index f324ea7..9c6433c 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -17,8 +17,8 @@
#endif
/* TRATS2 has 4 banks of DRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
/* Tizen - partitions definitions */
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
index f549f9f..4ca8eaf 100644
--- a/include/configs/turris_mox.h
+++ b/include/configs/turris_mox.h
@@ -8,7 +8,7 @@
#ifndef _CONFIG_TURRIS_MOX_H
#define _CONFIG_TURRIS_MOX_H
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 268c737..c1e80b4 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -49,7 +49,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index 1472248..f730926 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -57,7 +57,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index 2cdc3fb..d2fd23e 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -25,8 +25,8 @@
*/
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index c381934..e944e78 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -60,7 +60,7 @@
#define PHYS_SDRAM CSD0_BASE_ADDR
#define PHYS_SDRAM_SIZE (gd->ram_size)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
index 338d8af..d9e5dfa 100644
--- a/include/configs/vcoreiii.h
+++ b/include/configs/vcoreiii.h
@@ -14,13 +14,13 @@
#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
-#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
-#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M)
#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
-#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
+#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M)
#else
#error Unknown DDR size - please add!
#endif
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index f513dad..b209d97 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -60,7 +60,7 @@
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#endif
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index fea4329..1b9f2ca 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -69,7 +69,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G)
#define PHYS_SDRAM_2 0x100000000
diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h
index 0c11b6b..9a46d50 100644
--- a/include/configs/vexpress_aemv8.h
+++ b/include/configs/vexpress_aemv8.h
@@ -96,7 +96,7 @@
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x01000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define PHYS_SDRAM_2 (0x880000000)
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 5d77306..ef136c7 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -135,7 +135,7 @@
#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
/* additions for new relocation code */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
/* Basic environment settings */
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 215149a..7b526f7 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -123,7 +123,7 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
index a157296..df0e269 100644
--- a/include/configs/vinco.h
+++ b/include/configs/vinco.h
@@ -24,8 +24,8 @@
#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x4000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE 0x4000000
/* MMC */
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index a0846b3..7555d97 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -23,7 +23,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index 2107bec..38b940d 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h
@@ -7,7 +7,7 @@
#define __VOCORE2_CONFIG_H__
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index b4c757f..3acef22 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -89,7 +89,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index a4b12dc..cba215c 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -84,7 +84,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 054eb89..32555c9 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -16,8 +16,8 @@
/*
* Memory configurations
*/
-#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+#define CFG_SYS_SDRAM_SIZE SZ_128M
#define CONFIG_RTC_DS1374
diff --git a/include/configs/xea.h b/include/configs/xea.h
index 19ccf63..87f628d 100644
--- a/include/configs/xea.h
+++ b/include/configs/xea.h
@@ -23,7 +23,7 @@
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Extra Environment */
#define CONFIG_HOSTNAME "xea"
diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h
index 364dae0..612436a 100644
--- a/include/configs/xenguest_arm64.h
+++ b/include/configs/xenguest_arm64.h
@@ -11,7 +11,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_SYS_SDRAM_BASE
+#undef CFG_SYS_SDRAM_BASE
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
index d2c0e91..1b6e26e 100644
--- a/include/configs/xilinx_zynqmp_mini_nand.h
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@@ -12,7 +12,7 @@
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_SDRAM_SIZE 0x1000000
-#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_SDRAM_SIZE 0x1000000
+#define CFG_SYS_SDRAM_BASE 0x0
#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 7d0402f..613ed95 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -21,7 +21,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (128 << 20)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index b93451c..8739bb2 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -42,12 +42,12 @@
*/
#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
+#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
#else
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CFG_SYS_SDRAM_SIZE 0x10000000
#endif
-#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
+#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
@@ -70,12 +70,12 @@
#endif
#if defined(CONFIG_MAX_MEM_MAPPED) && \
- CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
+ CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
#define XTENSA_SYS_TEXT_ADDR \
(MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
#else
#define XTENSA_SYS_TEXT_ADDR \
- (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
+ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
#endif
/*==============================*/
diff --git a/include/init.h b/include/init.h
index d40d11f..699dc24 100644
--- a/include/init.h
+++ b/include/init.h
@@ -90,8 +90,8 @@
*
* If this is not provided, a default implementation will try to set up a
* single bank. It will do this if CONFIG_NR_DRAM_BANKS and
- * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
- * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CFG_SYS_SDRAM_BASE and the size will be determined by a call to
* get_effective_memsize().
*
* Return: 0 if OK, -ve on error
diff --git a/include/system-constants.h b/include/system-constants.h
index 83b41b3..07c3505 100644
--- a/include/system-constants.h
+++ b/include/system-constants.h
@@ -12,7 +12,7 @@
#define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR
#else
#ifdef CONFIG_MIPS
-#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
+#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET)
#else
#define SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index d249942..8deac75 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -467,7 +467,7 @@
{
struct bd_info *bd = gd->bd;
- *vstart = CONFIG_SYS_SDRAM_BASE;
+ *vstart = CFG_SYS_SDRAM_BASE;
*size = (gd->ram_size >= 256 << 20 ?
256 << 20 : gd->ram_size) - (1 << 20);
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 1cc07bc..b5e9f9d 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -208,7 +208,7 @@
* at SDRAM_BASE *device* address (p_paddr field).
* Its size is defined by the p_filesz field.
*/
- phdr->p_paddr = CONFIG_SYS_SDRAM_BASE;
+ phdr->p_paddr = CFG_SYS_SDRAM_BASE;
loaded_firmware_size = phdr->p_filesz;
/*
@@ -231,7 +231,7 @@
unmap_physmem(loaded_firmware, MAP_NOCACHE);
/* Resource table */
- shdr->sh_addr = CONFIG_SYS_SDRAM_BASE;
+ shdr->sh_addr = CFG_SYS_SDRAM_BASE;
rsc_table_size = shdr->sh_size;
loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET;
@@ -243,7 +243,7 @@
/* Load and verify */
ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size,
&rsc_addr, &rsc_size));
- ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE);
+ ut_asserteq(rsc_addr, CFG_SYS_SDRAM_BASE);
ut_asserteq(rsc_size, rsc_table_size);
ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset,
shdr->sh_size);