| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2018 NXP |
| */ |
| |
| #ifndef __IMX8M_CM_H |
| #define __IMX8M_CM_H |
| |
| #include <linux/sizes.h> |
| #include <linux/stringify.h> |
| #include <asm/arch/imx-regs.h> |
| |
| #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) |
| |
| #define CONFIG_SPL_MAX_SIZE (124 * 1024) |
| #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SPL_STACK 0x187FF0 |
| #define CONFIG_SPL_BSS_START_ADDR 0x00180000 |
| #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ |
| #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 |
| #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ |
| #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 |
| |
| /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
| #define CONFIG_MALLOC_F_ADDR 0x182000 |
| /* For RAW image gives a error info not panic */ |
| #define CONFIG_SPL_ABORT_ON_RAW_IMAGE |
| |
| #endif |
| |
| /* ENET Config */ |
| /* ENET1 */ |
| |
| #ifndef CONFIG_SPL_BUILD |
| #define BOOT_TARGET_DEVICES(func) \ |
| func(MMC, mmc, 0) \ |
| func(MMC, mmc, 1) \ |
| func(DHCP, dhcp, na) |
| |
| #include <config_distro_bootcmd.h> |
| #endif |
| |
| /* Initial environment variables */ |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| BOOTENV \ |
| "scriptaddr=0x43500000\0" \ |
| "kernel_addr_r=0x40880000\0" \ |
| "image=Image\0" \ |
| "console=ttymxc0,115200\0" \ |
| "fdt_addr=0x43000000\0" \ |
| "boot_fdt=try\0" \ |
| "fdt_file=imx8mq-cm.dtb\0" \ |
| "initrd_addr=0x43800000\0" \ |
| "bootm_size=0x10000000\0" \ |
| "mmcpart=1\0" \ |
| "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ |
| |
| /* Link Definitions */ |
| |
| #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 |
| #define CONFIG_SYS_INIT_SP_OFFSET \ |
| (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| #define CONFIG_SYS_INIT_SP_ADDR \ |
| (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| |
| |
| #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| #define PHYS_SDRAM 0x40000000 |
| #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ |
| |
| #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR |
| |
| /* Monitor Command Prompt */ |
| #define CONFIG_SYS_CBSIZE 1024 |
| #define CONFIG_SYS_MAXARGS 64 |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| sizeof(CONFIG_SYS_PROMPT) + 16) |
| |
| #define CONFIG_SYS_FSL_USDHC_NUM 2 |
| #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| |
| #endif |