powerpc: dts: p2020: Define L2 cache node
Copy definition of L2 cache node from upstream Linux kernel P2020 dts files.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 0a296cf..1c3f787 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -56,6 +56,14 @@
/include/ "pq3-duart-0.dtsi"
/include/ "pq3-gpio-0.dtsi"
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; /* 32 bytes */
+ cache-size = <0x80000>; /* L2,512K */
+ interrupts = <16 2 0 0>;
+ };
+
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-timer-0.dtsi"
diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi
index 7c4c206..7fdcb85 100644
--- a/arch/powerpc/dts/p2020.dtsi
+++ b/arch/powerpc/dts/p2020.dtsi
@@ -22,10 +22,12 @@
cpu0: PowerPC,P2020@0 {
device_type = "cpu";
reg = <0>;
+ next-level-cache = <&L2>;
};
cpu1: PowerPC,P2020@1 {
device_type = "cpu";
reg = <1>;
+ next-level-cache = <&L2>;
};
};
};