// SPDX-License-Identifier: GPL-2.0+ | |
/* | |
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ | |
*/ | |
/ { | |
memorycontroller: memorycontroller@0298e000 { | |
compatible = "ti,am654-ddrss"; | |
reg = <0x0 0x0298e000 0x0 0x200>, | |
<0x0 0x02980000 0x0 0x4000>, | |
<0x0 0x02988000 0x0 0x2000>; | |
reg-names = "ss", "ctl", "phy"; | |
clocks = <&k3_clks 20 0>; | |
power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>, | |
<&k3_pds 244 TI_SCI_PD_SHARED>; | |
assigned-clocks = <&k3_clks 20 1>; | |
assigned-clock-rates = <DDR_PLL_FREQUENCY>; | |
bootph-pre-ram; | |
ti,ss-reg = < | |
DDRSS_V2H_CTL_REG | |
>; | |
ti,ctl-reg = < | |
DDRCTL_DFIMISC | |
DDRCTL_DFITMG0 | |
DDRCTL_DFITMG1 | |
DDRCTL_DFITMG2 | |
DDRCTL_INIT0 | |
DDRCTL_INIT1 | |
DDRCTL_INIT3 | |
DDRCTL_INIT4 | |
DDRCTL_INIT5 | |
DDRCTL_INIT6 | |
DDRCTL_INIT7 | |
DDRCTL_MSTR | |
DDRCTL_ODTCFG | |
DDRCTL_ODTMAP | |
DDRCTL_RANKCTL | |
DDRCTL_RFSHCTL0 | |
DDRCTL_RFSHTMG | |
DDRCTL_ZQCTL0 | |
DDRCTL_ZQCTL1 | |
>; | |
ti,ctl-crc = < | |
DDRCTL_CRCPARCTL0 | |
DDRCTL_CRCPARCTL1 | |
DDRCTL_CRCPARCTL2 | |
>; | |
ti,ctl-ecc = < | |
DDRCTL_ECCCFG0 | |
>; | |
ti,ctl-map = < | |
DDRCTL_ADDRMAP0 | |
DDRCTL_ADDRMAP1 | |
DDRCTL_ADDRMAP2 | |
DDRCTL_ADDRMAP3 | |
DDRCTL_ADDRMAP4 | |
DDRCTL_ADDRMAP5 | |
DDRCTL_ADDRMAP6 | |
DDRCTL_ADDRMAP7 | |
DDRCTL_ADDRMAP8 | |
DDRCTL_ADDRMAP9 | |
DDRCTL_ADDRMAP10 | |
DDRCTL_ADDRMAP11 | |
DDRCTL_DQMAP0 | |
DDRCTL_DQMAP1 | |
DDRCTL_DQMAP4 | |
DDRCTL_DQMAP5 | |
>; | |
ti,ctl-pwr = < | |
DDRCTL_PWRCTL | |
>; | |
ti,ctl-timing = < | |
DDRCTL_DRAMTMG0 | |
DDRCTL_DRAMTMG1 | |
DDRCTL_DRAMTMG2 | |
DDRCTL_DRAMTMG3 | |
DDRCTL_DRAMTMG4 | |
DDRCTL_DRAMTMG5 | |
DDRCTL_DRAMTMG6 | |
DDRCTL_DRAMTMG7 | |
DDRCTL_DRAMTMG8 | |
DDRCTL_DRAMTMG9 | |
DDRCTL_DRAMTMG11 | |
DDRCTL_DRAMTMG12 | |
DDRCTL_DRAMTMG13 | |
DDRCTL_DRAMTMG14 | |
DDRCTL_DRAMTMG15 | |
DDRCTL_DRAMTMG17 | |
>; | |
ti,phy-cfg = < | |
DDRPHY_DCR | |
DDRPHY_DSGCR | |
DDRPHY_DX0GCR0 | |
DDRPHY_DX0GCR1 | |
DDRPHY_DX0GCR2 | |
DDRPHY_DX0GCR3 | |
DDRPHY_DX0GCR4 | |
DDRPHY_DX0GCR5 | |
DDRPHY_DX0GTR0 | |
DDRPHY_DX1GCR0 | |
DDRPHY_DX1GCR1 | |
DDRPHY_DX1GCR2 | |
DDRPHY_DX1GCR3 | |
DDRPHY_DX1GCR4 | |
DDRPHY_DX1GCR5 | |
DDRPHY_DX1GTR0 | |
DDRPHY_DX2GCR0 | |
DDRPHY_DX2GCR1 | |
DDRPHY_DX2GCR2 | |
DDRPHY_DX2GCR3 | |
DDRPHY_DX2GCR4 | |
DDRPHY_DX2GCR5 | |
DDRPHY_DX2GTR0 | |
DDRPHY_DX3GCR0 | |
DDRPHY_DX3GCR1 | |
DDRPHY_DX3GCR2 | |
DDRPHY_DX3GCR3 | |
DDRPHY_DX3GCR4 | |
DDRPHY_DX3GCR5 | |
DDRPHY_DX3GTR0 | |
DDRPHY_DX4GCR0 | |
DDRPHY_DX4GCR1 | |
DDRPHY_DX4GCR2 | |
DDRPHY_DX4GCR3 | |
DDRPHY_DX4GCR4 | |
DDRPHY_DX4GCR5 | |
DDRPHY_DX4GTR0 | |
DDRPHY_DX8SL0DXCTL2 | |
DDRPHY_DX8SL0IOCR | |
DDRPHY_DX8SL0PLLCR0 | |
DDRPHY_DX8SL0DQSCTL | |
DDRPHY_DX8SL1DXCTL2 | |
DDRPHY_DX8SL1IOCR | |
DDRPHY_DX8SL1PLLCR0 | |
DDRPHY_DX8SL1DQSCTL | |
DDRPHY_DX8SL2DXCTL2 | |
DDRPHY_DX8SL2IOCR | |
DDRPHY_DX8SL2PLLCR0 | |
DDRPHY_DX8SL2DQSCTL | |
DDRPHY_DXCCR | |
DDRPHY_ODTCR | |
DDRPHY_PGCR0 | |
DDRPHY_PGCR1 | |
DDRPHY_PGCR2 | |
DDRPHY_PGCR3 | |
DDRPHY_PGCR5 | |
DDRPHY_PGCR6 | |
>; | |
ti,phy-ctl = < | |
DDRPHY_DTCR0 | |
DDRPHY_DTCR1 | |
DDRPHY_MR0 | |
DDRPHY_MR1 | |
DDRPHY_MR2 | |
DDRPHY_MR3 | |
DDRPHY_MR4 | |
DDRPHY_MR5 | |
DDRPHY_MR6 | |
DDRPHY_MR11 | |
DDRPHY_MR12 | |
DDRPHY_MR13 | |
DDRPHY_MR14 | |
DDRPHY_MR22 | |
DDRPHY_PLLCR0 | |
DDRPHY_VTCR0 | |
>; | |
ti,phy-ioctl = < | |
DDRPHY_ACIOCR0 | |
DDRPHY_ACIOCR3 | |
DDRPHY_ACIOCR5 | |
DDRPHY_IOVCR0 | |
>; | |
ti,phy-timing = < | |
DDRPHY_DTPR0 | |
DDRPHY_DTPR1 | |
DDRPHY_DTPR2 | |
DDRPHY_DTPR3 | |
DDRPHY_DTPR4 | |
DDRPHY_DTPR5 | |
DDRPHY_DTPR6 | |
DDRPHY_PTR2 | |
DDRPHY_PTR3 | |
DDRPHY_PTR4 | |
DDRPHY_PTR5 | |
DDRPHY_PTR6 | |
>; | |
ti,phy-zq = < | |
DDRPHY_ZQ0PR0 | |
DDRPHY_ZQ1PR0 | |
DDRPHY_ZQCR | |
>; | |
}; | |
}; |