| Notes on the Vibren PXA255 IDP. |
| CS1 - alt flash (Mdoc or main flash) |
| CS2 - high speed expansion bus |
| CS3 - Media Q, low speed exp bus |
| - IDE: offset 0x03000000 (abs: 0x17000000) |
| - Eth: offset 0x03400000 (abs: 0x17400000) |
| - core voltage latch: offset 0x03800000 (abs: 0x17800000) |
| - CPLD: offset 0x03C00000 (abs: 0x17C00000) |
| MAX1602EE w/ code pulled high (Cirrus code) |
| vcc vpp A1VCC A0VCC A1VPP A0VPP |
| ===================================================== |
| 3 (vy) 3 (vy) 1 0 0 1 0x9 |
| 3 (vy) 12(12in) 1 0 1 0 0xA |
| 5 (vx) 5 (vx) 0 1 0 1 0x5 |
| 5 (vx 12(12in) 0 1 1 0 0x6 |
| Display power sequencing: |
| - within 1sec, activate scanning signals |
| - wait at least 50mS - scanning signals must be active before activating DISP |
| Schematic LV8V31 signal name |
| ========================================= |
| LCD_PWR Applies VDD to board |
| Both of the above signals are controlled by the CPLD |