include/configs/VOM405.h - filogic/uboot - Gitiles

 /*
  * (C) Copyright 2001-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

 /*
  * board/config.h - configuration options, board specific
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H

 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_VOM405		1	/* ...on a VOM405 board		*/

 #define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
 #define CONFIG_DISPLAY_BOARDINFO

 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

 #undef	CONFIG_BOOTARGS
 #undef  CONFIG_BOOTCOMMAND

 #define CONFIG_PREBOOT                  /* enable preboot variable      */

 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

 #undef  CONFIG_HAS_ETH1

 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_DNS
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME

 /*
  * Command line configuration.
  */
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_EEPROM

 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

 #undef  CONFIG_PRAM			/* no "protected RAM"           */

 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/


 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

 #define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

 #define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()

 #undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD	    691200

 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }

 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

 #define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

 #define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
 #define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
 #define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
 #define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
 #define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
 #define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)

 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT		1
 #else
 # undef CONFIG_SYS_RAMBOOT
 #endif

 /*
  * Environment Variable setup
  */
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */

 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
 #define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/

 /*
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_PPC4XX
 #define CONFIG_SYS_I2C_PPC4XX_CH0
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
 					/* 16 byte page write mode using*/
 					/* last 4 bits of the address	*/
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

 /*
  * External Bus Controller (EBC) Setup
  */
 #define CAN_BA		0xF0000000	    /* CAN Base Address			*/

 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
 #define CONFIG_SYS_EBC_PB0AP		0x92015480
 #define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
 #define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

 /*
  * FPGA stuff
  */
 #define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000

 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
 #define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
 #define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 #define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
 #define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */

 /*
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 #define CONFIG_SYS_TEMP_STACK_OCM	  1

 /* On Chip Memory location */
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
 #define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

 /*
  * Definitions for GPIO setup (PPC405EP specific)
  *
  * GPIO0[0]	- External Bus Controller BLAST output
  * GPIO0[1-9]	- Instruction trace outputs -> GPIO
  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  * GPIO0[24-27] - UART0 control signal inputs/outputs
  * GPIO0[28-29] - UART1 data signal input/output
  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
  */
 /* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
 /* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 #define CONFIG_SYS_GPIO0_OSRL		0x40000500  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */

 /*
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
 #define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33

 #endif	/* __CONFIG_H */
	/*
	* (C) Copyright 2001-2004
	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	*
	* SPDX-License-Identifier: GPL-2.0+
	*/

	/*
	* board/config.h - configuration options, board specific
	*/
	#ifndef __CONFIG_H
	#define __CONFIG_H

	/*
	* High Level Configuration Options
	* (easy to change)
	*/
	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
	#define CONFIG_VOM405 1 /* ...on a VOM405 board */

	#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
	#define CONFIG_DISPLAY_BOARDINFO

	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */

	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */

	#define CONFIG_BAUDRATE 9600
	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */

	#undef CONFIG_BOOTARGS
	#undef CONFIG_BOOTCOMMAND

	#define CONFIG_PREBOOT /* enable preboot variable */

	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

	#undef CONFIG_HAS_ETH1

	#define CONFIG_PPC4xx_EMAC
	#define CONFIG_MII 1 /* MII PHY management */
	#define CONFIG_PHY_ADDR 0 /* PHY address */
	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */

	/*
	* BOOTP options
	*/
	#define CONFIG_BOOTP_SUBNETMASK
	#define CONFIG_BOOTP_GATEWAY
	#define CONFIG_BOOTP_HOSTNAME
	#define CONFIG_BOOTP_BOOTPATH
	#define CONFIG_BOOTP_DNS
	#define CONFIG_BOOTP_DNS2
	#define CONFIG_BOOTP_SEND_HOSTNAME

	/*
	* Command line configuration.
	*/
	#define CONFIG_CMD_DHCP
	#define CONFIG_CMD_BSP
	#define CONFIG_CMD_IRQ
	#define CONFIG_CMD_I2C
	#define CONFIG_CMD_MII
	#define CONFIG_CMD_PING
	#define CONFIG_CMD_EEPROM

	#undef CONFIG_WATCHDOG /* watchdog disabled */

	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

	#undef CONFIG_PRAM /* no "protected RAM" */

	/*
	* Miscellaneous configurable options
	*/
	#define CONFIG_SYS_LONGHELP /* undef to save memory */


	#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	#else
	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	#endif
	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */

	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/

	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */

	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	#define CONFIG_SYS_NS16550_SERIAL
	#define CONFIG_SYS_NS16550_REG_SIZE 1
	#define CONFIG_SYS_NS16550_CLK get_serial_clock()

	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
	#define CONFIG_SYS_BASE_BAUD 691200

	/* The following table includes the supported baudrates */
	#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	57600, 115200, 230400, 460800, 921600 }

	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */

	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */

	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */

	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */

	/*
	* For booting Linux, the board info and command line data
	* have to be in the first 8 MB of memory, since this is
	* the maximum mapped by the Linux kernel during initialization.
	*/
	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	/*
	* FLASH organization
	*/
	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */

	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */

	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */

	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
	/*
	* The following defines are added for buggy IOP480 byte interface.
	* All other boards should use the standard values (CPCI405 etc.)
	*/
	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */

	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */

	/*
	* Start addresses for the final memory configuration
	* (Set up by the startup code)
	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	*/
	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)

	#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
	# define CONFIG_SYS_RAMBOOT 1
	#else
	# undef CONFIG_SYS_RAMBOOT
	#endif

	/*
	* Environment Variable setup
	*/
	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
	#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
	/* total size of a CAT24WC16 is 2048 bytes */

	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
	#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */

	/*
	* I2C EEPROM (CAT24WC16) for environment
	*/
	#define CONFIG_SYS_I2C
	#define CONFIG_SYS_I2C_PPC4XX
	#define CONFIG_SYS_I2C_PPC4XX_CH0
	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F

	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	/* mask of address bits that overflow into the "EEPROM chip address" */
	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	/* 16 byte page write mode using*/
	/* last 4 bits of the address */
	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */

	/*
	* External Bus Controller (EBC) Setup
	*/
	#define CAN_BA 0xF0000000 /* CAN Base Address */

	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
	#define CONFIG_SYS_EBC_PB0AP 0x92015480
	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */

	/*
	* FPGA stuff
	*/
	#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000

	/* FPGA program pin configuration */
	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
	#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
	#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */

	/*
	* Definitions for initial stack pointer and data area (in data cache)
	*/
	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	#define CONFIG_SYS_TEMP_STACK_OCM 1

	/* On Chip Memory location */
	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */

	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

	/*
	* Definitions for GPIO setup (PPC405EP specific)
	*
	* GPIO0[0] - External Bus Controller BLAST output
	* GPIO0[1-9] - Instruction trace outputs -> GPIO
	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	* GPIO0[24-27] - UART0 control signal inputs/outputs
	* GPIO0[28-29] - UART1 data signal input/output
	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	*/
	/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
	/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
	/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
	/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
	#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
	#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
	#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
	#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
	#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
	#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
	#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */

	/*
	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	* This value will be set if iic boot eprom is disabled.
	*/
	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33

	#endif /* __CONFIG_H */