ddr: altera: Add DDR driver for Agilex5 series
Adding DDR driver support for Agilex5 series.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 540b266..e08dd55 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -22,11 +22,38 @@
};
};
- memory {
- /* 8GB */
- reg = <0 0x80000000 0 0x80000000>,
- <8 0x80000000 1 0x80000000>;
- };
+ /*
+ * Both Memory base address and size default info is retrieved from HW setting.
+ * Reconfiguration / Overwrite these info can be done with examples below.
+ */
+ /*
+ * Example for memory size with 2GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 8GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 32GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 512GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>,
+ * <0x88 0x00000000 0x78 0x00000000>;
+ * };
+ */
chosen {
stdout-path = "serial0:115200n8";