ddr: altera: Add DDR driver for Agilex5 series
Adding DDR driver support for Agilex5 series.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index af3f5d3..8d6503d 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -389,6 +389,230 @@
};
};
+ socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* DSU */
+ i_ccu_caiu0@1c000000 {
+ reg = <0x1c000000 0x00001000>;
+ intel,offset-settings =
+ /* CAIUAMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* FPGA2SOC */
+ i_ccu_ncaiu0@1c001000 {
+ reg = <0x1c001000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU0AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* GIC_M */
+ i_ccu_ncaiu1@1c002000 {
+ reg = <0x1c002000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU1AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* SMMU */
+ i_ccu_ncaiu2@1c003000 {
+ reg = <0x1c003000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU2AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* PSS NOC */
+ i_ccu_ncaiu3@1c004000 {
+ reg = <0x1c004000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU3AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE0 */
+ i_ccu_dce0@1c005000 {
+ reg = <0x1c005000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR0 */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE1 */
+ i_ccu_dce1@1c006000 {
+ reg = <0x1c006000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR1 */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+ };
+
+ socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* DSU */
+ i_ccu_caiu0@1c000000 {
+ reg = <0x1c000000 0x00001000>;
+ intel,offset-settings =
+ /* CAIUAMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* FPGA2SOC */
+ i_ccu_ncaiu0@1c001000 {
+ reg = <0x1c001000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU0AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* GIC_M */
+ i_ccu_ncaiu1@1c002000 {
+ reg = <0x1c002000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU1AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* SMMU */
+ i_ccu_ncaiu2@1c003000 {
+ reg = <0x1c003000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU2AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* PSS NOC */
+ i_ccu_ncaiu3@1c004000 {
+ reg = <0x1c004000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU3AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE0 */
+ i_ccu_dce0@1c005000 {
+ reg = <0x1c005000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR0 */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE1 */
+ i_ccu_dce1@1c006000 {
+ reg = <0x1c006000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR1 */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+ };
+
socfpga_smmu_secure_config: socfpga-smmu-secure-config {
compatible = "intel,socfpga-dtreg";
#address-cells = <1>;
@@ -422,6 +646,26 @@
bootph-all;
};
};
+
+ socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* noc fw mpfe csr */
+ i_noc_fw_mpfe_csr@18000d00 {
+ reg = <0x18000d00 0x00000100>;
+ intel,offset-settings =
+ /* mpfe scr io96b0 reg*/
+ <0x00000000 0x00000001 0x00010101>,
+ /* mpfe scr io96b1 reg*/
+ <0x00000004 0x00000001 0x00010101>,
+ /* mpfe scr noc csr*/
+ <0x00000008 0x00000001 0x00010101>;
+ bootph-all;
+ };
+ };
};
};
@@ -467,6 +711,13 @@
bootph-all;
};
+&sdr {
+ compatible = "intel,sdr-ctl-agilex5";
+ reg = <0x18000000 0x400000>;
+ resets = <&rst DDRSCH_RESET>;
+ bootph-all;
+};
+
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
bootph-all;
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
index 03b5504..788e44f 100644
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
/dts-v1/;
@@ -544,6 +545,13 @@
status = "disabled";
};
+ sdr: sdr@18000000 {
+ compatible = "intel,sdr-ctl-agilex5";
+ reg = <0x18000000 0x400000>;
+ resets = <&rst DDRSCH_RESET>;
+ bootph-all;
+ };
+
/* QSPI address not available yet */
qspi: spi@108d2000 {
compatible = "cdns,qspi-nor";
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 540b266..e08dd55 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -22,11 +22,38 @@
};
};
- memory {
- /* 8GB */
- reg = <0 0x80000000 0 0x80000000>,
- <8 0x80000000 1 0x80000000>;
- };
+ /*
+ * Both Memory base address and size default info is retrieved from HW setting.
+ * Reconfiguration / Overwrite these info can be done with examples below.
+ */
+ /*
+ * Example for memory size with 2GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 8GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 32GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 512GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>,
+ * <0x88 0x00000000 0x78 0x00000000>;
+ * };
+ */
chosen {
stdout-path = "serial0:115200n8";
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index d07b3fc..27072e5 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -6,23 +6,24 @@
*/
#include <config.h>
-#include <asm/arch/board.h>
-#include <asm/arch/clock_manager.h>
-#include <asm/arch/mailbox_s10.h>
-#include <asm/arch/misc.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/secure_vab.h>
-#include <asm/arch/smc_api.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
#include <errno.h>
#include <fdtdec.h>
+#include <log.h>
+#include <init.h>
#include <hang.h>
+#include <handoff.h>
#include <image.h>
-#include <init.h>
-#include <log.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
+#include <bloblist.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -58,7 +59,18 @@
int dram_init_banksize(void)
{
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#ifndef CONFIG_SPL_BUILD
+ struct spl_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+ handoff_load_dram_banks(ho);
+#endif
+#else
fdtdec_setup_memory_banksize();
+#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
return 0;
}
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23..2b436b64 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
@@ -126,11 +127,27 @@
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff
+/* Firewall F2SDRAM DDR SCR registers */
+#define FW_F2SDRAM_DDR_SCR_EN 0x00
+#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c
+
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
+ writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \
+ writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg))
+#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \
+ writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg))
+#else
#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
+#endif
void firewall_setup(void);
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fbe3af8..97e0114 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -5,27 +5,29 @@
#include <config.h>
#include <command.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <asm/cache.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
#include <errno.h>
+#include <init.h>
+#include <handoff.h>
+#include <hang.h>
+#include <watchdog.h>
#include <fdtdec.h>
#include <linux/libfdt.h>
-#include <altera.h>
+#include <linux/printk.h>
#include <miiphy.h>
#include <netdev.h>
-#include <watchdog.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/pl310.h>
#include <asm/arch/misc.h>
+#include <asm/arch/nic301.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/scan_manager.h>
-#include <asm/arch/system_manager.h>
-#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
-#include <asm/pl310.h>
-#include <linux/printk.h>
+#include <asm/arch/system_manager.h>
+#include <altera.h>
+#include <bloblist.h>
+#include <cpu_func.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,8 +53,18 @@
int dram_init(void)
{
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ struct spl_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+ gd->ram_size = ho->ram_bank[0].size;
+ gd->ram_base = ho->ram_bank[0].start;
+#else
if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
+#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
return 0;
}
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index 793b8b8..e0b2b42 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,17 +6,18 @@
*/
#include <altera.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
#include <asm/arch/board.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
+#include <asm/system.h>
#include <asm/global_data.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <log.h>
#include <mach/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,19 @@
};
/*
+ * The Agilex5 platform has enabled the bloblist feature, and the bloblist
+ * address and size are initialized based on the defconfig settings.
+ * During the SPL phase, this function is used to prevent the bloblist
+ * from initializing its address and size with the saved boot parameters,
+ * which may have been incorrectly set.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+{
+ save_boot_params_ret();
+}
+
+/*
* Print CPU information
*/
#if defined(CONFIG_DISPLAY_CPUINFO)