// SPDX-License-Identifier: GPL-2.0+ | |
/* | |
* Copyright 2019 NXP | |
*/ | |
#include "imx8mm-u-boot.dtsi" | |
/ { | |
wdt-reboot { | |
compatible = "wdt-reboot"; | |
wdt = <&wdog1>; | |
bootph-pre-ram; | |
}; | |
}; | |
&aips4 { | |
bootph-pre-ram; | |
}; | |
®_usdhc2_vmmc { | |
u-boot,off-on-delay-us = <20000>; | |
}; | |
&pinctrl_reg_usdhc2_vmmc { | |
bootph-pre-ram; | |
}; | |
&pinctrl_uart2 { | |
bootph-pre-ram; | |
}; | |
&pinctrl_usdhc2_gpio { | |
bootph-pre-ram; | |
}; | |
&pinctrl_usdhc2 { | |
bootph-pre-ram; | |
}; | |
&pinctrl_usdhc3 { | |
bootph-pre-ram; | |
}; | |
&gpio1 { | |
bootph-pre-ram; | |
}; | |
&gpio2 { | |
bootph-pre-ram; | |
}; | |
&gpio3 { | |
bootph-pre-ram; | |
}; | |
&gpio4 { | |
bootph-pre-ram; | |
}; | |
&gpio5 { | |
bootph-pre-ram; | |
}; | |
&uart2 { | |
bootph-pre-ram; | |
}; | |
&usbmisc1 { | |
bootph-pre-ram; | |
}; | |
&usbphynop1 { | |
bootph-pre-ram; | |
}; | |
&usbotg1 { | |
bootph-pre-ram; | |
}; | |
&usdhc1 { | |
bootph-pre-ram; | |
}; | |
&usdhc2 { | |
bootph-pre-ram; | |
sd-uhs-sdr104; | |
sd-uhs-ddr50; | |
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; | |
assigned-clock-rates = <400000000>; | |
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; | |
}; | |
&usdhc3 { | |
bootph-pre-ram; | |
mmc-hs400-1_8v; | |
mmc-hs400-enhanced-strobe; | |
/* | |
* prevents voltage switch warn: driver will switch even at | |
* fixed voltage | |
*/ | |
/delete-property/ vmmc-supply; | |
/delete-property/ vqmmc-supply; | |
assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; | |
assigned-clock-rates = <400000000>; | |
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; | |
}; | |
&i2c1 { | |
bootph-pre-ram; | |
}; | |
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { | |
bootph-pre-ram; | |
}; | |
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { | |
bootph-pre-ram; | |
}; | |
&pinctrl_i2c1 { | |
bootph-pre-ram; | |
}; | |
&pinctrl_pmic { | |
bootph-pre-ram; | |
}; | |
&wdog1 { | |
bootph-pre-ram; | |
}; |