// SPDX-License-Identifier: GPL-2.0 | |
/* | |
* Copyright 2022 Google LLC | |
*/ | |
/dts-v1/; | |
#include "socfpga_arria10_mercury_aa1.dtsi" | |
/ { | |
model = "Google Chameleon V3"; | |
compatible = "google,chameleon-v3", | |
"altr,socfpga-arria10", "altr,socfpga"; | |
aliases { | |
serial0 = &uart0; | |
i2c0 = &i2c0; | |
i2c1 = &i2c1; | |
}; | |
}; | |
&gmac0 { | |
status = "okay"; | |
}; | |
&gpio0 { | |
status = "okay"; | |
}; | |
&gpio1 { | |
status = "okay"; | |
}; | |
&gpio2 { | |
status = "okay"; | |
}; | |
&i2c0 { | |
status = "okay"; | |
ssm2603: ssm2603@1a { | |
compatible = "adi,ssm2603"; | |
reg = <0x1a>; | |
}; | |
}; | |
&i2c1 { | |
status = "okay"; | |
u80: u80@21 { | |
compatible = "nxp,pca9535"; | |
reg = <0x21>; | |
gpio-controller; | |
#gpio-cells = <2>; | |
gpio-line-names = | |
"SOM_AUD_MUTE", | |
"DP1_OUT_CEC_EN", | |
"DP2_OUT_CEC_EN", | |
"DP1_SOM_PS8469_CAD", | |
"DPD_SOM_PS8469_CAD", | |
"DP_OUT_PWR_EN", | |
"STM32_RST_L", | |
"STM32_BOOT0", | |
"FPGA_PROT", | |
"STM32_FPGA_COMM0", | |
"TP119", | |
"TP120", | |
"TP121", | |
"TP122", | |
"TP123", | |
"TP124"; | |
}; | |
}; | |
&mmc { | |
status = "okay"; | |
}; | |
&uart0 { | |
status = "okay"; | |
}; | |
&uart1 { | |
status = "okay"; | |
}; | |
&usb0 { | |
status = "okay"; | |
dr_mode = "host"; | |
}; |