Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
uboot
/
9ed6823e81e01974adf50dbaa86886c4ba7ee76d
/
.
/
board
/
freescale
/
t208xqds
/
t2081_rcw.cfg
blob: a2d5ecf4adca9deda3dd48bd591392fb9201aa98 [
file
] [
log
] [
blame
]
#PBL preamble and RCW header
aa55aa55
010e0100
#Default SerDes Protocol: 0x6C
#Core/DDR: 1533Mhz/2133MT/s
12100017
15000000
00000000
00000000
6c000002
00008000
e8104000 c1000000
00000000
00000000
00000000
000307fc
00000000
00000000
00000000
00000004