/* SPDX-License-Identifier: GPL-2.0 */ | |
/* | |
* Copyright (C) 2020 MediaTek Inc. | |
* | |
* Author: Weijie Gao <weijie.gao@mediatek.com> | |
*/ | |
#ifndef _DT_BINDINGS_MT7620_RESET_H_ | |
#define _DT_BINDINGS_MT7620_RESET_H_ | |
#define PPE_RST 31 | |
#define SDHC_RST 30 | |
#define MIPS_CNT_RST 28 | |
#define PCIE_RST 26 | |
#define UHST_RST 25 | |
#define EPHY_RST 24 | |
#define ESW_RST 23 | |
#define UDEV_RST 22 | |
#define FE_RST 21 | |
#define WLAN_RST 20 | |
#define UARTL_RST 19 | |
#define SPI_RST 18 | |
#define I2S_RST 17 | |
#define I2C_RST 16 | |
#define NAND_RST 15 | |
#define DMA_RST 14 | |
#define PIO_RST 13 | |
#define UARTF_RST 12 | |
#define PCM_RST 11 | |
#define MC_RST 10 | |
#define INTC_RST 9 | |
#define TIMER_RST 8 | |
#define SYS_RST 0 | |
#endif /* _DT_BINDINGS_MT7620_RESET_H_ */ |