// SPDX-License-Identifier: GPL-2.0+ | |
/* | |
* Copyright 2022 NXP | |
*/ | |
/ { | |
wdt-reboot { | |
compatible = "wdt-reboot"; | |
wdt = <&wdog3>; | |
bootph-pre-ram; | |
}; | |
firmware { | |
optee { | |
compatible = "linaro,optee-tz"; | |
method = "smc"; | |
}; | |
}; | |
}; | |
&{/soc@0} { | |
bootph-all; | |
bootph-pre-ram; | |
}; | |
&aips1 { | |
bootph-pre-ram; | |
bootph-all; | |
}; | |
&aips2 { | |
bootph-pre-ram; | |
}; | |
&aips3 { | |
bootph-pre-ram; | |
}; | |
&iomuxc { | |
bootph-pre-ram; | |
}; | |
®_usdhc2_vmmc { | |
u-boot,off-on-delay-us = <20000>; | |
bootph-pre-ram; | |
}; | |
&pinctrl_reg_usdhc2_vmmc { | |
bootph-pre-ram; | |
}; | |
&pinctrl_uart1 { | |
bootph-pre-ram; | |
}; | |
&pinctrl_usdhc2_gpio { | |
bootph-pre-ram; | |
}; | |
&pinctrl_usdhc2 { | |
bootph-pre-ram; | |
}; | |
&gpio1 { | |
bootph-pre-ram; | |
}; | |
&gpio2 { | |
bootph-pre-ram; | |
}; | |
&gpio3 { | |
bootph-pre-ram; | |
}; | |
&gpio4 { | |
bootph-pre-ram; | |
}; | |
&lpuart1 { | |
bootph-pre-ram; | |
}; | |
&usdhc1 { | |
bootph-pre-ram; | |
}; | |
&usdhc2 { | |
bootph-pre-ram; | |
fsl,signal-voltage-switch-extra-delay-ms = <8>; | |
}; | |
&lpi2c2 { | |
bootph-pre-ram; | |
}; | |
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { | |
bootph-pre-ram; | |
}; | |
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { | |
bootph-pre-ram; | |
}; | |
&pinctrl_lpi2c2 { | |
bootph-pre-ram; | |
}; | |
&fec { | |
phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; | |
phy-reset-duration = <15>; | |
phy-reset-post-delay = <100>; | |
}; | |
&eqos { | |
compatible = "fsl,imx-eqos"; | |
}; | |
ðphy1 { | |
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; | |
reset-assert-us = <15000>; | |
reset-deassert-us = <100000>; | |
}; | |
&s4muap { | |
bootph-pre-ram; | |
status = "okay"; | |
}; |