// SPDX-License-Identifier: GPL-2.0 | |
/* | |
* Device Tree Source for AM6 SoC family in Quad core configuration | |
* | |
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ | |
*/ | |
#include "k3-am65.dtsi" | |
/ { | |
cpus { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
cpu-map { | |
cluster0: cluster0 { | |
core0 { | |
cpu = <&cpu0>; | |
}; | |
core1 { | |
cpu = <&cpu1>; | |
}; | |
}; | |
cluster1: cluster1 { | |
core0 { | |
cpu = <&cpu2>; | |
}; | |
core1 { | |
cpu = <&cpu3>; | |
}; | |
}; | |
}; | |
cpu0: cpu@0 { | |
compatible = "arm,cortex-a53"; | |
reg = <0x000>; | |
device_type = "cpu"; | |
enable-method = "psci"; | |
i-cache-size = <0x8000>; | |
i-cache-line-size = <64>; | |
i-cache-sets = <256>; | |
d-cache-size = <0x8000>; | |
d-cache-line-size = <64>; | |
d-cache-sets = <128>; | |
next-level-cache = <&L2_0>; | |
}; | |
cpu1: cpu@1 { | |
compatible = "arm,cortex-a53"; | |
reg = <0x001>; | |
device_type = "cpu"; | |
enable-method = "psci"; | |
i-cache-size = <0x8000>; | |
i-cache-line-size = <64>; | |
i-cache-sets = <256>; | |
d-cache-size = <0x8000>; | |
d-cache-line-size = <64>; | |
d-cache-sets = <128>; | |
next-level-cache = <&L2_0>; | |
}; | |
cpu2: cpu@100 { | |
compatible = "arm,cortex-a53"; | |
reg = <0x100>; | |
device_type = "cpu"; | |
enable-method = "psci"; | |
i-cache-size = <0x8000>; | |
i-cache-line-size = <64>; | |
i-cache-sets = <256>; | |
d-cache-size = <0x8000>; | |
d-cache-line-size = <64>; | |
d-cache-sets = <128>; | |
next-level-cache = <&L2_1>; | |
}; | |
cpu3: cpu@101 { | |
compatible = "arm,cortex-a53"; | |
reg = <0x101>; | |
device_type = "cpu"; | |
enable-method = "psci"; | |
i-cache-size = <0x8000>; | |
i-cache-line-size = <64>; | |
i-cache-sets = <256>; | |
d-cache-size = <0x8000>; | |
d-cache-line-size = <64>; | |
d-cache-sets = <128>; | |
next-level-cache = <&L2_1>; | |
}; | |
}; | |
L2_0: l2-cache0 { | |
compatible = "cache"; | |
cache-level = <2>; | |
cache-size = <0x80000>; | |
cache-line-size = <64>; | |
cache-sets = <512>; | |
next-level-cache = <&msmc_l3>; | |
}; | |
L2_1: l2-cache1 { | |
compatible = "cache"; | |
cache-level = <2>; | |
cache-size = <0x80000>; | |
cache-line-size = <64>; | |
cache-sets = <512>; | |
next-level-cache = <&msmc_l3>; | |
}; | |
msmc_l3: l3-cache0 { | |
compatible = "cache"; | |
cache-level = <3>; | |
}; | |
}; |