| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| /* |
| * Device Tree Source for the RZ/G2UL SoC |
| * |
| * Copyright (C) 2022 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr |
| |
| #include "r9a07g043.dtsi" |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a55"; |
| reg = <0>; |
| device_type = "cpu"; |
| #cooling-cells = <2>; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| L3_CA55: cache-controller-0 { |
| compatible = "cache"; |
| cache-unified; |
| cache-size = <0x40000>; |
| cache-level = <3>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, |
| <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", |
| "hyp-virt"; |
| }; |
| }; |
| |
| &soc { |
| interrupt-parent = <&gic>; |
| |
| cru: video@10830000 { |
| compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; |
| reg = <0 0x10830000 0 0x400>; |
| clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>, |
| <&cpg CPG_MOD R9A07G043_CRU_PCLK>, |
| <&cpg CPG_MOD R9A07G043_CRU_ACLK>; |
| clock-names = "video", "apb", "axi"; |
| interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; |
| resets = <&cpg R9A07G043_CRU_PRESETN>, |
| <&cpg R9A07G043_CRU_ARESETN>; |
| reset-names = "presetn", "aresetn"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg = <1>; |
| crucsi2: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&csi2cru>; |
| }; |
| }; |
| }; |
| }; |
| |
| csi2: csi2@10830400 { |
| compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2"; |
| reg = <0 0x10830400 0 0xfc00>; |
| interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>, |
| <&cpg CPG_MOD R9A07G043_CRU_VCLK>, |
| <&cpg CPG_MOD R9A07G043_CRU_PCLK>; |
| clock-names = "system", "video", "apb"; |
| resets = <&cpg R9A07G043_CRU_PRESETN>, |
| <&cpg R9A07G043_CRU_CMN_RSTB>; |
| reset-names = "presetn", "cmn-rstb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| }; |
| |
| port@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| |
| csi2cru: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&crucsi2>; |
| }; |
| }; |
| }; |
| }; |
| |
| irqc: interrupt-controller@110a0000 { |
| compatible = "renesas,r9a07g043u-irqc", |
| "renesas,rzg2l-irqc"; |
| reg = <0 0x110a0000 0 0x10000>; |
| #interrupt-cells = <2>; |
| #address-cells = <0>; |
| interrupt-controller; |
| interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>, |
| <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>, |
| <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>, |
| <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>, |
| <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>, |
| <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>, |
| <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "nmi", |
| "irq0", "irq1", "irq2", "irq3", |
| "irq4", "irq5", "irq6", "irq7", |
| "tint0", "tint1", "tint2", "tint3", |
| "tint4", "tint5", "tint6", "tint7", |
| "tint8", "tint9", "tint10", "tint11", |
| "tint12", "tint13", "tint14", "tint15", |
| "tint16", "tint17", "tint18", "tint19", |
| "tint20", "tint21", "tint22", "tint23", |
| "tint24", "tint25", "tint26", "tint27", |
| "tint28", "tint29", "tint30", "tint31", |
| "bus-err", "ec7tie1-0", "ec7tie2-0", |
| "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", |
| "ec7tiovf-1"; |
| clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, |
| <&cpg CPG_MOD R9A07G043_IA55_PCLK>; |
| clock-names = "clk", "pclk"; |
| power-domains = <&cpg>; |
| resets = <&cpg R9A07G043_IA55_RESETN>; |
| }; |
| |
| gic: interrupt-controller@11900000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0x11900000 0 0x40000>, |
| <0x0 0x11940000 0 0x60000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
| |
| &sysc { |
| interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, |
| <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "lpm_int", "ca55stbydone_int", |
| "cm33stbyr_int", "ca55_deny"; |
| }; |