| /* |
| * Copyright 2014 Freescale Semiconductor, Inc. |
| * |
| * Configuration settings for the Freescale i.MX6SX Sabresd board. |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| #include "mx6_common.h" |
| |
| #ifdef CONFIG_SPL |
| #include "imx6_spl.h" |
| #endif |
| |
| /* Size of malloc() pool */ |
| #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) |
| |
| #define CONFIG_BOARD_EARLY_INIT_F |
| |
| #define CONFIG_MXC_UART |
| #define CONFIG_MXC_UART_BASE UART1_BASE |
| |
| #ifdef CONFIG_IMX_BOOTAUX |
| /* Set to QSPI2 B flash at default */ |
| #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 |
| |
| #define UPDATE_M4_ENV \ |
| "m4image=m4_qspi.bin\0" \ |
| "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ |
| "update_m4_from_sd=" \ |
| "if sf probe 1:0; then " \ |
| "if run loadm4image; then " \ |
| "setexpr fw_sz ${filesize} + 0xffff; " \ |
| "setexpr fw_sz ${fw_sz} / 0x10000; " \ |
| "setexpr fw_sz ${fw_sz} * 0x10000; " \ |
| "sf erase 0x0 ${fw_sz}; " \ |
| "sf write ${loadaddr} 0x0 ${filesize}; " \ |
| "fi; " \ |
| "fi\0" \ |
| "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" |
| #else |
| #define UPDATE_M4_ENV "" |
| #endif |
| |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| UPDATE_M4_ENV \ |
| "script=boot.scr\0" \ |
| "image=zImage\0" \ |
| "console=ttymxc0\0" \ |
| "fdt_high=0xffffffff\0" \ |
| "initrd_high=0xffffffff\0" \ |
| "fdt_file=imx6sx-sdb.dtb\0" \ |
| "fdt_addr=0x88000000\0" \ |
| "boot_fdt=try\0" \ |
| "ip_dyn=yes\0" \ |
| "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ |
| "mmcdev=2\0" \ |
| "mmcpart=1\0" \ |
| "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ |
| "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
| "root=${mmcroot}\0" \ |
| "loadbootscript=" \ |
| "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
| "bootscript=echo Running bootscript from mmc ...; " \ |
| "source\0" \ |
| "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
| "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
| "mmcboot=echo Booting from mmc ...; " \ |
| "run mmcargs; " \ |
| "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
| "if run loadfdt; then " \ |
| "bootz ${loadaddr} - ${fdt_addr}; " \ |
| "else " \ |
| "if test ${boot_fdt} = try; then " \ |
| "bootz; " \ |
| "else " \ |
| "echo WARN: Cannot load the DT; " \ |
| "fi; " \ |
| "fi; " \ |
| "else " \ |
| "bootz; " \ |
| "fi;\0" \ |
| "netargs=setenv bootargs console=${console},${baudrate} " \ |
| "root=/dev/nfs " \ |
| "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ |
| "netboot=echo Booting from net ...; " \ |
| "run netargs; " \ |
| "if test ${ip_dyn} = yes; then " \ |
| "setenv get_cmd dhcp; " \ |
| "else " \ |
| "setenv get_cmd tftp; " \ |
| "fi; " \ |
| "${get_cmd} ${image}; " \ |
| "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
| "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ |
| "bootz ${loadaddr} - ${fdt_addr}; " \ |
| "else " \ |
| "if test ${boot_fdt} = try; then " \ |
| "bootz; " \ |
| "else " \ |
| "echo WARN: Cannot load the DT; " \ |
| "fi; " \ |
| "fi; " \ |
| "else " \ |
| "bootz; " \ |
| "fi;\0" |
| |
| #define CONFIG_BOOTCOMMAND \ |
| "mmc dev ${mmcdev};" \ |
| "mmc dev ${mmcdev}; if mmc rescan; then " \ |
| "if run loadbootscript; then " \ |
| "run bootscript; " \ |
| "else " \ |
| "if run loadimage; then " \ |
| "run mmcboot; " \ |
| "else run netboot; " \ |
| "fi; " \ |
| "fi; " \ |
| "else run netboot; fi" |
| |
| /* Miscellaneous configurable options */ |
| #define CONFIG_SYS_MEMTEST_START 0x80000000 |
| #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) |
| |
| #define CONFIG_STACKSIZE SZ_128K |
| |
| /* Physical Memory Map */ |
| #define CONFIG_NR_DRAM_BANKS 1 |
| #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| |
| #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| |
| #define CONFIG_SYS_INIT_SP_OFFSET \ |
| (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| #define CONFIG_SYS_INIT_SP_ADDR \ |
| (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| |
| /* MMC Configuration */ |
| #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR |
| |
| /* I2C Configs */ |
| #define CONFIG_SYS_I2C |
| #define CONFIG_SYS_I2C_MXC |
| #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
| #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
| #define CONFIG_SYS_I2C_SPEED 100000 |
| |
| /* PMIC */ |
| #define CONFIG_POWER |
| #define CONFIG_POWER_I2C |
| #define CONFIG_POWER_PFUZE100 |
| #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 |
| |
| /* Network */ |
| #define CONFIG_FEC_MXC |
| #define CONFIG_MII |
| |
| #define IMX_FEC_BASE ENET_BASE_ADDR |
| #define CONFIG_FEC_MXC_PHYADDR 0x1 |
| |
| #define CONFIG_FEC_XCV_TYPE RGMII |
| #define CONFIG_ETHPRIME "FEC" |
| |
| #define CONFIG_PHYLIB |
| #define CONFIG_PHY_ATHEROS |
| |
| #ifdef CONFIG_CMD_USB |
| #define CONFIG_USB_EHCI |
| #define CONFIG_USB_EHCI_MX6 |
| #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| #define CONFIG_USB_HOST_ETHER |
| #define CONFIG_USB_ETHER_ASIX |
| #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| #define CONFIG_MXC_USB_FLAGS 0 |
| #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| #endif |
| |
| #define CONFIG_CMD_PCI |
| #ifdef CONFIG_CMD_PCI |
| #define CONFIG_PCI |
| #define CONFIG_PCI_PNP |
| #define CONFIG_PCI_SCAN_SHOW |
| #define CONFIG_PCIE_IMX |
| #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) |
| #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) |
| #endif |
| |
| #define CONFIG_IMX_THERMAL |
| |
| #ifdef CONFIG_FSL_QSPI |
| #define CONFIG_SYS_FSL_QSPI_LE |
| #define CONFIG_SYS_FSL_QSPI_AHB |
| #ifdef CONFIG_MX6SX_SABRESD_REVA |
| #define FSL_QSPI_FLASH_SIZE SZ_16M |
| #else |
| #define FSL_QSPI_FLASH_SIZE SZ_32M |
| #endif |
| #define FSL_QSPI_FLASH_NUM 2 |
| #endif |
| |
| #ifndef CONFIG_SPL_BUILD |
| #ifdef CONFIG_VIDEO |
| #define CONFIG_VIDEO_MXS |
| #define CONFIG_VIDEO_LOGO |
| #define CONFIG_SPLASH_SCREEN |
| #define CONFIG_SPLASH_SCREEN_ALIGN |
| #define CONFIG_CMD_BMP |
| #define CONFIG_BMP_16BPP |
| #define CONFIG_VIDEO_BMP_RLE8 |
| #define CONFIG_VIDEO_BMP_LOGO |
| #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR |
| #endif |
| #endif |
| |
| #define CONFIG_ENV_OFFSET (8 * SZ_64K) |
| #define CONFIG_ENV_SIZE SZ_8K |
| #define CONFIG_ENV_IS_IN_MMC |
| |
| #define CONFIG_SYS_FSL_USDHC_NUM 3 |
| #if defined(CONFIG_ENV_IS_IN_MMC) |
| #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ |
| #endif |
| |
| #endif /* __CONFIG_H */ |