Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee b35b9bd1d4ee Merge tag 'v6.8-dts-raw' 1f50937554b4 Merge tag 'sound-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound 576ba37bcbf9 Merge tag 'net-6.8-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net c83dc02bae3e Merge tag 'qcom-arm64-fixes-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes fb254675a395 ASoC: dt-bindings: nvidia: Fix 'lge' vendor prefix c748b8a7dbe8 Merge tag 'tegra-for-6.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes a2e893adde74 Merge tag 'imx-fixes-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes abb0f1b369e4 Merge tag 'qcom-arm64-fixes-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes f143aa9a89ec Revert "arm64: dts: qcom: msm8996: Hook up MPM" 9a5690b7be49 arm64: dts: qcom: sc8280xp-x13s: limit pcie4 link speed ca6dcb63bd34 arm64: dts: qcom: sc8280xp-crd: limit pcie4 link speed 8532bb680bd0 dt-bindings: net: renesas,ethertsn: Document default for delays 42569705a4a0 Merge tag 'v6.8-rc6-dts-raw' 06c62487a0b4 arm64: dts: imx8mp: Fix LDB clocks property 7c93039778e4 arm64: dts: imx8mp: Fix TC9595 reset GPIO on DH i.MX8M Plus DHCOM SoM 7f9a36c5ce39 ARM: dts: imx7: remove DSI port endpoints 87ea8526eaf3 Merge tag 'loongarch-fixes-6.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson d4a4b892cd33 Merge tag 'arm-fixes-6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 4faf103c7468 Merge tag 'renesas-fixes-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes c1858748b935 Merge tag 'riscv-dt-fixes-for-v6.8-rc6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes f1bb487d660f LoongArch: dts: Minor whitespace cleanup b60485a78d66 Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux d641a222a5d4 arm64: tegra: Fix Tegra234 MGBE power-domains 31aeabc2669e ARM: dts: renesas: rcar-gen2: Add missing #interrupt-cells to DA9063 nodes 8c5d69d4f1e9 arm64: dts: qcom: Fix interrupt-map cell sizes 43b35c5b7347 arm: dts: Fix dtc interrupt_map warnings f00ce91341b9 arm64: dts: Fix dtc interrupt_provider warnings c21ad68d3254 arm: dts: Fix dtc interrupt_provider warnings 20a9f605f025 Merge tag 'v6.8-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes 1d9be1dcae7c Merge tag 'imx-fixes-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes c27426925b7b Merge tag 'v6.8-rc5-dts-raw' 582c3e28f603 Merge tag 'sound-6.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound 81da29f3007e arm64: tegra: Set the correct PHY mode for MGBE 30e4bc5d76ff Merge tag 'devicetree-fixes-for-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux f0c34a9f448e riscv: dts: sifive: add missing #interrupt-cells to pmic db36be2a8839 arm64: dts: rockchip: Correct Indiedroid Nova GPIO Names ec7d411e57d6 arm64: dts: rockchip: Drop interrupts property from rk3328 pwm-rockchip node 105b1e4e5e28 arm64: dts: rockchip: set num-cs property for spi on px30 a05f0ca9a008 arm64: dts: rockchip: minor rk3588 whitespace cleanup 41d6b3786aa9 riscv: dts: starfive: replace underscores in node names 910c8965eb0c dt-bindings: ufs: samsung,exynos-ufs: Add size constraints on "samsung,sysreg" d78e8a541b0a net: marvell,prestera: Fix example PCI bus addressing b40e56bea854 ASoC: dt-bindings: google,sc7280-herobrine: Drop bouncing @codeaurora 48b3246a26fe Revert "arm64: dts: imx8mn-var-som-symphony: Describe the USB-C connector" a1c414f8f89a Revert "arm64: dts: imx8mp-dhcom-pdk3: Describe the USB-C connector" 768ad06f1efa arm64: dts: tqma8mpql: fix audio codec iov-supply 77040f90f388 Merge tag 'v6.8-rc3-dts-raw' 65143ffc8608 arm64: dts: rockchip: drop unneeded status from rk3588-jaguar gpio-leds 39497955d1c0 ARM: dts: rockchip: Drop interrupts property from pwm-rockchip nodes 610e244453be arm64: dts: rockchip: Fix the num-lanes of pcie3x4 on Cool Pi CM5 EVB d6e600aea013 arm64: dts: rockchip: rename vcc5v0_usb30_host regulator for Cool Pi CM5 EVB 6be17990ec10 arm64: dts: rockchip: aliase sdmmc as mmc1 for Cool Pi CM5 EVB 77765eecb670 arm64: dts: rockchip: aliase sdmmc as mmc1 for Cool Pi 4B 7bca62b5ae66 arm64: dts: qcom: sm6115: Fix missing interconnect-names b2bc58ba4504 arm64: dts: imx8mp: Disable UART4 by default on Data Modul i.MX8M Plus eDM SBC 9474eb5c3d86 ALSA: Various fixes for Cirrus Logic CS35L56 support 1e8df48d4da1 dt-bindings: tpm: Drop type from "resets" 4d5c46ab184f dt-bindings: display: nxp,tda998x: Fix 'audio-ports' constraints fede8bd8306c dt-bindings: xilinx: replace Piyush Mehta maintainership eb691d1ece78 Merge tag 'v6.8-rc2-dts-raw' 5b093a56e797 ASoC: sun4i-spdif: Add Allwinner H616 compatible f2ce9dca7322 ASoC: sun4i-spdif: Fix requirements for H6 fd23c7505f20 arm64: dts: qcom: sm8650-mtp: add gpio74 as reserved gpio cfbd9243ac13 arm64: dts: qcom: sm8650-qrd: add gpio74 as reserved gpio 101ce3470b0e Merge tag 'drm-fixes-2024-01-27' of git://anongit.freedesktop.org/drm/drm 71ca3bf1c96e Merge tag 'arm-fixes-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 74c898882ebb riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format 28b77b56d972 arm64: dts: rockchip: mark system power controller on rk3588-evb1 986a9f1778ef Merge tag 'samsung-fixes-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/fixes 6cf0227916ec arm64: dts: Fix TPM schema violations 60245a9006e9 ARM: dts: Fix TPM schema violations 92924d8db61a Merge tag 'exynos-drm-fixes-for-v6.8-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes 3b240d0d94a9 dt-bindings: media: Remove K3 Family Prefix from Compatible 186b38b97035 ARM: dts: exynos4212-tab3: add samsung,invert-vclk flag to fimd c4f0c99dffb8 arm64: dts: exynos: gs101: comply with the new cmu_misc clock names 429796fee0f1 dt-bindings: clock: gs101: rename cmu_misc clock-names 80d76b25d32f Merge tag 'v6.8-rc1-dts-raw' 339d8d1caab5 Merge tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip df1980733ce9 Merge tag 'dmaengine-fix-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 8c23badf69c3 Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux d5a95e32a555 Merge tag 'loongarch-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson 815e38060bf4 Merge tag 'sound-fix-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound f07a1b362766 Merge tag 'for-v6.8-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply 9411a3099e9c Merge tag 'i2c-for-6.8-rc1-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux fcb7108dc362 Merge tag 'rtc-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux 8e06ce5908ff Merge tag 'input-for-v6.8-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input 7b18579c0bef Merge tag 'phy-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy dd4871a00012 Merge tag 'gpio-fixes-for-v6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux 8dfd2acd2c0c Merge tag 'backlight-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight 736ecd5cf03c Merge tag 'iommu-updates-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 7d29a06cb311 dt-bindings: i2c: document st,stm32mp25-i2c compatible 365a95704e98 dt-bindings: at24: add ROHM BR24G04 05d2a9834fd6 Merge tag 'usb-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 70a7bee43907 Merge tag 'tty-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 6a04bf7a4f07 Merge tag 'char-misc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc e0c35697cd80 Merge tag 'pci-v6.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci cf29a14b0a23 Merge tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 902219ef9ed0 Merge tag 'mailbox-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox c437f65015a8 Merge tag 'leds-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds d0902d05b4a0 Merge tag 'mfd-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd 8be1d4636d32 Merge tag 'rproc-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux 6eaaddf12639 Merge tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 2cb012b6fe68 LoongArch: dts: DeviceTree for Loongson-2K2000 6ab0a6f08b83 LoongArch: dts: DeviceTree for Loongson-2K1000 491426707de1 LoongArch: dts: DeviceTree for Loongson-2K0500 c007f27059d1 dt-bindings: interrupt-controller: loongson,liointc: Fix dtbs_check warning for interrupt-names d9a3ae336ecb dt-bindings: interrupt-controller: loongson,liointc: Fix dtbs_check warning for reg-names 4ee19a9d7583 dt-bindings: loongarch: Add Loongson SoC boards compatibles 3e99ee3f7c53 dt-bindings: loongarch: Add CPU bindings for LoongArch e8bc7c9c625e dt-bindings: don't anchor DT_SCHEMA_FILES to bindings directory f5918b47370e dt-bindings: rtc: max31335: add max31335 bindings 7e34d7b53615 rtc: rv8803: add wakeup-source support 81d186f05921 Merge branch 'pci/dt-bindings' 8bd798490681 Merge branch 'pci/controller/rcar' e166e5aad3b0 Merge branch 'pci/controller/cadence' 9de355a75fde dt-bindings: gpio: xilinx: Fix node address in gpio 28bf1e4e9775 dt-bindings: mailbox: qcom-ipcc: document the X1E80100 Inter-Processor Communication Controller f6b31bdd3c60 dt-bindings: mailbox: add Versal IPI bindings c3301d070937 dt-bindings: mailbox: zynqmp: extend required list 6bf977408719 dt-bindings: mailbox: qcom,apcs-kpss-global: use fallbacks b9ea63718a7e dt-bindings: mailbox: qcom,apcs-kpss-global: drop duplicated qcom,ipq8074-apcs-apps-global e485b251a3a4 Merge tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 60edd8755b1b Merge tag 'pwm/for-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm f946a0610062 Merge tag 'hid-for-linus-2024010801' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid 5a9222178c60 Merge tag 'media/v6.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media 0c57fa00ac11 Merge tag 'mmc-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 120152dd192c Merge tag 'pmdomain-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm f25acec1f182 Merge tag 'gnss-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss 040b6611cd72 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 432f2b929aa4 Merge tag 'gpio-updates-for-v6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux 5df1a59e6086 Merge tag 'linux-watchdog-6.8-rc1' of git://www.linux-watchdog.org/linux-watchdog 1d81fba29be6 Merge tag 'hwmon-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging dd7110d3d5d1 Merge tag 'sound-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound c916bd7a1d38 Merge tag 'drm-next-2024-01-10' of git://anongit.freedesktop.org/drm/drm 32704b03c7ec Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi c0d1d21fe5ff dt-bindings: fpga: altera: Convert bridge bindings to yaml 86986ec77fc7 dt-bindings: fpga: Convert bridge binding to yaml 149beabce38e dt-bindings: vendor-prefixes: Add smi da831df01407 Merge tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc d0949aef9e29 Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc c5ee04d9a430 Merge tag 'net-next-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next 17d4b2f2c7c6 dt-bindings: riscv: Document cbop-block-size 6361e08793d7 dt-bindings: riscv: permit numbers in "riscv,isa" 99f0fa81f51f dt-bindings: riscv: cpus: Clarify mmu-type interpretation 5744984c407c ARM: dts: usr8200: Fix phy registers fd6e692990ee dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" db07ea081cee dt-bindings: power: Clarify wording for wakeup-source property 9deb5d7e7649 Merge tag 'v6.8-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 f412e763e552 dt-bindings: mfd: sprd: Add support for UMS9620 b50b2489e1a2 dt-bindings: input: bindings for Adafruit Seesaw Gamepad 9fcf5401177c Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support" 6b479ffcb9ed dt-bindings: riscv: add Zacas ISA extension description 45e895d242d0 Merge remote-tracking branch 'palmer/fixes' into for-next 129abc9e5b89 Merge tag 'thermal-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 72e795875f31 Merge tag 'mtd/for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux a0d6ec02f5dd Merge tag 'spi-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 092d72f89f32 Merge tag 'regulator-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator f19bbcb501a1 Merge branch 'clk-rs9' into clk-next 6c5ff3361f38 Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-next 5348f28123c3 Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into clk-next dde8a0d89600 Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and 'clk-sophgo' into clk-next 147299598f64 dt-bindings: ignore paths outside kernel for DT_SCHEMA_FILES 5e8ad2415574 dt-bindings: tpm: Document Microsoft fTPM bindings 4446def763e6 dt-bindings: tpm: Convert IBM vTPM bindings to DT schema d46251bba773 dt-bindings: tpm: Convert Google Cr50 bindings to DT schema 4c0c46fcf77f dt-bindings: tpm: Consolidate TCG TIS bindings fc825b2e9d71 dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible 5d51cf126484 dt-bindings: arm: Add remote etm dt-binding 32c458bd3442 dt-bindings: mmc: sdhci-pxa: Fix 'regs' typo c9ab453dff7c media: dt-bindings: samsung,s5p-mfc: Fix iommu properties schemas 481554b6b752 dt-bindings: display: panel: Add synaptics r63353 panel controller e04e21bef16e dt-bindings: arm: merge qcom,idle-state with idle-state 452e35e6ff26 Merge tag 'irq-core-2024-01-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip d35742374b96 dt-bindings: display: samsung,exynos-mixer: Fix 'regs' typo ac8ffc6d0764 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux daf5be0b133e Merge tag 'powerpc-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux b633610fad05 Revert "net: stmmac: Enable Per DMA Channel interrupt" fc2b6856183b dt-bindings: rtc: qcom-pm8xxx: fix inconsistent example 5c111c61a49a dt-bindings: net: snps,dwmac: per channel irq 94d319464237 ASoC: dt-bindings: move tas2563 from tas2562.yaml to tas2781.yaml 8fbbcaccc3ff Merge tag 'socfpga_dts_updates_for_v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt 1161aaee27ae dt-bindings: mmc: add Marvell ac5 e9a747531a5d dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 74165b0 57b4e3b1199f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net cab393f5e80d dt-bindings: serial: Describe ARM dcc interface 1d92607a561e dt-bindings: usb: dwc3: Limit num-hc-interrupters definition cee9797861a0 dt-bindings: usb: xhci: Add num-hc-interrupters definition 4823f8dd230f arm64: dts: mediatek: mt8195: Add 'rx-fifo-depth' for cherry 4a4f48930e20 dt-bindings: usb: mtk-xhci: add a property for Gen1 isoc-in transfer issue 4ddd871b77e8 arm64: dts: qcom: msm8996: Remove PNoC clock from MSS 5598c7c58459 arm64: dts: qcom: msm8996: Remove AGGRE2 clock from SLPI a06133f3b90d arm64: dts: qcom: msm8998: Remove AGGRE2 clock from SLPI 0e31729b965a arm64: dts: qcom: msm8939: Drop RPM bus clocks a9231f1fa44d arm64: dts: qcom: sdm630: Drop RPM bus clocks 7806d0946f48 arm64: dts: qcom: qcs404: Drop RPM bus clocks 6bbd4a339ffd arm64: dts: qcom: msm8996: Drop RPM bus clocks 6c5785d4dec0 arm64: dts: qcom: msm8916: Drop RPM bus clocks d99558e0d6ba dt-bindings: usb: qcom,dwc3: Fix SDM660 clock description 0e7834fa9ba2 dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding f7405c1062e5 dt-bindings: connector: Add child nodes for multiple PD capabilities a2f2b957f7b0 arm64: dts: intel: minor whitespace cleanup around '=' a21ad91a14ac arm64: dts: socfpga: agilex: drop redundant status c64326a0161d arm64: dts: socfpga: agilex: add unit address to soc node 70eea150a8db arm64: dts: socfpga: agilex: move firmware out of soc node 056acfded5ce arm64: dts: socfpga: agilex: move FPGA region out of soc node 8e373ef160c7 arm64: dts: socfpga: agilex: align pin-controller name with bindings 56a65e118b36 arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties 5ea405da6608 arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings 0bc2b8deec9a arm64: dts: socfpga: stratix10: add unit address to soc node 3932c6fc63c2 arm64: dts: socfpga: stratix10: move firmware out of soc node 174dfac57ae2 arm64: dts: socfpga: stratix10: move FPGA region out of soc node e63c11b1c86c arm64: dts: socfpga: stratix10: align pincfg nodes with bindings 5ad3116fb135 arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB 9185b800f9c3 arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size b3832f4d101c ARM: dts: socfpga: align NAND controller name with bindings 7772fcc4eef4 ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size f466442c93ff dt-bindings: clock: mediatek: add clock controllers of MT7988 967ed08fdbd4 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs 8bb435f3ea7d dt-bindings: clock: mediatek: add MT7988 clock IDs 8b8c659b2121 dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC b822e804fd2c dt-bindings: gpio: add NPCM sgpio driver bindings f4c19e862d2b dt-bindings: gpio: realtek: Add realtek,rtd-gpio 6690161ed7a9 Merge branches 'apple/dart', 'arm/rockchip', 'arm/smmu', 'virtio', 'x86/vt-d', 'x86/amd' and 'core' into next 7382fa53a648 dt-bindings: net: renesas,etheravb: Document RZ/G3S support 247b8886892f dt-bindings: hwmon: (lm75) Add AMS AS6200 temperature sensor fec847c57a81 dt-bindings: Add MP2856/MP2857 voltage regulator device 42c42ff6c177 dt-bindings: hwmon: gpio-fan: Convert txt bindings to yaml 6c13c9d07051 dt-bindings: mmc: sdhci-msm: document dedicated IPQ4019 and IPQ8074 1e934476b96c dt-bindings: mmc: synopsys-dw-mshc: add iommus for Intel SocFPGA 82a434279c9e dt-bindings: HID: i2c-hid: elan: Introduce Ilitek ili2901 5fa4567d6c4f Merge tag 'v6.8-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt a04786e0b7e0 Merge tag 'v6.8-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 0bf9a2425459 Merge tag 'qcom-arm64-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt a3fde0732d5b Merge tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt 62073621d812 Merge tag 'arm-soc/for-6.8/devicetree' of https://github.com/Broadcom/stblinux into soc/dt 4cfe8fd4e2b4 Merge tag 'sprd-dt-6.8-rc1' of https://github.com/lyrazhang/linux into soc/dt a355b8e8cbdd dt-bindings: thermal: qcom-spmi-adc-tm5/hc: Clean up examples 36a030b546d0 dt-bindings: thermal: qcom-spmi-adc-tm5/hc: Fix example node names ca1c0a8c8091 dt-bindings: thermal: sun8i: Add binding for D1/T113s THS controller 7123707b90de dt-bindings: thermal-zones: Document critical-action c29ec9b83fd7 dt-bindings: thermal: qcom-tsens: document the SM8650 Temperature Sensor 5a12787401b5 dt-bindings: thermal: loongson,ls2k-thermal: Fix binding check issues 0a6d923c5231 dt-bindings: thermal: convert Mediatek Thermal to the json-schema dc5dd3862b77 dt-bindings: input: iqs269a: Add bindings for OTP variants 5aa00301cee3 dt-bindings: input: iqs269a: Add bindings for slider gestures c4635c803af3 Merge tag 'iio-for-6.8b' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next 571d91b8d8df arm64: dts: rockchip: Fix led pinctrl of lubancat 1 548cbdf62c21 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 86c28823371d arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b 275bc737b480 arm64: dts: rockchip: support poweroff on the rock-5b e4f7332bb7f8 arm64: dts: rockchip: Support poweroff on Orange Pi 5 d0c46aeba839 arm64: dts: rockchip: nanopc-t6 sdmmc beautification df73c00bc509 arm64: dts: sprd: Change UMS512 idle-state nodename to match bindings 12243eba2b74 arm64: dts: sprd: Add clock reference for pll2 on UMS512 af72bfcc73f3 arm64: dts: sprd: Removed unused clock references from etm nodes d8f5562e697b arm64: dts: sprd: Add support for Unisoc's UMS9620 bd8f67f82f65 dt-bindings: arm: Add compatible strings for Unisoc's UMS9620 9da3db96fae0 arm64: dts: sprd: fix the cpu node for UMS512 3ebc08960525 Merge tag 'v6.7-rc7' into gpio/for-next cb90fcbed71e dt-bindings: timer: Add StarFive JH8100 clint 6f2b19f4df72 dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs 4421b3e3124f dt-bindings: iio: Add AD7091R-8 51a0454cffd6 dt-bindings: power: supply: bq24190: Add BQ24296 compatible 4639caeeab2f dt-bindings: power: reset: xilinx: Rename node names in examples c873132667ed dt-bindings: power: reset: qcom-pon: fix inconsistent example 64cf7a912b11 arm64: dts: rockchip: Fix rk3588 USB power-domain clocks 815a2542ad42 arm64: dts: rockchip: configure eth pad driver strength for orangepi r1 plus lts 9df823a6207b arm64: dts: rockchip: Support poweroff on NanoPC-T6 78bd00069022 arm64: dts: rockchip: rk3308-rock-pi-s gpio-line-names cleanup 9d6e0741ae7c arm64: dts: rockchip: Add support for rk3588 based board Cool Pi CM5 EVB a64a2e009e21 dt-bindings: arm: rockchip: Add Cool Pi CM5 4397d62daec8 arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B f1a9c321e26f dt-bindings: arm: rockchip: Add Cool Pi 4B 1e413c69529f dt-bindings: vendor-prefixes: Add Cool Pi a67ded35095e arm64: dts: rockchip: add gpio-line-names to rk3328-rock-pi-e e0ec5767b690 ARM: dts: rockchip: Remove rockchip,default-sample-phase from rk3036.dtsi 75e0afe6681c ARM: dts: rockchip: Add stdout-path for rk3036 kylin 5b38dc06a1e9 dt-bindings: watchdog: qcom,pm8916-wdt: add parent spmi node to example d2f78877f2ea dt-bindings: watchdog: nxp,pnx4008-wdt: convert txt to yaml af1fdc5cd02d dt-bindings: watchdog: qca,ar7130-wdt: convert txt to yaml 5c3d9631b9ac dt-bindings: watchdog: intel,keembay: reference common watchdog schema 6d86f883fd9c dt-bindings: watchdog: re-order entries to match coding convention e28051167c06 dt-bindings: touchscreen: neonode,zforce: Use standard properties 3119a224ac1c dt-bindings: touchscreen: convert neonode,zforce to json-schema 15bf36928144 Merge tag 'icc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next dd37eb39a550 dt-bindings: input: convert drv266x to json-schema 795f4eddfec7 Merge tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt 991ab34b2120 Merge tag 'reset-for-v6.8' of git://git.pengutronix.de/pza/linux into soc/drivers 4e7b4659bc67 dt-bindings: mtd: partitions: u-boot: Fix typo 35dd951a7fd5 Merge tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers 69b18d58cc6d Merge tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers fc5aa9bf69fd Merge tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers 84c9739eb5b5 Merge tag 'qcom-drivers-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers 0ef14d7a1f46 dt-bindings: crypto: qcom-qce: document the SC7280 crypto engine 2fd8394e6d9f dt-bindings: crypto: qcom-qce: constrain clocks for SM8150-compatible QCE 40fd9d4f3234 dt-bindings: crypto: qcom-qce: constrain clocks for IPQ9574 QCE 30960ac02d6e dt-bindings: rng: starfive: Add jh8100 compatible string e6272a79f69c Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net dcd8ac1c5dd8 dt-bindings: spi: stm32: add st,stm32mp25-spi compatible 87166d1d3f3f Merge tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt 69abc2365d38 dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add X1E80100 USB PHY binding 822a13d2bf90 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document X1E80100 compatible 6722c7fe2a57 dt-bindings: phy: qcom: snps-eusb2: Document the X1E80100 compatible a38a399bccf1 dt-bindings: phy: mediatek: tphy: add a property for force-mode switch ca521e2ecf25 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: fix path to header aa156a9707ec Merge tag 'amlogic-arm64-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt e6127e00f352 Merge tag 'mvebu-dt64-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt aad08c0a0671 Merge tag 'mvebu-dt-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt e4320c558711 Merge tag 'samsung-dt64-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 077793e138f6 Merge tag 'qcom-arm32-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt 7ff5e1692425 Merge tag 'ti-k3-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt f009c98b2a3f dt-bindings: iio: dac: add MCP4821 e46c2c536959 Merge tag 'ti-keystone-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt edeab43af36b Merge tag 'zynqmp-dt-for-6.8' of https://github.com/Xilinx/linux-xlnx into soc/dt 4e78ad68f722 Merge tag 'imx-dt64-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt f4ece4b3d883 Merge tag 'imx-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt 1a2b6b1db701 Merge tag 'imx-bindgins-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt 71e20fbc3d5b Merge tag 'ux500-dts-soc-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt 056c9efa37c5 Merge tag 'renesas-dts-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt 339491d0999f Merge tag 'stm32-dt-for-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt 06086605676a dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in dts 640904451ab8 dt-bindings: dmaengine: Add Loongson LS2X APB DMA controller f88d59ec5d12 Merge tag 'sunxi-dt-for-6.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt e833ff47f9b9 Merge tag 'at91-dt-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt 9f821c027b01 Merge tag 'juno-update-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt 4bab8a451f49 Merge tag 'v6.8-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt a4789dd06449 Merge tag 'v6.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 5045526f0b7c Merge tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt a7603f8260b8 Merge tag 'samsung-dt-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 16a1d6e0b098 Merge tag 'samsung-dt64-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 0f1f66f39700 ARM: dts: ste: minor whitespace cleanup around '=' 22532c5d3f4a Merge tag 'omap-for-v6.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt 5288e13a2ad4 Merge tag 'hisi-arm64-dt-for-6.8' of https://github.com/hisilicon/linux-hisi into soc/dt f44f238cabce Merge tag 'w1-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next 61f41fa45eaf Merge tag 'iio-for-6.8a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next 07d575b06ff9 dt-bindings: pwm: ti,pwm-omap-dmtimer: Update binding for yaml fc02de1f5dc0 dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible 780449a81d3c dt-bindings: pwm: remove Xinlei's mail f96dd7edb887 arm64: dts: qcom: sc8180x: Fix up PCIe nodes b1ecf20e17e0 arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent eeed8f113289 dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp 2ef9211e8711 dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent 188c161805d3 dt-bindings: pinctrl: qcom: drop common properties 7834682c0d2c dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings c31ea3c9600f dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts 6cec6f6f090c dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts ef7b1c134921 dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts a3abecdd0e2e dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts 2b1d1c0dd621 dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts 36f8bb953634 dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts 670ced18d87f dt-bindings: pinctrl: qcom: create common LPASS LPI schema 5ca197c58799 dt-bindings: pinctrl: qcom: Add SM4450 pinctrl 8d27a131f7ad dt-bindings: pinctrl: qcom,pmic-mpp: clean up example 6674c2217ce1 Merge tag 'mediatek-drm-next-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next d7dde4a72dfa Merge tag 'drm-msm-next-2023-12-15' of https://gitlab.freedesktop.org/drm/msm into drm-next 64ddcb330a18 arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550 206ab99c38ce arm64: dts: qcom: sm8550: Update idle state time requirements 319f395fbc2a arm64: dts: qcom: sm8550: Separate out X3 idle state af2f75b56294 ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY 4a72661b117b arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK 5b72e989a37a arm64: dts: qcom: x1e80100: align mem timer size cells with bindings b17d7383c10f arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent 3840ead2163a ARM: dts: qcom: sdx55: fix USB SS wakeup 9e773fad2487 ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts d0728def7588 ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells' 0ee9dac79d46 ASoC: qcom: add sound card support for SM8650 345b970f1857 add es8326 dt-bindings, commonize headset codec 85a45459eeed GPIO inclusion fixes to misc sound drivers 616e88e1109d arm64: dts: qcom: sc8180x: fix USB SS wakeup f3d1b2acf659 arm64: dts: qcom: sdm670: fix USB SS wakeup 987f42804a25 arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts 2e58236aa851 ASoC: dt-bindings: qcom,lpass-va-macro: remove spurious contains in if statement bded77d8cc7b dt-bindings: regulator: qcom,usb-vbus-regulator: clean up example e1481a467961 powerpc/fsl: Fix fsl,tmu-calibration to match the schema 26e2fad496d4 arm64: dts: amlogic: fix format for s4 uart node 8a5115be3855 arm64: dts: amlogic: drop redundant status=okay 799049c22bf2 arm64: dts: amlogic: enable some nodes for board AQ222 3fea93dcdd73 arm64: dts: amlogic: add some device nodes for S4 44721ac7f4da Merge tag 'drm-misc-next-2023-12-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next d623bb97a280 Merge tag 'samsung-pinctrl-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel 81d84dd62616 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS WSA 4f673348bd77 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS VA d5b1bc404268 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS TX 40420db77069 ASoC: dt-bindings: qcom,lpass-rx-macro: Add X1E80100 LPASS RX 605001444f21 ASoC: dt-bindings: qcom,sm8250: Add X1E80100 sound card 4e179f2c3905 ASoC: dt-bindings: mt8188-mt6359: add es8326 support 0c819517fcb2 ASoC: dt-bindings: qcom,sm8250: document SM8650 sound card 0292b51ac8c4 ASoC: tegra: tegra20_ac97: Convert to use GPIO descriptors 4c6bc6503e5e Merge tag 'device_is_big_endian-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core into gpio/for-next 31d8096d43a1 dt-bindings: gpio: dwapb: allow gpio-ranges 873d4c02bbfa dt-bindings: clock: google,gs101: rename CMU_TOP gate defines bfc73914844a dt-bindings: clock: si5351: add PLL reset mode property af0493badd9d dt-bindings: clock: si5351: convert to yaml d1a5fb288be1 dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform ee353e29bfb4 dt-bindings: clk: rs9: Add 9FGV0841 48b20705829d dt-bindings: clock: brcm,kona-ccu: convert to YAML b2b282bb3ba9 dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema e35ce136c12f dt-bindings: clock: xilinx: add versal compatible 746818ace7a3 dt-bindings: rtc: Add Nuvoton ma35d1 rtc d8c717fd9bc8 dt-bindings: Remove alt_ref from versal e9caccbf099c arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting b616df631790 arm64: dts: qcom: sc8180x: Describe the GIC redistributor ae7e39a80f0f arm64: dts: qcom: sc8180x: Add interconnects to UFS 0f32e7aa54e0 arm64: dts: qcom: sc8180x: Add missing MDP clocks 3641f17d731d arm64: dts: qcom: sc8180x: Add UFS GDSC 2bbb23973697 arm64: dts: qcom: sc7280*: move MPSS and WPSS memory to dtsi a5b4605b6fc6 ARM: dts: qcom: msm8974*: Re-enable remoteprocs on various boards f1ecb44efc55 ARM: dts: qcom: msm8974: Remove bogus cd-gpio pinctrl 9dd85d38d004 ARM: dts: qcom: msm8974-klte: Remove unused property 34c2fdcebf94 arm64: dts: qcom: sc7280: Rename reserved-memory nodes 84a50703ca7d dt-bindings: remoteproc: qcom: sc7180-pas: Add SC7280 compatibles 47f83514132e dt-bindings: remoteproc: qcom: sc7180-pas: Fix SC7280 MPSS PD-names 1dce719ef64f arm64: dts: qcom: sc7280: Remove unused second MPSS reg afedac693f18 arm64: dts: qcom: sdm670: add display subsystem 1d8d2d147ea5 dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel 3ea56a52a7c2 dt-bindings: wdt: Add ts72xx 18522cdf3ec6 dt-bindings: watchdog: dlg,da9062-watchdog: Document DA9063 watchdog 688fe0bdd724 dt-bindings: watchdog: dlg,da9062-watchdog: Add fallback for DA9061 watchdog 9054003bb13e dt-bindings: watchdog: mediatek,mtk-wdt: add MT7988 watchdog and toprgu 63d466a6e3b3 dt-bindings: watchdog: realtek,rtd1295-watchdog: convert txt to yaml 5b6c41392896 dt-bindings: watchdog: qcom-wdt: Make the interrupt example edge triggered 4f8423c375eb dt-bindings: iio: chemical: add aosong,ags02ma 766801c2fc4b dt-bindings: vendor-prefixes: add aosong 530dcc2cff54 arm64: dts: qcom: sm8150-hdk: enable DisplayPort and USB-C altmode a63d7ac5c9ca arm64: dts: qcom: sm8150: add USB-C ports to the OTG USB host 6177bf5ba3b4 arm64: dts: qcom: sm8150: add USB-C ports to the USB+DP QMP PHY cccb449ab331 arm64: dts: qcom: sm8150: add DisplayPort controller 414013ad4921 arm64: dts: qcom: sm8150-hdk: fix SS USB regulators 94e5a8422a14 arm64: dts: qcom: sm8150-hdk: enable HDMI output 94cd2b0ff062 arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX d8577fce5e20 arm64: dts: qcom: sm8650: add fastrpc-compute-cb nodes e14f9c1044bd arm64: dts: qcom: sm8550-qrd: add PM8010 regulators 66e97e0962a7 arm64: dts: qcom: sm8550-mtp: Add pm8010 regulators 6437200479ec arm64: dts: qcom: qcm2290: Hook up MPM 75b87eb7e3ee arm64: dts: qcom: msm8996: Hook up MPM e043072a3a33 arm64: dts: qcom: sm6375: Hook up MPM 623a6180066f dt-bindings: arm: qcom: Add Motorola Moto G 4G (2013) 030e5c73208a arm64: dts: qcom: x1e80100-crd: Fix supplies for some LDOs in PM8550 58e87053c1f0 arm64: dts: qcom: sc7280: add QCrypto nodes 6d138c9b4127 arm64: dts: qcom: sc7180: Switch pompom to the generic edp-panel 9248e79cd654 arm64: dts: qcom: sm8150: fix USB SS wakeup 8143f0f67202 arm64: dts: qcom: sm8150: fix USB DP/DM HS PHY interrupts 1d46c82d351b arm64: dts: qcom: sdm845: fix USB SS wakeup 5c261eb8cd11 arm64: dts: qcom: sdm845: fix USB DP/DM HS PHY interrupts 2998fdbc15fe arm64: dts: qcom: sc8180x: fix USB DP/DM HS PHY interrupts 220ee261025f arm64: dts: qcom: sm8550: drop unneeded assigned-clocks from codec macros ef2823c0a498 arm64: dts: qcom: sm8550: move Soundwire pinctrl to its nodes 611112fa3972 arm64: dts: qcom: sm8450: drop unneeded assigned-clocks from codec macros 7fe6ee08b28c arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes eb6e95625c03 arm64: dts: qcom: sm8550: add missing two RX Soundwire ports in configuration 6f45533e32ad arm64: dts: qcom: sm8650: drop unneeded assigned-clocks from WSA macro 108c60eb7746 dt-bindings: arm: qcom: Fix up htc-memul compatible c493fe546f0a arm64: dts: qcom: sm6115: Hook up interconnects fd22f3a58a9e Merge branch 'icc-sm6115' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD 85a531800a07 ARM: dts: qcom: msm8926-motorola-peregrine: Add initial device tree 9c323b20cda8 ARM: dts: qcom: ipq4019: add dedicated SDHCI compatible 2fcaa70bfc3c arm64: dts: qcom: ipq8074: add dedicated SDHCI compatible 757c981838e3 arm64: dts: qcom: Fix coresight warnings in in-ports and out-ports 34e4f27862d1 arm64: dts: qcom: msm8998: Fix 'out-ports' is a required property 61e7df01e058 arm64: dts: qcom: msm8996: Fix 'in-ports' is a required property 786be94e8465 arm64: dts: qcom: qrb5165-rb5: add the Bluetooth node fe9d727180d2 arm64: dts: qcom: sa8775p: Add missing space between node name and braces 8df2548eb151 arm64: dts: qcom: Use "pcie" as the node name instead of "pci" 756ec289cf35 ARM: dts: qcom: Use "pcie" as the node name instead of "pci" 2066a55949a7 arm64: dts: qcom: acer-aspire1: Add sound 90485d1f88ce arm64: dts: qcom: acer-aspire1: Correct audio codec definition 3d97796b14f9 arm64: dts: qcom: acer-aspire1: Enable RTC 5d870a6a209b arm64: dts: qcom: sm8450: switch UFS QMP PHY to new style of bindings 1e57f262d57c arm64: dts: qcom: sm8350: switch UFS QMP PHY to new style of bindings 731a9974488a arm64: dts: qcom: sm8250: switch UFS QMP PHY to new style of bindings 8a512baad9fa arm64: dts: qcom: sm8150: switch UFS QMP PHY to new style of bindings 9c4063711b1f arm64: dts: qcom: sm6350: switch UFS QMP PHY to new style of bindings 79c130d88048 arm64: dts: qcom: sm6115: switch UFS QMP PHY to new style of bindings 65d88afa8518 arm64: dts: qcom: sdm845: switch UFS QMP PHY to new style of bindings fa34450ebcf9 arm64: dts: qcom: msm8998: switch UFS QMP PHY to new style of bindings 2d00768d0566 arm64: dts: qcom: msm8996: switch UFS QMP PHY to new style of bindings 6d501541ab8b arm64: dts: qcom: sm8450-hdk: Enable the A730 GPU 9999a06044c2 arm64: dts: qcom: sm8550-mtp: Enable the A740 GPU 1c8862cd1be0 arm64: dts: qcom: sm8550-qrd: Enable the A740 GPU db2dd74a4321 arm64: dts: qcom: sm8550: Add GPU nodes 41411e46e180 arm64: dts: qcom: sm8450: Add GPU nodes 67082abed4d1 arm64: dts: qcom: msm8939: Make blsp_dma controlled-remotely b0768548dacf arm64: dts: qcom: msm8916: Make blsp_dma controlled-remotely e529c8cd00c4 arm64: dts: qcom: msm8939: Add clock-frequency for broadcast timer dc95d696633b arm64: dts: qcom: Add missing vio-supply for AW2013 ce476167f046 arm64: dts: qcom: ipq6018: Add QUP5 SPI node 4723cf41be1a arm64: dts: qcom: ipq6018: Add remaining QUP UART node af3ecf0ef5eb Merge branch '20231201-videocc-8150-v3-1-56bec3a5e443@quicinc.com' into clk-for-6.8 eeb32e2a4dbd dt-bindings: clock: Update the videocc resets for sm8150 c591d3616c87 arm64: dts: qcom: qrb4210-rb2: Enable MPSS and Wi-Fi 479632ff42dd arm64: dts: freescale: fix the schema check errors for fsl,tmu-calibration 4c12613ce6e0 ARM: dts: imx27-phytec-phycore-som: Use 'rtc' as node name e55cb89e6ef8 ARM: dts: imx25: Remove unneeded keypad properties 610b835be6b9 dt-bindings: net: marvell,orion-mdio: Drop "reg" sizes schema 5605354f949e arm64: dts: freescale: imx8qxp: Disable dsp reserved memory by default bb83d09752aa arm64: dts: imx8qxp: Add VPU subsystem file 11f5b7454c94 arm64: dts: imx8qxp-mek: Move port under USB connector f6d6c203902d arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup 643674137f59 dt-bindings: PCI: qcom: Document the SM8650 PCIe Controller ddec040496f1 dt-bindings: PCI: dwc: rockchip: Document optional PCIe reference clock input 2d8a490fd767 dt-bindings: PCI: qcom: Correct reset-names property 2bdefbbe9381 dt-bindings: PCI: qcom: Correct clocks for SM8150 01ce80af6cc2 dt-bindings: PCI: qcom: Correct clocks for SC8180x 9c60f1faccc9 dt-bindings: PCI: qcom: Adjust iommu-map for different SoC c78e4dd9c7c0 arm64: dts: rockchip: make use gpio-keys for buttons on puma-haikou 146cf4124863 arm64: dts: rockchip: expose BIOS Disable feedback pin on rk3399-puma 26575df71b2d arm64: dts: rockchip: fix misleading comment in rk3399-puma-haikou.dts 93c2098cfa35 ARM: dts: ux500-href: Switch HREF520 to AB8505 488dc522177c ARM: dts: ux500-href: Push AB8500 config out 7acade644174 ARM: dts: ux500-href: Push AB8500 inclusion to the top 0043c908a991 dt-bindings: connector: usb: add accessory mode description 7b7f80d863a5 arm64: dts: rockchip: Add vop on rk3588 ef9ea9ea51ca arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode a843a4a028e7 arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode 83869275890f arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode 237d1d3aa847 arm64: dts: ti: k3-am6*: Add additional regs for DMA components 6540bf190683 arm64: dts: ti: k3-j7*: Add additional regs for DMA components f584859d0f96 arm64: dts: ti: k3-am65: Add additional regs for DMA components e76881a36a46 arm64: dts: cn913x: add device trees for COM Express boards a57b87e79272 dt-bindings: arm64: add Marvell COM Express boards 22b670935a1f arm64: dts: armada-3720-turris-mox: set irq type for RTC 6b8494ce5492 ARM64: dts: Add special compatibles for the Turris Mox 8fcbbd77bc4f ARM64: dts: marvell: Fix some common switch mistakes 61b4fbe68e70 ARM: dts: marvell: make dts use gpio-fan matrix instead of array 1a025bb583e1 ARM: dts: marvell: Fix some common switch mistakes 283f9ebb847c dt-bindings: serial: Add a new compatible string for UMS9620 42414ddb491a dt-bindings: serial: imx: Properly describe the i.MX1 interrupts a5b226724ae1 dt-bindings: usb: qcom,dwc3: Add X1E80100 binding a94c79572ac2 dt-bindings: usb: Document WCD939x USB SubSystem Altmode/Analog Audio Switch 6c2112d5f3f3 arm64: dts: qcom: qrb5165-rb5: use u16 for DP altmode svid 79493bc9fc10 dt-bindings: connector: usb: add altmodes description a98f9ad936ee dt-bindings: usb: nxp,ptn5110: Fix typos in the title da44f4e15545 dt-bindings: usb: genesys,gl850g: Document 'peer-hub' c32fd07e4010 dt-bindings: nvmem: add new stm32mp25 compatible for stm32-romem cc8835249ffb ARM: dts: stm32: add dcmipp support to stm32mp135 dc483bc0495b dt-bindings: gnss: u-blox: add "reset-gpios" binding 82239f64506f dt-bindings: iommu: rockchip: Add Rockchip RK3588 b10f7d79bc86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net e39b04bbed6e Merge branch 'icc-qcm2290' into icc-next c95f389c0366 Merge branch 'icc-sm6115' into icc-next b1f1b32e611b dt-bindings: PCI: rcar-pci-host: Add optional regulators 51eab76bc15c arm64: dts: allwinner: h618: add Transpeed 8K618-T TV box 8f65017d5eb4 dt-bindings: arm: sunxi: document Transpeed 8K618-T board name a043657dff28 dt-bindings: vendor-prefixes: add Transpeed b9b13eec182f arm64: dts: st: add bsec support to stm32mp25 4ba9da13226a ARM: dts: stm32: Consolidate usbh_[eo]hci phy properties on stm32mp15 3cd8f921b287 ARM: dts: stm32: don't mix SCMI and non-SCMI board compatibles 9d7cd7004fbc dt-bindings: arm: stm32: don't mix SCMI and non-SCMI board compatibles 3409584c8b1b ARM: dts: stm32: minor whitespace cleanup around '=' 46d3a566ba35 regulator: dt-bindings: qcom,rpmh: add compatible for pm8010 b876feae34ef ASoC: dt-bindings: audio-graph-port: Document new DAI link flags playback-only/capture-only b0c246496fbc dt-bindings: display: msm: dp: declare compatible string for sm8150 363bcab6054e scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string 3d1e051b5db8 arm64: dts: imx8mp-dhcom-pdk3: Describe the USB-C connector ef545aff5ca3 arm64: dts: imx8mn-var-som-symphony: Describe the USB-C connector 13069c168986 arm64: dts: imx8mp-tqma8mpql-mba8mpxl: Fix USB connector description c92840a54a7a arm64: dts: imx8mp-venice: Fix USB connector description d0235ca7db0f arm64: dts: imx8mp-verdin: Fix USB connector description 8e6a721ca452 arm64: dts: imx8dxl-ss-conn: Move clk_dummy out of USB node 7662ace2b978 arm64: dts: imx8mn-evk: Move port under USB connector 92576b82f349 arm64: dts: imx8mm-evk: Move port under USB connector 91c629656840 arm64: dts: freescale: introduce dimonoff-gateway-evk board 8b75c148251b dt-bindings: arm: fsl: add Dimonoff gateway EVK board 192ca710eafd dt-bindings: vendor-prefixes: add dimonoff edc62a2939e3 arm64: dts: imx8m*-tqma8m*: Add chassis-type d35e9fd630d7 arm64: dts: imx8mn-beacon: Support overdrive mode a684f6ef9a40 arm64: dts: imx8mn: Enable Overdrive mode 0c6ce8fb001d arm64: dts: imx8mm-beacon: Enable overdrive mode 42e3d3eaa3cb arm64: dts: imx8mm: Add optional overdrive DTSI f9b749293626 arm64: dts: imx8mm: Reduce GPU to nominal speed aadc35d489bd arm64: dts: imx93: Fix the micfil clock-names entries f8b732c140f6 ARM: dts: imx23/28: Fix the DMA controller node name 9697ec153a9c ARM: dts: imx23-sansa: Use preferred i2c-gpios properties 62875ee7373e ARM: dts: imx27-apf27dev: Fix LED name 6bd0d6d0fb3d ARM: dts: imx25/27: Pass timing0 3cd4341f361d ARM: dts: imx25: Fix the iim compatible string 52eef6a12e21 arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support b0f009ddef83 arm64: dts: exynos: google: Add initial Google gs101 SoC support 7932b36aab04 dt-bindings: arm: google: Add bindings for Google ARM platforms c439b1ecd46b dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings 5114ddf2754e dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes 5142777cc846 arm64: dts: renesas: white-hawk-cpu: Fix missing serial console pin control 9c5b72f0dbf7 arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces c20cd1060c83 arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board functionalities d1702886b9b1 arm64: dts: renesas: r9a08g045: Add Ethernet nodes c8bc29914258 arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node 2ac19b878bcd arm64: zynqmp: Add missing destination mailbox compatible bfda609d3986 arm64: zynqmp: Fix clock node name in kv260 cards bf79a715a44c arm64: zynqmp: Move fixed clock to / for kv260 067130bf35dd dt-bindings: soc: Add new board description for MicroBlaze V 3909199b5365 dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc 5a30f0c409d5 arm64: xilinx: Remove address/size-cells from gem nodes c7afa96873c9 arm64: xilinx: Remove address/size-cells from flash node e3a99f7f8d11 arm64: xilinx: Put ethernet phys to mdio node 6f4a9a0c8df9 arm64: xilinx: Remove mt25qu512a compatible string from SOM e3823e6a85e8 arm64: xilinx: Use lower case for partition address ee878ab978b7 arm64: xilinx: Do not use '_' in DT node names edb56e5ac871 riscv: dts: starfive: Enable SDIO wifi on JH7100 boards 738fd2fd6271 riscv: dts: starfive: Enable SD-card on JH7100 boards 4a3456d5f756 riscv: dts: starfive: Add JH7100 MMC nodes 0b98a998f256 riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards b7e59570a83e riscv: dts: starfive: Add JH7100 cache controller 0e3644417255 riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs 2ce3980ca0ba riscv: dts: starfive: Group tuples in interrupt properties 21bb4608c1f4 arm64: dts: ti: k3-am62-main: Add GPU device node 21dbc3bb6085 dt-bindings: interconnect: qcom,msm8998-bwmon: Add QCM2290 bwmon instance 0a5288800340 dt-bindings: rockchip,vop2: Add more endpoint definition 689213783aed dt-bindings: display: vop2: Add rk3588 support d06f02a431a5 dt-bindings: interconnect: qcom,msm8998-bwmon: Add SM6115 bwmon instance a67732e07f79 arm64: dts: fsd: Add MFC related DT enteries a8f325704092 arm64: dts: ti: k3-j721s2-evm: Add overlay for PCIE1 Endpoint Mode c33d48e723e9 arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE0 Endpoint Mode 411f344456e4 arm64: dts: ti: k3-j721e-sk: Add TPS6594 family PMICs e88109a7ea70 arm64: dts: ti: k3-am69-sk: Add support for TPS6594 PMIC 8203df16463f arm64: dts: ti: k3-j784s4-evm: Add support for TPS6594 PMIC 12693cd3a151 arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICs 022683d6bab2 arm64: dts: ti: k3-j721s2-som-p0: Add TP6594 family PMICs b13637076b0a arm64: dts: ti: k3-j7200-som-p0: Add TP6594 family PMICs 073920a8e469 spi: dw: Remove Intel Thunder Bay SOC support 853b38b4ccbe dt-bindings: media: s5p-mfc: Add mfcv12 variant af1444135df0 dt-bindings: soc: rockchip: add rk3588 vop/vo syscon ea9d3ade1f63 media: dt-bindings: Add OmniVision OV64A40 eac07152e0b8 media: dt-bindings: media: imx335: Add supply bindings 37535c00a2ec media: dt-bindings: gc0308: add binding 9be8a81b5d55 media: dt-bindings: ov8856: decouple lanes and link frequency from driver e78a33d58798 media: dt-bindings: alvium: add document YAML binding 123e53dddda5 dt-bindings: vendor-prefixes: Add prefix alliedvision 5367c47d39ee media: dt-bindings: ak7375: Add ak7345 support 33368f1c353f dt-bindings: mfd: pm8008: Clean up example node names 2ab5a6b315e7 dt-bindings: leds: qcom,spmi-flash-led: Fix example node name fa6a05463677 dt-bindings: leds: aw200xx: Fix led pattern and add reg constraints 44e89edff478 dt-bindings: leds: awinic,aw200xx: Add AW20108 device 6cd025d35790 dt-bindings: leds: aw200xx: Remove property "awinic,display-rows" 65b3a1cec5b9 dt-bindings: leds: aw200xx: Introduce optional enable-gpios property 48e46bb513fb dt-bindings: leds: Add Allwinner A100 LED controller 193b43eae00d dt-bindings: leds: Fix JSON pointer in max-brightness ac28e493721a ARM: dts: imx25: Move usbphy nodes out of simple-bus 90f8840e451d ARM: dts: imx1: Use 'bus' for AIPI bus dfc79426f635 ARM: dts: imx27-phytec-phycore-rdk: Move usbphy nodes out of simple-bus 92c19f27621f ARM: dts: imx27-pdk: Move usbphy0 out of simple-bus 09cddc0d2c3d ARM: dts: imx27: Use 'bus' for EMI bus e7cd1893e9ea ARM: dts: imx27: Use 'bus' for AIPI bus 81e952ba68c6 media: dt-bindings: media: i2c: Add bindings for TW9900 2ed7758d7c0a dt-bindings: vendor-prefixes: Add techwell vendor prefix 9b5febaeea2a arm64: dts: freescale: add fsl-lx2160a-mblx2160a board c763b70a3ecc dt-bindings: arm: fsl: Add TQ-Systems LX2160A based boards 6c6fc780325f ARM: dts: imx27-phytec-phycore-som: Use the mux- prefix 2571ab1025eb ARM: dts: imx1: Fix sram node c64c46277345 ARM: dts: imx27: Fix sram node 4606862f29a7 ARM: dts: imx: Use flash@0,0 pattern e9c196aff7af ARM: dts: imx25/27-eukrea: Fix RTC node name 34087a021485 ARM: dts: imx25-pdk: Pass #sound-dai-cells f91e9208f059 ARM: dts: imx25: Pass I2C clock-names property cb93e178f443 arm64: dts: freescale: imx93: add i3c1 and i3c2 3b2d451cf59f arm64: dts: ls1012a: Remove big-endian from thermal 25e47251c772 dt-bindings: input: microchip,cap11xx: add advanced sensitivity settings a0fb1bc7fd22 Merge tag 'exynos-drm-next-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next aae3e1a63026 dt-bindings: riscv: add Zfa ISA extension description ab9eea090f24 dt-bindings: riscv: add Zvfh[min] ISA extension description 7a64028da27c dt-bindings: riscv: add Zihintntl ISA extension description f4789213e5b6 dt-bindings: riscv: add Zfh[min] ISA extensions description c5de05064f79 dt-bindings: riscv: add vector crypto ISA extensions description 215c236fe6da dt-bindings: riscv: add scalar crypto ISA extensions description 1a96ef0c118a Merge tag 'pef2256-framer' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 6dbce6382acc Merge tag 'pef2256-framer' into devel 1c566bdd0e0f dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer 0e2e3f19a42d arm64: dts: rockchip: Add Anbernic RG351V aa1c981f085f arm64: dts: rockchip: Split RG351M from Odroid Go Advance 5985d0436d7f dt-bindings: arm: rockchip: Add Anbernic RG351V dddd8bf614e2 arm64: dts: rockchip: Add ethernet0 alias to the dts for RK3588(S) boards e79626358af1 arm64: dts: rockchip: Add ethernet0 alias to the dts for RK3566 boards c2bbb4cb37ce arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for PX30 5df2cd229ef2 arm64: dts: rockchip: Remove ethernetX aliases from the SoC dtsi for RK3328 773747ea9224 arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for RK3368 c47780f2190d arm64: dts: rockchip: Remove ethernet0 alias from the SoC dtsi for RK3399 0e5a28940713 arm64: dts: rockchip: make dts use gpio-fan matrix instead of array 51d3d03836a0 arm64: dts: rockchip: add gpio alias for gpio dt nodes 5fcf2d67aa35 arm64: dts: rockchip: Add dynamic-power-coefficient to rk3399 GPU 80e922961b8e arm64: dts: rockchip: add rk3588 spi aliases to soc dtsi 8f3fbd13ee16 arm64: dts: rockchip: add rk3588 gpio aliases to soc dtsi 15b3dffcbe21 arm64: dts: rockchip: add rk3588 i2c aliases to soc dtsi 095c6f3ed2af arm64: dts: rockchip: move rk3588 serial aliases to soc dtsi 5dc789289ead arm64: dts: rockchip: add Theobroma Jaguar SBC bc75d639d8bd dt-bindings: arm: rockchip: Add Theobroma-Systems Jaguar SBC 3c240c87c027 arm64: dts: rockchip: Add Powkiddy X55 2496d275584a dt-bindings: arm: rockchip: Add Powkiddy X55 517f4adf026d arm64: dts: rockchip: add USB3 host to rock-5a d474a82f6b8f arm64: dts: rockchip: add USB3 host to rock-5b 4bf4fdf576e0 arm64: dts: rockchip: add missing tx/rx-fifo-depth for rk3328 gmac 56e0ff652ec1 arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s 36bdcd2e79dd ARM: dts: rockchip: add hdmi-connector node to rk3036-kylin bd117185d559 ARM: dts: rockchip: fix rk3036 hdmi ports node 2127f8eafedb dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix fff73dbf51fc dt-bindings: soc: samsung: usi: add google,gs101-usi compatible 37ffa8542576 dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property fd8ed4626aeb dt-bindings: serial: samsung: Add google-gs101-uart compatible 33bfe5e1dc68 dt-bindings: watchdog: Document Google gs101 watchdog bindings e6381c01b68b riscv: dts: thead: Enable LicheePi 4A eMMC and microSD 3bd0505c030a riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD a53de85228bf riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock fd1214b13ed4 ARM: dts: microchip: sama5d27_som1_ek: Remove mmc-ddr-3_3v property from sdmmc0 node 5d2956b92dea dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle 402b4259739c dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S 150ddb24b2f0 Merge tag 'coresight-next-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next 64011b700499 dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU a5ab14d25e79 dt-bindings: arm-smmu: Add compatible for X1E80100 SoC aaa9819e17c5 dt-bindings: iommu: arm,smmu: document the SM8650 System MMU c04ccbbeb58a dt-bindings: iommu: arm,smmu: document clocks for the SM8350 GPU SMMU b73f681e020f arm64: dts: juno: Align thermal zone names with bindings 8762e182cc34 dt-bindings: hwmon: Add lltc ltc4286 driver bindings 7711cd743748 Merge tag 'exynos-drm-next-for-v6.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into exynos-drm-next 0c9c816dddb4 Backmerge tag 'v6.7-rc5' into drm-next cc330eac5dd3 dt-bindings: iio: humidity: Add TI HDC302x support 07a88600291a dt-bindings: iio: light: add ltr390 a803f8c65ec8 dt-bindings: iio: pressure: add honeywell,hsc030 49600f0eeb26 dt-bindings: iio: temperature: add MLX90635 device 5f69a9e8d3dd dt-bindings: hwmon: Increase max number of io-channels 565f404ae838 dt-bindings: hwmon: Add mps mp5990 driver bindings ad5cba1ee29a ASoC: dt-bindings: qcom,lpass-wsa-macro: Add SM8650 LPASS WSA 880126e66fb3 ASoC: dt-bindings: qcom,lpass-va-macro: Add SM8650 LPASS VA 19ed8a218bd9 ASoC: dt-bindings: qcom,lpass-tx-macro: Add SM8650 LPASS TX 322423704418 ASoC: dt-bindings: qcom,lpass-rx-macro: Add SM8650 LPASS RX f09397ff6cbf dt-bindings: dma: Add dma-channel-mask to nvidia,tegra210-adma 6263d2ffbb0f dt-bindings: dma: sf-pdma: add new compatible name 7581e8bd108d arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node de53c9a33f27 arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace 53ceb33cc2de arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs d305525393a4 arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes d4dbd2b56a9f arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0 209e23166717 arm64: dts: mt6358: Drop bogus "regulator-fixed" compatible properties b5aaf3dc3cc4 arm64: dts: mt8183: kukui-jacuzzi: Drop bogus anx7625 panel_flag property aef30bad7a04 arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile c8d764a0bbc6 dt-bindings: soc: mediatek: pwrap: Modify compatible for MT8188 1b35e3cf8066 dt-bindings: arm: mediatek: Add mt8188 pericfg compatible 7e4914880550 dt-bindings: arm: Add compatible for MediaTek MT8188 c4c85ca7297e arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes e7300ae6b913 dt-bindings: display: mediatek: dsi: add compatible for MediaTek MT8195 cebba0dd1a01 arm64: dts: mediatek: mt6358: Merge ldo_vcn33_* regulators 8ac8be12ac45 dt-bindings: arm: mediatek: convert audsys and mt2701-afe-pcm to yaml 275042f3fe7b arm64: dts: mediatek: mt8195: add MDP3 nodes aba1f17e7acc arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name 7032d5f144c2 arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes 22bae315e031 dt-bindings: display: mediatek: padding: add compatible for MT8195 751c1a1076cb dt-bindings: display: mediatek: split: add compatible for MT8195 e2f195c9941b dt-bindings: display: mediatek: ovl: add compatible for MT8195 98aa994aefee dt-bindings: display: mediatek: merge: add compatible for MT8195 6f5d6cbaa3f9 dt-bindings: display: mediatek: color: add compatible for MT8195 ef86984ae659 dt-bindings: display: mediatek: aal: add compatible for MT8195 8f6efe19695a dt-bindings: media: mediatek: mdp3: add component TDSHP for MT8195 f3a2d9b01651 dt-bindings: media: mediatek: mdp3: add component TCC for MT8195 9952a02bb5ee dt-bindings: media: mediatek: mdp3: add component STITCH for MT8195 6c49acbc4134 dt-bindings: media: mediatek: mdp3: add component HDR for MT8195 d6fdbfb3b4ad dt-bindings: media: mediatek: mdp3: add component FG for MT8195 a7d6e829425b dt-bindings: media: mediatek: mdp3: add compatible for MT8195 WROT 7db0370c2d66 dt-bindings: media: mediatek: mdp3: add compatible for MT8195 RSZ 5620ceb8b6ca dt-bindings: media: mediatek: mdp3: add config for MT8195 RDMA 8f056e0ef45c dt-bindings: media: mediatek: mdp3: merge the indentical RDMA under display c2d8940ef6fd dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with generic names 4347ab16a815 media: dt-bindings: mediatek: Add phandle to mediatek,scp on MDP3 RDMA e14664bd10f6 arm64: dts: mediatek: mt8195-cherry: Assign sram supply to MFG1 pd 0561502a0693 arm64: dts: mediatek: mt8195-cherry: Add MFG0 domain supply 08b52bb4b076 dt-bindings: reset: mt8188: Add VDOSYS reset control bits 10fbcb9df4e2 dt-bindings: arm: mediatek: Add compatible for MT8188 88c996595db3 dt-bindings: display: mediatek: padding: Add MT8188 ca5643fef42b dt-bindings: display: mediatek: merge: Add compatible for MT8188 ae3b78a94c61 dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188 744464b66c7e dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 01b1569a2d88 dt-bindings: thermal: convert Mediatek Thermal to the json-schema 90d08ec14e3c arm64: dts: mt8183: Add jacuzzi pico/pico6 board 5df3f176b5bf dt-bindings: arm64: mediatek: Add mt8183-kukui-jacuzzi-pico 281ab3bf124c arm64: dts: mt8183: Add jacuzzi makomo board 52cfc0fd5dd9 dt-bindings: arm64: mediatek: Add mt8183-kukui-jacuzzi-makomo 19dd875d8e0a arm64: dts: mt8183: Add kukui katsu board b8dd2f8c3e1c dt-bindings: arm64: mediatek: Add mt8183-kukui-katsu 9a6a916f0bc6 arm64: dts: mediatek: Move MT6358 PMIC interrupts to MT8183 boards 3f27ea46dc3d arm64: dts: mediatek: Use interrupts-extended where possible ad0c69fd2fa3 arm64: dts: mediatek: mt8173: Use interrupts-extended where possible c82e8139aeaa arm64: dts: mediatek: mt8183: Use interrupts-extended where possible d8a485fe96f7 dt-bindings: soc: mediatek: add mt8186 and mt8195 svs dt-bindings e66d619c0c3a dt-bindings: arm: mediatek: mmsys: Add VPPSYS compatible for MT8188 5e6b938fc74f arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones e90ef555e054 arm64: dts: mediatek: mt8183: Add decoder 0f0ccec6cc8d arm64: dts: mediatek: mt8173: Drop VDEC_SYS reg from decoder b6aed11d9548 arm64: dts: mediatek: cherry: Add platform thermal configuration 86760b83d52b dt-bindings: display: simple: Add AUO G156HAN04.0 LVDS display a9ddc30ef584 dt-bindings: display: panel: Add Ilitek ili9805 panel controller defac25462fb dt-bindings: display: st7701: Add Anbernic RG-ARC panel 336bc0e68db2 dt-bindings: display: panel: add Fascontek FS035VG158 panel 955ce81826fb dt-bindings: vendor-prefixes: Add fascontek 752a79b7aaef dt-bindings: display: panel: Clean up leadtek,ltk035c5444t properties 770aea203c16 Merge 6.7-rc5 into tty-next 34ef5edc5b88 Merge 6.7-rc5 into usb-next 621073890e71 Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64 bf94b2d5359e arm64: dts: exynos: add minimal support for exynosautov920 sadk board e9fd8cf1d2d8 arm64: dts: exynos: add initial support for exynosautov920 SoC d0863d30608a dt-bindings: pinctrl: samsung: correct ExynosAutov920 wake-up compatibles 9bdf0db8ae4b dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum 5b54324e6d5b dt-bindings: dma: Drop undocumented examples e2fd1a08fd82 Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-next a04c2351b389 dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 9b3c118b3d19 dt-bindings: clock: Add Google gs101 clock management unit bindings d97b5e938286 dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible 6a5a439c0701 dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible 10422d721886 dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible 3a5cb767f670 media: dt-bindings: media: rkisp1: Fix the port description for the parallel interface 1da803cb7af8 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable WiFi 8da528961e4e arm64: dts: qcom: qcm6490-fairphone-fp5: Enable various remoteprocs e6fa65e6d152 arm64: dts: qcom: sc7280: Add CDSP node fc9753f721c5 arm64: dts: qcom: sc7280: Add ADSP node c8ee1d58df76 arm64: dts: qcom: sc7280: Use WPSS PAS instead of PIL 52f7c413fda4 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable UFS 4df3a7b5d504 arm64: dts: qcom: msm8953: Set initial address for memory 423afe7e3dcb ARM: dts: qcom: msm8226: Add GPU bba409f9c339 ARM: dts: qcom: Disable pm8941 & pm8226 smbb charger by default 7e9db953a623 arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 IDP board 4e3613f89c7f arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc d8bfc2581200 dt-bindings: input: gpio-mouse: Convert to json-schema 2691fb7a0b13 dt-bindings: drm: rockchip: convert inno_hdmi-rockchip.txt to yaml 2dc455b73efa ARM: dts: samsung: exynos4210-i9100: Add accelerometer node 0fab2792a476 ARM: dts: samsung: exynos4210-i9100: Add node for touch keys 7ea4a30a8fd6 ARM: dts: samsung: exynos4210-i9100: Unconditionally enable LDO12 4cee9945012b ARM: dts: microchip: sama5d27_wlsom1_ek: Remove mmc-ddr-3_3v property from sdmmc0 node e76f84dfaedb arm64: dts: qcom: sm8650: Add DisplayPort device nodes 2cfe9148e611 arm64: dts: qcom: pm8550: drop PWM address/size cells 49e3d2a63a49 dt-bindings: display: mediatek: padding: Add MT8188 8c1a5538e89b dt-bindings: display: mediatek: merge: Add compatible for MT8188 29025812d6c3 dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries 3e60d5b58b7d dt-bindings: gpu: samsung-scaler: constrain iommus and power-domains 1d6aee346b02 dt-bindings: gpu: samsung-g2d: constrain iommus and power-domains d4a84a84e922 dt-bindings: gpu: samsung: constrain clocks in top-level properties 1e0b14dc8237 dt-bindings: gpu: samsung: re-order entries to match coding convention ba50ff463c59 dt-bindings: gpu: samsung-rotator: drop redundant quotes 1a3c1bf5b141 dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188 0a16c7e2c414 dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 925f69a6cc7d dt-bindings: serial: qcom,msm-uartdm: Vote for shared resources 44f4478aa927 dt-bindings: serial: snps-dw-apb-uart: include rs485 schema fad4b52a0fdb arm64: dts: hisilicon: hikey970-pmic: clean up SPMI node 051c12eb5d46 arm64: dts: hisilicon: hikey970-pmic: fix regulator cells properties e567127bd619 dt-bindings: hisilicon: Merge hi3620-clock into hisilicon,sysctrl binding 4b823f7042ef arm64: dts: qcom: x1e80100: Add Compute Reference Device f51679f0f817 arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts ca121fc146b2 dt-bindings: arm: qcom: Document X1E80100 SoC and boards c53c3b8c12a4 dt-bindings: arm: cpus: Add qcom,oryon compatible aa432318faa9 Merge branch 'icc-x1e80100' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 9eba2f2fb214 Merge branch '20231205061002.30759-4-quic_sibis@quicinc.com' into arm64-for-6.8 f213e67c84b7 Merge branch '20231205061002.30759-4-quic_sibis@quicinc.com' into clk-for-6.8 ecc521e21905 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 079af735ef3c dt-bindings: clock: qcom: Add X1E80100 GCC clocks 8f4495322f78 arm64: dts: qcom: sm8650-mtp: add WSA8845 speakers 02b73ff63440 arm64: dts: qcom: sm8650: add Soundwire controllers e6679602ac09 arm64: dts: qcom: sm8650: add ADSP audio codec macros 5c0a5d9640c3 arm64: dts: qcom: sm8650: add LPASS LPI pin controller 7f6211cc8e63 arm64: dts: qcom: sm8650: add ADSP GPR b72a9e98977b arm64: dts: qcom: sm8650-qrd: enable IPA 13bdc41575ab arm64: dts: qcom: sm8650: add IPA information 0fd767d395a1 arm64: dts: qcom: sm8650-qrd: add interconnect dependent device nodes d68c8f7f237a arm64: dts: qcom: sm8650-mtp: add interconnect dependent device nodes 900a28b939d2 arm64: dts: qcom: sm8650: add interconnect dependent device nodes ff01973261d0 arm64: dts: qcom: sm8650: add initial SM8650 QRD dts 185ce15a620b arm64: dts: qcom: sm8650: add initial SM8650 MTP dts 487b5dde17e2 arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable 61ff00c8e1de arm64: dts: qcom: add initial SM8650 dtsi 7266e49a2f3e dt-bindings: arm: qcom: document SM8650 and the reference boards 34a104c65fa9 Merge branch 'icc-sm8650' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 dc9c79dc36cc Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into arm64-for-6.8 482bf7559678 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 89cdcbe73e3a dt-bindings: display: msm: dp-controller: document SM8650 compatible 6457d6362b66 docs: dt-bindings: add DTS Coding Style document 17bd76b0dcba ARM: dts: rockchip: add gpio alias for gpio dt nodes 1e3bf6cdb555 dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Clean up example ebf62e0e08ff dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Fix regulator binding ff778a37f71a dt-bindings: mfd: hisilicon,hi6421-spmi-pmic: Fix up binding reference 60bfc8c9aef9 dt-bindings: firmware: qcom,scm: Allow interconnect for everyone ae3daad140cd arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree 3ab4a6461f9d dt-bindings: arm: qcom: Add Xiaomi Pad 6 (xiaomi-pipa) a4229e4b1bf7 arm64: dts: qcom: sm8550-qrd: enable IPA 0b02bd1a7f8b arm64: dts: qcom: sm8550: add IPA information 1d704f347212 dt-bindings: firmware: qcom,scm: document SCM on X1E80100 SoCs a07e2c07074c dt-bindings: arm: qcom-soc: extend pattern matching for X1E80100 SoC 190053cb1ce8 arm64: dts: qcom: minor whitespace cleanup around '=' e5d9eb69d255 ARM: dts: qcom: minor whitespace cleanup around '=' a12829c0d5ea arm64: dts: qcom: ipq8074: Add QUP4 SPI node 81c5f29af493 arm64: dts: qcom: qdu1000: Add ECPRI clock controller 7f8d2a160503 Merge branch '20231123064735.2979802-2-quic_imrashai@quicinc.com' into clk-for-6.8 a7b1e49f140b dt-bindings: clock: qcom: Add ECPRICC clocks for QDU1000 and QRU1000 0d8365b85a68 ARM: dts: qcom: sdx55: fix USB wakeup interrupt types 4e5dc5d2a1e5 arm64: dts: qcom: sm8550: fix USB wakeup interrupt types b0dd9226dd63 arm64: dts: qcom: sm8150: fix USB wakeup interrupt types 301d240b276b arm64: dts: qcom: sm6375: fix USB wakeup interrupt types bcfa8e3ed274 arm64: dts: qcom: sdm845: fix USB wakeup interrupt types 20a6fe5d28b2 arm64: dts: qcom: sdm670: fix USB wakeup interrupt types d2c7cfd6cfc3 arm64: dts: qcom: sc8180x: fix USB wakeup interrupt types 6f29d799b7cf arm64: dts: qcom: sc7280: fix usb_2 wakeup interrupt types ca84d4480b44 arm64: dts: qcom: sc7280: fix usb_1 wakeup interrupt types 096085135fda arm64: dts: qcom: sc7180: fix USB wakeup interrupt types 6c1f003cc9a1 arm64: dts: qcom: sa8775p: fix USB wakeup interrupt types 45bd09d633c8 arm64: dts: qcom: msm8916-longcheer-l8150: Add battery and charger 195857e6f299 arm64: dts: qcom: pm8916: Add BMS and charger 6caacf1f1bd3 arm64: dts: qcom: sc7280: Add 0xac Adreno speed bin 3ddcb3a31e24 arm64: dts: qcom: sc7280: Mark Adreno SMMU as DMA coherent b8bf84b9efc0 arm64: dts: qcom: sc7280: Fix up GPU SIDs 0830942e59a4 arm64: dts: qcom: sc7280: Add ZAP shader support 6a2b85d201c9 dt-bindings: arm: qcom-soc: extend pattern for matching existing SoCs ddd782c9e1e9 dt-bindings: cache: qcom,llcc: Add X1E80100 compatible 573141bcc2f7 arm64: dts: qcom: sdx75-idp: Enable USB3 and PHY support 93789523f679 arm64: dts: qcom: Add USB3 and PHY support on SDX75 ddc8552a97e0 arm64: dts: qcom: Add interconnect nodes for SDX75 2f6480d75792 arm64: dts: qcom: sm8350: Fix remoteproc interrupt type 22ab1e4b96e5 arm64: dts: qcom: pm8350k: Remove hanging whitespace 648dd7cb906d arm64: dts: qcom: sm8350: Fix DMA0 address aa5e755d7246 dt-bindings: iio: adc: qcom: Add Qualcomm smb139x aee24a669374 arm64: dts: qcom: sc8180x: align APSS with bindings c51b52a3c7aa arm64: dts: qcom: sm6375-pdx225: add fixed touchscreen AVDD regulator 714c2d01cb79 arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller 869ed2bf0b06 arm64: dts: qcom: sm6115: align mem timer size cells with bindings 5b01a3bc4e38 arm64: dts: qcom: sm8150: use 'gpios' suffix for PCI GPIOs abcbd3630645 arm64: dts: qcom: sc8180x-primus: use 'gpios' suffix for PCI GPIOs 5281b1e2c756 arm64: dts: qcom: sc8180x-flex-5g: use 'gpios' suffix for PCI GPIOs dbf927ecfde3 arm64: dts: qcom: sdm845: correct Soundwire node name 27d49e38f5d4 arm64: dts: qcom: sdm845-db845c: correct LED panic indicator 85591f38ba27 arm64: dts: qcom: qrb5165-rb5: correct LED panic indicator 65b61add6d70 arm64: dts: qcom: sm8250: Add wakeup-source to usb_1 and usb_2 343c9084fd53 arm64: dts: qcom: sdm850-lenovo-yoga: Add wakeup-sources eb9d72ac20a4 arm64: dts: qcom: sa8775p-ride: enable pmm8654au_0_pon_resin e4828a6315b4 arm64: dts: qcom: sm8350: move DPU opp-table to its node cfa2fb4b7f5b arm64: dts: qcom: sc8280xp-x13s: drop sound-dai-cells from eDisplayPort 927e9926b48f arm64: dts: qcom: sc8180x-primus: drop sound-dai-cells from eDisplayPort ca8a02834a8f arm64: dts: qcom: sm8250: correct Soundwire node name 682a341c0cdc arm64: dts: qcom: sc8280xp: correct Soundwire node name 13f2dbc0a9cb arm64: dts: qcom: qdu1000-idp: drop unused LLCC multi-ch-bit-off 6cda67d14000 arm64: dts: qcom: qdu1000: correct LLCC reg entries 208a56e344a2 arm64: dts: qcom: sm8450: fix soundwire controllers node name c7bee631d3e9 arm64: dts: qcom: sm8550: fix soundwire controllers node name 255ca7c95406 Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into clk-for-6.8 52721c372031 dt-bindings: clock: qcom: Document the SM8650 RPMH Clock Controller a8430c36d8bc dt-bindings: clock: qcom: document the SM8650 GPU Clock Controller e39f08bf115a dt-bindings: clock: qcom: document the SM8650 Display Clock Controller 076aa9fc05f3 dt-bindings: clock: qcom: document the SM8650 General Clock Controller abeff2c9f476 dt-bindings: clock: qcom: document the SM8650 TCSR Clock Controller 3714369ceebb dt-bindings: cache: qcom,llcc: Document the SM8650 Last Level Cache Controller cb0f1e272d52 dt-bindings: clock: qcom,gcc-msm8939: Add CSI2 related clocks 7ee4127b7a3f arm64: dts: qcom: sc8280xp: Add in CAMCC for sc8280xp d380ef670205 Merge branch '20231026105345.3376-3-bryan.odonoghue@linaro.org' into arm64-for-6.8 30a292de3f9a Merge branch '20231026105345.3376-3-bryan.odonoghue@linaro.org' into clk-for-6.8 f007e023cbd5 dt-bindings: clock: Add SC8280XP CAMCC aec8967c6dce dt-bindings: clock: Use gcc.yaml for common clock properties 7c1eb93bd0d3 dt-bindings: clock: qcom,gcc-ipq6018: split to separate schema b6364ec8f82d dt-bindings: arm: qcom,ids: Add SoC ID for SM8650 3f482ad7991e arm64: dts: qcom: sm8550: Enable download mode register write fe077e894545 arm64: dts: qcom: sm8350: Add TCSR halt register space 956699ec82d4 arm64: dts: qcom: sm8250: Add TCSR halt register space e0bd046de230 arm64: dts: qcom: ipq5018: add few more reserved memory regions c38c43d3b995 arm64: dts: qcom: ipq5332: add missing properties to the GPIO LED node 0390c1ee5e11 arm64: dts: qcom: ipq9574: enable GPIO based LED 2f9b91c0cf6d arm64: dts: qcom: qrb2210-rb1: use USB host mode 2196010939c0 dt-bindings: firmware: qcom,scm: document SM8650 SCM Firmware Interface ae8a176c474a dt-bindings: soc: qcom: pmic-glink: document SM8650 compatible c3cb68af1e5d dt-bindings: soc: qcom,aoss-qmp: document the SM8560 Always-On Subsystem side channel a6ea4114f911 dt-bindings: mmc: mtk-sd: add tuning steps related property 30e4bc60ac6d dt-bindings: mfd: ti,am3359-tscadc: Allow dmas property to be optional 5c51588d48df dt-bindings: mfd: qcom,spmi-pmic: Add pm8916 vm-bms and lbc a03962f53dbd dt-bindings: mfd: qcom-spmi-pmic: Document PM8937 PMIC 81a2c830f173 dt-bindings: mfd: qcom,tcsr: Add compatible for sm8250/sm8350 fe50e0fb05fc dt-bindings: mfd: ams,as3711: Convert to json-schema 197c27b6cfaa arm64: dts: fsd: add specific compatibles for Tesla FSD 395fa67b6b72 Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64 5927c83d20c8 dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD 78e4ed4670d7 dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD c168df69f5a1 dt-bindings: serial: samsung: add specific compatible for Tesla FSD 6dedf66f0e8b dt-bindings: pwm: samsung: add specific compatible for Tesla FSD 457e5d03f14d dt-bindings: i2c: exynos5: add specific compatible for Tesla FSD 4b7a14529669 dt-bindings: mmc: renesas,sdhi: Document RZ/Five SoC a135e0045af7 dt-bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms d0ed6c92c98e dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support f7a9df14027b dt-bindings: net: microchip,ksz: document microchip,rmii-clk-internal b81aa4a5992d media: dt-bindings: mediatek: Add phandle to mediatek,scp on MDP3 RDMA b80f939c4051 dt-bindings: iio/adc: qcom,spmi-vadc: clean up examples 44c4f2c40551 dt-bindings: iio/adc: qcom,spmi-vadc: fix example node names c57fab0a68f9 dt-bindings: iio/adc: qcom,spmi-rradc: clean up example f330b6a06a10 dt-bindings: iio/adc: qcom,spmi-iadc: clean up example d089bb38e3f6 dt-bindings: iio/adc: qcom,spmi-iadc: fix example node name d92310a0b805 dt-bindings: iio/adc: qcom,spmi-iadc: fix reg description 6afb70912c0a Merge tag 'renesas-dts-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt 77be7b2ec3d6 arm64: dts: ti: Add verdin am62 mallow board 5fe3785a98a1 dt-bindings: arm: ti: Add verdin am62 mallow board 7bf01a4e3239 ASoC: dt-bindings: fsl,xcvr: Adjust the number of interrupts 568ee5fdf77d dt-bindings: interconnect: Add Qualcomm SM6115 NoC 7549b7adec53 arm64: dts: ti: verdin-am62: Improve spi1 chip-select pinctrl 0b160138fdcc arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Remove HDMI Reset Line Name 42aed107725d arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add HDMI support 766ac2241c85 arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Lower I2C1 frequency bcf7dd5b8b09 arm64: dts: ti: phycore-am64: Add R5F DMA Region and Mailboxes e1dfb1eb87a4 riscv: dts: microchip: add the mpfs' system controller qspi & associated flash 59d2f723c14b dt-bindings: soc: microchip: add a property for system controller flash 4b452a4cfa9e ARM: dts: imx23/28: Remove undocumented "fsl,clkctrl" 485e1601cd25 ARM: dts: bcm2711: Add BCM2711 xHCI support 439353e944b0 dt-bindings: usb: xhci: Add support for BCM2711 4b95e8b40522 ARM: dts: imx28-lwe: Pass device_type to the memory node ea0431aa1757 ARM: dts: imx23/28: Remove unneeded "fsl,mxs-gpio" e63738dd96c8 ARM: dts: imx28-tx28: Pass #sound-dai-cells fc88878c01c0 arm64: dts: imx8mq-phanbell: make dts use gpio-fan matrix instead of array e21fe3809cd3 arm64: dts: freescale: verdin-imx8mp: add support to mallow board a75cfdc4a966 arm64: dts: freescale: verdin-imx8mm: add support to mallow board 3b7bee60295f arm64: dts: imx8mm-venice-gw7: Adjust PCI Ethernet nodes 5241ecb06203 dt-bindings: arm: fsl: add verdin imx8mp mallow board b80ecc880136 dt-bindings: arm: fsl: add verdin imx8mm mallow board ad1ae2498610 arm64: dts: imx8mm: Slow default video_pll1 clock rate 5aa830cec5a3 arm64: dts: imx8mm: Remove video_pll1 clock rate from clk node 110274d03548 arm64: dts: imx8mm: Simplify mipi_dsi clocks 99d898689e0b ARM: dts: imx7s: Add on-chip memory 29d17af3b09b ARM: dts: imx7: add MIPI-DSI support d9c25edf04ae scsi: ufs: dt-bindings: Add msi-parent for UFS MCQ dba1025f17d0 ARM: dts: nxp: Fix some common switch mistakes 4ea7b578957d arm64: dts: freescale: minor whitespace cleanup around '=' dbb52d93894b arm64: dts: imx8dxl-ss-ddr: change ddr_pmu0 compatible 941d70d2ae55 arm64: dts: tqma8mpql: Remove invalid/unused property ec00a410133c arm64: dts: imx8-ss-audio: Remove unexistent'shared-interrupt' 604139ed79f6 arm64: dts: imx93: Remove unexistent 'shared-interrupt' 7a445842e287 arm64: dts: imx8qxp-mek: Fix gpio-sbu-mux compatible 0c2122b767be arm64: dts: imx8mp-debix-model-a: Use phy-mode 2e9827c5e054 arm64: dts: imx8mm-nitrogen-r2: Fix I2C mux subnode name d1e22a0dfb43 arm64: dts: imx8dxl-ss-conn: Fix Ethernet interrupt-names order 6299d7ae35e5 arm64: dts: imx8mm-emcon-avari: Fix gpio-cells 9de3f32f3c7d arm64: dts: imx8qm-ss-dma: Pass lpuart dma-names 6905c613057b arm64: dts: freescale: Add SKOV IMX8MP CPU revB board b20a05f3b464 arm64: dts: imx8mn-var-som-symphony: add vcc supply for PCA9534 a5a6af3c0bdd arm64: dts: freescale: introduce rve-gateway board 83600000758e arm64: dts: freescale: debix-som-a-bmb-08: Add CSI Power Regulators b5e632bcd082 arm64: dts: imx8-apalis: add can power-up delay on ixora board 9804057f0f96 arm64: dts: imx8mn-var-som: add fixed 3.3V regulator for EEPROM e3c93255cfdb arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes 8357f0b7ae64 arm64: dts: imx8mp: Disable dsp reserved memory by default 3b2b78d127df arm64: dts: imx8mp: Add NPU Node b13969aeeefc arm64: dts: freescale: debix-som: Add heartbeat LED 5c6068a3aecc arm64: dts: freescale: Add dual-channel LVDS overlay for TQMa8MPxL 37dbfb74c066 arm64: dts: imx8mp-venice-gw74xx: remove unecessary propreties in tpm node 12f50b18b3a5 ARM: dts: nxp: minor whitespace cleanup around '=' 7e4a296e0073 ARM: dts: imx7d-colibri-emmc: Add usdhc aliases aac483d2d190 ARM: dts: imx6qdl-colibri: Add usdhc aliases 534d21c04c41 ARM: dts: imx6qdl-apalis: Add usdhc aliases 4105f51d0c63 ARM: dts: nxp: imx7d-pico: add cpu-supply nodes 4a5f36c1120b dt-bindings: arm: Add compatible for SKOV i.MX8MP RevB board 7efe4371f644 dt-bindings: arm: fsl: add RVE gateway board 3c86e357feb0 dt-bindings: vendor-prefixes: add rve 04660a3dbd9f ARM: dts: broadcom: Add BCM63138's high speed UART 2e36ee7e60cd arm64: dts: ti: k3-am62x: Add overlay for IMX219 8478bfdedc00 arm64: dts: ti: k3-am62a7-sk: Enable camera peripherals a361c10e44cc arm64: dts: ti: k3-am62x: Add overlays for OV5640 820399f7bf0f arm64: dts: ti: k3-am62x-sk: Enable camera peripherals 4de948eeb982 arm64: dts: ti: k3-am625-beagleplay: Add overlays for OV5640 8d6be01e5e7c arm64: dts: ti: k3-am62a-main: Enable CSI2-RX d52951f9d78a arm64: dts: ti: k3-am62-main: Enable CSI2-RX 4d667e27b3fd arm64: dts: ti: k3-am65: Add AM652 dtsi file 3d2161ed0c2b dt-bindings: perf: fsl-imx-ddr: Add i.MX8DXL compatible 189fe310f16e dt-bindings: clock: support i.MX93 ANATOP clock module b44d3f817227 ARM: dts: imx: tqma7: add lm75a sensor (rev. 01xxx) b654e96c546e dt-bindings: display: simple: add Evervision VGG644804 panel 05a02c1a58e1 dt-bindings: ili9881c: Add Ampire AM8001280G LCD panel 96be0427a528 ARM: dts: rockchip: Move uart aliases to SoC dtsi for RK3128 18c0b8b47af4 ARM: dts: rockchip: Move i2c aliases to SoC dtsi for RK3128 0191774d40bb ARM: dts: rockchip: Move gpio aliases to SoC dtsi for RK3128 4b6344ed1b32 ARM: dts: rockchip: Add Sonoff iHost Smart Home Hub 3cbab293b053 dt-bindings: arm: rockchip: Add Sonoff iHost afacdf8be4db ARM: dts: rockchip: Add rv1109 SoC ad1e5ad721a5 ARM: dts: rockchip: Split up rgmii1 pinctrl on rv1126 fc0ef88ee0a1 ARM: dts: rockchip: Add i2c2 node to rv1126 bf739d2f67ae ARM: dts: rockchip: Serial aliases for rv1126 049605e5080d ARM: dts: rockchip: Add alternate UART pins to rv1126 59e8d345382e ARM: dts: rockchip: Enable GPU for XPI-3128 464bddcf0726 ARM: dts: rockchip: Add GPU node for RK3128 8af06043d850 ARM: dts: rockchip: Add power-controller for RK3128 8f65bb97112e dt-bindings: display: himax-hx8394: Add Powkiddy X55 panel ed2d8407a82d dt-bindings: display: Document Himax HX8394 panel rotation 5319f5062c10 dt-bindings: display: simple: Add boe,bp101wx1-100 panel db09be0ff97b ARM: dts: imx6q-apalis: add can power-up delay on ixora board 31fdbd1cd6c6 dt-bindings: display: msm: document the SM8650 Mobile Display Subsystem 52e16372d1c6 dt-bindings: display: msm: document the SM8650 DPU 258f55b8a6c7 dt-bindings: display: msm-dsi-controller-main: document the SM8650 DSI Controller f06034e33173 dt-bindings: display: msm-dsi-phy-7nm: document the SM8650 DSI PHY e7cafbdafccf dt-bindings: display: msm: Add SDM670 MDSS 58504ed9c645 dt-bindings: display/msm: sdm845-dpu: Describe SDM670 d8b80f6fd0c5 dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible 0c71ce621111 arm64: dts: ti: k3-am625-beagleplay: Use UART name in pinmux name 0895f560a171 arm64: dts: ti: k3-am62a7-sk: Add interrupt support for IO Expander 696f6e8d6176 arm64: dts: ti: k3-am625-verdin: Enable Verdin UART2 145b9a5ffb00 arm64: dts: ti: k3-am62-main: Add gpio-ranges properties 0d95f5e22dde arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level 8ccabbb5322f arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board level 4b9d0ee63df8 arm64: dts: ti: k3-am65: Add full compatible to dss-oldi-io-ctrl node b64af72b8e7b arm64: dts: ti: k3-j784s4: Add chipid node to wkup_conf bus a70ca898f980 arm64: dts: ti: k3-j721s2: Add chipid node to wkup_conf bus 638e0242808a arm64: dts: ti: k3-j721e: Add chipid node to wkup_conf bus 0b0e18c3dce2 arm64: dts: ti: k3-j7200: Add chipid node to wkup_conf bus 16b21e3cf2ea arm64: dts: ti: k3-am65: Add chipid node to wkup_conf bus ba6541592794 dt-bindings: iio: light: isl76682: Document ISL76682 3678e1e114f2 dt-bindings: pinctrl: qcom,sm8550-lpass-lpi: add X1E80100 LPASS LPI 4854bb4b43e2 dt-bindings: pinctrl: pinctrl-single: add ti,j7200-padconf compatible 062b01e5c736 dt-bindings: iio: light: add support for Vishay VEML6075 3f170ed89d6f dt-bindings: usb: tps6598x: add reset-gpios property 69a424bfd498 dt-bindings: iio/adc: ti,palmas-gpadc: Drop incomplete example 5cf3c6e7327b dt-bindings: adi,ad5791: Add support for controlling RBUF 7a11d1470ed1 dt-bindings: display: bridge: lt8912b: Add power supplies 562bb8392ec6 spi: spl022: fix sleeping in interrupt context 83c535a1ec6b dt-bindings: iio: honeywell,mprls0025pa: drop ref from pressure properties 7cb202a1a899 dt-bindings: media: add bindings for stm32 dcmipp fce776c784a0 dt-bindings: media: Add bindings for THine THP7312 ISP 23c5bf41000e dt-bindings: media: i2c: add galaxycore,gc2145 dt-bindings e6429afd32f1 dt-bindings: vendor-prefixes: Add prefix for GalaxyCore Inc. d1287a3d111f dt-bindings: gpio: rockchip: add a pattern for gpio hogs e08aefe3ce14 Merge tag 'qcom-dts-for-6.7-2' into arm32-for-6.8 66862cc676b1 ARM: dts: qcom: Add support for HTC One Mini 2 ac27d4b5eaa6 Merge tag 'v6.7-rc4' into media_stage 8a745825682b arm64: dts: qcom: sm6350: Make watchdog bark interrupt edge triggered 4de273b8d5cf arm64: dts: qcom: sc8280xp: Make watchdog bark interrupt edge triggered 94d4ed6b0efb arm64: dts: qcom: sa8775p: Make watchdog bark interrupt edge triggered 9e80723d8b4f arm64: dts: qcom: sm8250: Make watchdog bark interrupt edge triggered ef5fa5d97caa arm64: dts: qcom: sm8150: Make watchdog bark interrupt edge triggered 3879bc4c1c04 arm64: dts: qcom: sdm845: Make watchdog bark interrupt edge triggered 8e7e69e2041a arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered 6584d8b4799e arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered 04f80707bc19 arm64: dts: qcom: sc8180x: drop duplicated PCI iommus property 04597b9d0b6f dt-bindings: arm: qcom: Add HTC One Mini 2 7ff927ff9139 dt-bindings: vendor-prefixes: document HTC Corporation fa70da0426ea arm64: dts: qcom: sm8550: correct TX Soundwire clock ed7e07a029d6 arm64: dts: qcom: sm8450: correct TX Soundwire clock 541ded0776d2 arm64: dts: qcom: sc8180x-primus: Fix HALL_INT polarity 39c752cf5603 arm64: dts: qcom: sc8280xp-crd: fix eDP phy compatible e5319a1187df arm64: dts: qcom: sdm632-fairphone-fp3: Enable LPASS daf6cf6a007f arm64: dts: qcom: msm8916-acer-a1-724: Add notification LED 2a186fbc9370 arm64: dts: qcom: ipq6018: use CPUFreq NVMEM 91d98fe1640a arm64: dts: qcom: msm8939-huawei-kiwi: Add initial device tree 6718a893d987 dt-bindings: arm: qcom: Add Huawei Honor 5X / GR5 (2016) f36c60304a90 arm64: dts: qcom: msm8953: Use non-deprecated qcom,domain in LPASS fa91149122fc arm64: dts: qcom: qrb2210-rb1: add wifi variant property 9862c76b6484 arm64: dts: qcom: qrb2210-rb1: Enable CAN bus controller 90510995b456 arm64: dts: qcom: qrb2210-rb1: Set up HDMI f168a1f5fd2a arm64: dts: qcom: qcm2290: Hook up interconnects a66c95bb5052 arm64: dts: qcom: qcm2290: Add display nodes 1b3d99e8ad9d arm64: dts: qcom: sc7280: Add the missing MDSS icc path 463b9cc7faa3 arm64: dts: qcom: sc7180: Add the missing MDSS icc path a2b32f52593b arm64: dts: qcom: sc8280xp: Add QMP handle to RPMh stats 0541077473ea dt-bindings: soc: qcom: stats: Add QMP handle 46fd383def7f arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg 45ca7aacee21 arm64: dts: qcom: sm8250-xiaomi-elish: Fix typos 9dee357f1ff5 arm64: dts: qcom: msm8939-longcheer-l9100: Add proximity-near-level d6b8367dbb65 arm64: dts: qcom: qrb4210-rb2: Enable bluetooth 9e8fcdbc4d75 arm64: dts: qcom: sm6115: Add UART3 e88a0c4a9117 arm64: dts: qcom: sdm632-fairphone-fp3: Enable WiFi/Bluetooth a808b8c6d7f4 dt-bindings: arm: qcom: Fix html link 004244e4cbd5 arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts 3f55e77ebc86 arm64: dts: qcom: Add base qcm6490 idp board dts 9e08836a864f dt-bindings: arm: qcom: Add QCM6490 IDP and QCS6490 RB3Gen2 board c538a9224903 arm64: dts: qcom: sm4450-qrd: mark QRD4450 reserved gpios 34764956c2e4 arm64: dts: qcom: sm4450-qrd: add QRD4450 uart support b5fe030e21e0 arm64: dts: qcom: sm4450: add uart console support 76478ce29df3 arm64: dts: qcom: sm4450: Add RPMH and Global clock 52ea11ee57e9 arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node d42f9497ccad arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to GCC 9b98d0a1718e dt-bindings: clocks: qcom,gcc-ipq8074: allow QMP PCI PHY PIPE clocks 2417b30e3609 arm64: dts: qcom: msm8953: add SPI interfaces 66dd2b49a0b3 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PM7325 thermals 0b651704285a arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMK7325 thermals 8630d7baedf5 arm64: dts: qcom: qcm6490-fairphone-fp5: Add PM7250B thermals 959371b1b650 iio: adc: Add PM7325 PMIC7 ADC bindings b1e6472aae24 arm64: dts: qcom: sm8250: Add OPP table support to UFSHC 6aeff20d0bd6 arm64: dts: qcom: sdm845: Add OPP table support to UFSHC e8d1d500097e ARM: dts: qcom: msm8974: Add watchdog node 615027dbbe1d dt-bindings: arm: qcom: drop the IPQ board types ebb3e763ee5b arm64: dts: qcom: ipq5018: enable the CPUFreq support 3ca74e9810cf dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible dcbafe8963f4 ARM: dts: qcom: sdx65: correct SPMI node name 98b030d58c93 ARM: dts: qcom: sdx65: add missing GCC clocks 07a16205d0e0 ARM: dts: qcom: sdx65: correct PCIe EP phy-names fe48cd5331dc dt-bindings: display: msm: Add reg bus and rotator interconnects 8c1892c5f696 dt-bindings: display: msm: qcm2290-mdss: Use the non-deprecated DSI compat 7cfd5769a991 dt-bindings: display/msm: qcom, sm8150-mdss: correct DSI PHY compatible 91abf991ed4a dt-bindings: display/msm: qcom, sm8250-mdss: add DisplayPort controller node c203dee53e38 ARM: dts: rockchip: Enable gmac for XPI-3128 a31102a06882 ARM: dts: rockchip: Add gmac node for RK3128 d02bab784773 dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible 61b6b8e5340b dt-bindings: net: qcom,ipa: document SM8650 compatible a0fa8df10233 Merge tag 'renesas-pinctrl-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 6c58c6977828 dt-bindings: gpio: modepin: Describe label property 7f00d1c96321 dt-bindings: display: ti: Add support for am62a7 dss 6bed64726635 arm64: dts: ti: k3-am68-sk-base-board: Add alias for MCU CPSW2G f494c9948974 arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG2 devices 403938b5222f arm64: dts: ti: iot2050: Refactor the m.2 and minipcie power pin 45e3b6aa9185 arm64: dts: ti: iot2050: Definitions for runtime pinmuxing b14c51a347fb arm64: dts: ti: iot2050: Drop unused ecap0 PWM 38f52ad2cea9 arm64: dts: ti: iot2050: Re-add aliases a84e54a6c2a0 arm64: dts: ti: k3-am62x-sk-common: Mark mcu gpio and mcu_gpio_intr as reserved 0baa456c51ce arm64: dts: ti: k3-am62p5-sk: Mark mcu gpio and mcu_gpio_intr as reserved 131aadfec025 arm64: dts: ti: k3-am642-evm/sk: Mark mcu_gpio_intr as reserved bbda0d8be30e arm64: dts: ti: k3-am64-main: Fix typo in epwm_tbclk node name 5e8876dba890 arm64: dts: ti: k3-am65-main: Fix DSS irq trigger type fd78a91dedf3 arm64: dts: ti: k3-am62a-main: Fix GPIO pin count in DT nodes 05614d5b4f00 arm64: dts: ti: minor whitespace cleanup around '=' ca6dff24071e ARM: dts: omap4-embt2ws: Add Bluetooth cff0864e2eea Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 2a2ae1545117 dt-bindings: input: gpio-keys: Allow optional dedicated wakeirq aed93474ebc0 Merge patch series "Add Huashan Pi board support" 318917bad2c6 riscv: dts: sophgo: add Huashan Pi board device tree 8a2824be66df riscv: dts: sophgo: add initial CV1812H SoC device tree 3ff295494c04 riscv: dts: sophgo: cv18xx: Add gpio devices dfcd3e4c81d9 riscv: dts: sophgo: Separate compatible specific for CV1800B soc 8c5d4ad957fa dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles e393d2e6705e dt-bindings: timer: Add SOPHGO CV1812H clint 65cc6be0d442 dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic dce8266bb548 ARM: dts: omap: logicpd-torpedo: do not disguise GNSS device 0f0cee70a881 ARM: dts: omap4-embt2ws: enable 32K clock on WLAN 33dfdcf03832 ARM: dts: ti/omap: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties aa5a9a109405 dt-bindings: power: meson-g12a-power: document ISP power domain a9f86a1f45b5 dt-bindings: marvell: Add Marvell MV88E6060 DSA schema 5024553a10f5 dt-bindings: marvell: Rewrite MV88E6xxx in schema ad4c44e96eec dt-bindings: net: ethernet-switch: Accept special variants 17baedd697fb dt-bindings: net: mvusb: Fix up DSA example 9c7ccdf2dc30 dt-bindings: net: dsa: Require ports or ethernet-ports 8adbf64f3cdd dt-bindings: input: mediatek,pmic-keys: Drop incomplete example cdc098b167e1 dt-bindings: input: sprd,sc27xx-vibrator: Drop incomplete example 0629a76a9d04 dt-bindings: correct white-spaces in examples 2f78b6dd5c42 dt-bindings: reset: hisilicon,hi3660-reset: Drop providers and consumers from example f835598ebf60 dt-bindings: arm/calxeda: drop unneeded quotes 0d2567437a54 dt-bindings: fsl,dpaa2-console: drop unneeded quotes 352ed027a423 dt-bindings: interrupt-controller: qcom,pdc: document pdc on X1E80100 df641036bac4 dt-bindings: qcom,pdc: document the SM8650 Power Domain Controller 1e17b2ba4499 dt-bindings: interrupt-controller: Add SDX75 PDC compatible c0aff4abb03a dt-bindings: reset: imx-src: Simplify compatible schema and drop unneeded quotes df20c9f94014 dt-bindings: reset: qcom: drop unneeded quotes 1516b28c7069 dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/Five SoC a80bc27a0fe8 dt-bindings: reset: Add compatible and DT bindings for Amlogic C3 Reset Controller 0b8db84ecfc4 ASoC: Intel: Soundwire related board and match updates 303600aff1ef Merge v6.7-rc3 into drm-next d03f6dca688d arm64: dts: rockchip: Use NCM6A-IO board for edgeble-neu6b 2dcf7dbe2812 dt-bindings: arm: rockchip: Update edgeble-neu6 bindings b2a45d98f95b arm64: dts: rockchip: add USB3 host on rk3588s-orangepi-5 766aa3119c2f ARM: dts: motorola-mapphone: Add basic support for mz609 and mz617 3ea15a23d9c7 ARM: dts: motorola-mapphone: Move handset devices to a common file 5127524f7e6f ARM: dts: motorola-mapphone: Move LCD to common file for xt875 and xt894 7e16bd264a3a dt-bindings: omap: Add Motorola mapphone mz609 and mz617 tablets 7d420d843f98 ARM: dts: renesas: r9a06g032: Add missing space in compatible 0faa59be192f arm64: dts: renesas: r9a09g011: Add missing space in compatible 807cfe5cde5c dt-bindings: phy: add compatible for Mediatek MT8195 c52707b1bf77 dt-bindings: phy: amlogic,g12a-mipi-dphy-analog: drop unneeded reg property and example 34ec5dda2a01 dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: drop text about parent syscon and drop example f738d7a9dfab dt-bindings: iommu: dart: Add t8103-usb4-dart compatible 2c963cfa7e8e ARM: dts: renesas: armadillo800eva: Add LCD panel a35135dad31c dt-bindings: pinctrl: renesas: Drop unneeded quotes d5212619f0a0 ARM: dts: renesas: r8a7740: Add LCDC nodes 048bdb67a0f6 arm64: dts: renesas: draak: Move HDMI bus properties to correct node ab52a67f9767 arm64: dts: renesas: draak: Make HDMI the default video input dab3ba03f28c Merge 6.7-rc3 into usb-next ec6cd76a8793 arm64: dts: meson-axg: jethub-jxx add support for EEPROM 2da076589eac arm64: dts: amlogic: meson-axg: pinctrl node for NAND cdc5df918882 arm64: dts: amlogic: minor whitespace cleanup around '=' a5dead35fc4b arm64: dts: Add watchdog node for Amlogic S4 SoCs 37c5369b4667 arm64: dts: Add watchdog node for Amlogic C3 SoCs 1d8b2a265b81 dt-bindings: soc: amlogic,meson-gx-hhi-sysctrl: add example covering meson-axg-hhi-sysctrl 9556e1708419 ARM: dts: imx7s: Add DMA channels for CSPI peripherals c1e5b6c6855f arm64: dts: imx8mp-venice-gw72xx: add TPM device fc1ee0050ce4 arm64: dts: imx8mm-venice-gw72xx: add TPM device 5a125bf20bf1 arm64: dts: imx93: update anatop node 292fc296ecdd arm64: dts: imx93-11x11-evk: add 12 ms delay to make sure the VDD_SD power off b81451d8d4d3 arm64: dts: imx93: change tuning start to get a large scan range for standard tuning 7ee940495143 arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC 1b2037987962 arm64: dts: imx8mp: Describe M24C32-D write-lockable page in DH i.MX8MP DHCOM DT 94d5d7d36ba8 ARM: dts: imx6ul: mba6ulx: fix typo in comments cbbed6036bfe ARM: dts: imx6qdl: mba6: fix typo in comments e6c50d6fd99e arm64: dts: imx8mp-beacon-kit: Enable DSI to HDMI Bridge 3743277142d0 arm64: dts: imx8mm: Add CCM interrupts 663758efb819 arm64: dts: imx8mn: Add CCM interrupts 88774bafda13 arm64: dts: imx8mp: Add CCM interrupts e4d9f4208c6c ARM: dts: imx7s: Add missing #thermal-sensor-cells e4c3f040fee6 ARM: dts: imx7s: Fix nand-controller #size-cells 62a7c97c7c3f ARM: dts: imx7s: Fix lcdif compatible 9f3037b332bf ARM: dts: imx7d: Fix coresight funnel ports d844fe5270b1 arm64: dts: freescale: add initial device tree for MBa93xxCA starter kit ad161fbd54ca arm64: dts: freescale: tqma9352-mba93xxla: add 'chassis-type' property 8ec09c8f530c arm64: dts: imx93: Configure clock rate for audio PLL 9d7ba48273ea arm64: dts: imx93: Add audio device nodes b1553710809c dt-bindings: iio: hmc425a: add entry for ADRF5740 Attenuator 471ace1f09be dt-bindings: gpio: brcmstb: drop unneeded quotes f8159413e6f1 ARM: dts: ti: keystone: minor whitespace cleanup around '=' 381a63044158 dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids c1ad3e49f07c dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids c8fb56a76774 dt-bindings: dma: qcom,gpi: document the SM8650 GPI DMA Engine 8e868f10ea21 dt-bindings: dma: rz-dmac: Document RZ/Five SoC e1504d7602c0 dt-bindings: net: qcom,ipa: add SM8550 compatible f118e169a194 dt-bindings: dma: qcom: gpi: add compatible for X1E80100 11518ff4d13c dt-bindings: pinctrl: qcom: Add X1E80100 pinctrl d3fe1008f0c8 ASoC: dt-bindings: correct white-spaces in examples f9b11918132f dt-bindings: crypto: convert Inside Secure SafeXcel to the json-schema 52b8a84c5283 dt-bindings: dma: ti: k3-udma: Describe cfg register regions 9b2e4fa1e7f2 dt-bindings: dma: ti: k3-pktdma: Describe cfg register regions 6d91e2a3766b dt-bindings: dma: ti: k3-bcdma: Describe cfg register regions ea1d92699d2a dt-bindings: dma: ti: k3-*: Add descriptions for register regions 7cf45f021d31 arm64: dts: exynosautov9: use Exynos7 fallbacks for pin wake-up controller dc0e2a7e69c2 arm64: dts: exynos850: use Exynos7 fallbacks for pin wake-up controllers 185cc3e40c9f dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers 54829849af39 Merge branch 'icc-x1e80100' into icc-next 8e2202f335a4 dt-bindings: interconnect: Add Qualcomm X1E80100 SoC 54f1f68e019b dt-bindings: interconnect: qcom-bwmon: document SM8650 BWMONs 4e7bf80ce812 dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm SM8650 SoC 615397ecb02b Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net e673bd9cbb13 dt-bindings: serial: fsl-linflexuart: change the maintainer email address f79b00fe4cab dt-bindings: serial: renesas,sci: Document RZ/Five SoC 911d5cce2a4e Merge tag 'drm-misc-next-2023-11-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next ab1f350663b1 dt-bindings: power: rpmpd: Update part number to X1E80100 6fe8e1a8dc99 dt-bindings: backlight: mp3309c: Remove two required properties cc4e22233cb5 dt-bindings: usb: qcom,dwc3: adjust number of interrupts on SM6125 9161184d7271 dt-bindings: net: renesas,ethertsn: Add Ethernet TSN 788d52642da4 Merge tag 'v6.7-rc2' into media_stage d2975fb00035 dt-bindings: gpu: Add Imagination Technologies PowerVR/IMG GPU 59078ccb21d1 dt-bindings: usb: qcom,dwc3: document the SM8560 SuperSpeed DWC3 USB controller 627316c016dd dt-bindings: usb: renesas,usbhs: Document RZ/Five SoC 99b07ecabc3d dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible 0118ff6d8abd ASoC: dt-bindings: fsl,mqs: Convert format to json-schema 0a9a12593184 ASoC: dt-bindings: sound-card-common: List sound widgets ignoring system suspend 165648aad162 ARM: dts: stm32: add SPI support on STM32F746 8f3fa20269a0 ARM: dts: stm32: add STM32F746 syscfg clock dc50601ba2d8 dt-bindings: net: xlnx,axi-ethernet: Introduce DMA support 72d23e1de1b0 arm64: dts: imx8mp: Add reserve-memory nodes for DSP 9bab315d31f8 spi: axi-spi-engine improvements 23a75f159231 ARM: dts: stm32: use the same 3v3 for SD and DSI nodes on stm32f469-disco 4656437906e9 ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128 25251d661471 ARM: dts: rockchip: Add dwc2 otg fifo siztes for RK3128 2d36fa2aa286 ARM: dts: rockchip: Add USB host clocks for RK3128 4e1bd401bbe3 ARM: dts: rockchip: Add Geniatech XPI-3128 RK3128 board 7e6458d9a7f3 ARM: dts: rockchip: Add sdmmc_det pinctrl for RK3128 12867f1ccb42 dt-bindings: arm: rockchip: Add Geniatech XPI-3128 fda729bcbd69 arm64: dts: rockchip: Add Powkiddy RK2023 317a36f59e1b arm64: dts: rockchip: Update powkiddy,rgb30 include to rk2023 DTSI dc9a81379af6 dt-bindings: arm: rockchip: Add Powkiddy RK2023 70a31fd9ffa3 dt-bindings: spi: axi-spi-engine: convert to yaml b68504144dbe Merge tag 'drm-misc-next-2023-11-17' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 8260e721d1b5 dt-bindings: display: nv3051d: Update NewVision NV3051D compatibles 0a502f9716cc arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 eccf7ee1aefe arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 fbd14cd9ff35 ARM: dts: microchip: sam9x60ek: Add IRQ support for ethernet PHY c86d9749ca2a ARM: dts: microchip: sam9x60_curiosity: Add IRQ support for ethernet PHY 1e1f6887a01b arm64: dts: allwinner: h616: add Orange Pi Zero 2W support 5795c68b5edc dt-bindings: arm: sunxi: add Orange Pi Zero 2W a5b7fa02fbde dt-bindings: crypto: qcom,prng: document SM8650 53be5450f8ac dt-bindings: crypto: qcom-qce: document the SM8650 crypto engine e65dc233e98b dt-bindings: crypto: qcom,inline-crypto-engine: document the SM8650 ICE d2a2bd80cca6 dt-bindings: net: renesas,etheravb: Document RZ/Five SoC f491b5315b58 dt-bindings: Document Marvell Aquantia PHY 7b52e889e53f arm64: dts: rockchip: add analog audio to RK3588 EVB1 92de4720f37c spi: dt-bindings: renesas,rspi: Document RZ/Five SoC 6e54c4bd7590 ASoC: dt-bindings: renesas,rz-ssi: Document RZ/Five SoC 87bb03481662 dt-bindings: adis16460: Add 'spi-cs-inactive-delay-ns' property 91e2c8ceb4de dt-bindings: adis16475: Add 'spi-cs-inactive-delay-ns' property f9fe5526efd5 dt-bindings: iio: Add MCP9600 thermocouple EMF converter 9942ece9d870 dt-bindings: iio: imu: Add Bosch BMI323 49d380d6e152 dt-bindings: adc: provide max34408/9 device tree binding document 895869158303 dt-bindings: media: wave5: add yaml devicetree bindings 77bf61c28407 dt-bindings: arm: Add support for DSB MSR register 18adf91da0ca dt-bindings: arm: Add support for DSB element size 075ac55ca93b dt-bindings: phy: qcom,snps-eusb2: document the SM8650 Synopsys eUSB2 PHY fda8409f7058 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: document the SM8650 QMP USB/DP Combo PHY b0b6815d9143 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document the SM8650 QMP PCIe PHYs db24b834638a dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8650 QMP UFS PHY 6a737e056a8b media: dt-bindings: Add JH7110 Camera Subsystem 716cbea9d35a dt-bindings: power: reset: $ref reboot-mode in nvmem-reboot-mode c8dedfdf167b dt-bindings: power: reset: $ref reboot-mode in syscon-reboot-mode 6c14a95472bb ARM: dts: samsung: s5pv210: fix camera unit addresses/ranges 866767db6bbb ARM: dts: samsung: exynos4: fix camera unit addresses/ranges f0d3848e2cef ARM: dts: samsung: exynos4x12: replace duplicate pmu node with phandle dc6ff9889013 dt-bindings: w1: Add AMD AXI w1 host and MAINTAINERS entry a8a9188e96a6 dt-bindings: power: fsl,scu-pd: Document imx8dl f06b78172daa dt-bindings: qcom,pdc: Add compatible for SM8550 7a87643120eb dt-bindings: input: samsung,s6sy761: convert to DT schema e4ccdd770c53 Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64 7b213bd80e13 dt-bindings: hwinfo: samsung,exynos-chipid: add exynosautov920 compatible 892b87e000d2 dt-bindings: arm: samsung: Document exynosautov920 SADK board binding ce1b89aee7ea dt-bindings: pwm: samsung: add exynosautov920 compatible 5e6bd42714ad dt-bindings: serial: samsung: add exynosautov920-uart compatible 3ea12f0eff84 dt-bindings: samsung: usi: add exynosautov920-usi compatible 5b6e042a72b8 dt-bindings: samsung: exynos-pmu: add exynosautov920 compatible 2dff85192843 dt-bindings: samsung: exynos-sysreg: add exynosautov920 sysreg 3123103c12c0 dt-bindings: pinctrl: samsung: add exynosautov920 5b929ffdc9be arm64: dts: exynos: add gpio-key node for exynosautov9-sadk 6bc5effbe8dd arm64: dts: exynosautov9: add specific compatibles to several blocks 25addf827769 arm64: dts: exynos850: add specific compatibles to several blocks 5ab70c11f08f arm64: dts: exynos7885: add specific compatibles to several blocks f7c77a1ea95a arm64: dts: exynos7: add specific compatibles to several blocks 56493af64c01 arm64: dts: exynos5433: add specific compatibles to several blocks 3530786802b6 dt-bindings: pwm: samsung: add specific compatibles for existing SoC 97419692fe3c ASoC: dt-bindings: samsung-i2s: add specific compatibles for existing SoC 7081448ca2cf dt-bindings: iio: samsung,exynos-adc: add specific compatibles for existing SoC 973115e1f51f dt-bindings: gpu: arm,mali-midgard: add specific compatibles for existing Exynos SoC 6b99281097f0 dt-bindings: samsung: exynos-pmu: add specific compatibles for existing SoC a893a294345b dt-bindings: serial: samsung: add specific compatibles for existing SoC 2a3d0691d56f dt-bindings: rtc: s3c-rtc: add specific compatibles for existing SoC 7e49408d51e6 dt-bindings: pinctrl: samsung: add specific compatibles for existing SoC 1bb1eca74ad5 Merge drm/drm-next into drm-misc-next e9731895ee20 dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatibles for existing SoC 33b5aa8f7d9a ARM: dts: qcom: mdm9615: drop qcom, prefix from SSBI node name fa1f536e3df0 ARM: dts: qcom: ipq8064: drop qcom, prefix from SSBI node name 4e5382dc8820 ARM: dts: qcom: apq8060-dragonboard: rename mpp ADC channels to adc-channel 6be6ba7888ef ARM: dts: qcom: pm8921: Disable keypad by default 5917ae72cd70 ARM: dts: qcom: msm8974: move regulators to board files 551cbcd2547c ARM: dts: qcom: msm8960: drop useless rpm regulators node 6d9878cc6a6a ARM: dts: qcom: msm8660: move RPM regulators to board files d0ed11e33ba0 ARM: dts: qcom: mdm9615: move RPM regulators to board files 1c636116afea ARM: dts: qcom: apq8064: move RPM regulators to board files b9d11fecae9e ARM: dts: qcom: pm8058: switch to interrupts-extended e8a26b432fd4 ARM: dts: qcom: pm8018: switch to interrupts-extended 86831cb445f6 ARM: dts: qcom: pm8921: switch to interrupts-extended 6d6c0b95e077 ARM: dts: qcom: pm8058: use defined IRQ flags 9d0903209824 ARM: dts: qcom: pm8921: move reg property 6a63db48b660 ARM: dts: qcom: pm8018: move reg property 9d6af1dd4790 ARM: dts: qcom: pm8921: reorder nodes 5db5515193a6 ARM: dts: qcom: pm8058: reorder nodes d4df6f1babb5 ARM: dts: qcom: msm8660: split PMIC to separate dtsi files c56480ffb4b8 ARM: dts: qcom: mdm9615: split PMIC to separate dtsi files f8574d2c7c62 ARM: dts: qcom: apq8064: split PMICs to separate dtsi files 298695290d90 ARM: dts: qcom: msm8960: split PMIC to separate dtsi files 1c3c930ec46c ARM: dts: qcom: msm8960: move PMIC interrupts to the board files 7f5541db889f ARM: dts: qcom: msm8660: move PMIC interrupts to the board files 812cfe71b26a ARM: dts: qcom: mdm9615: move PMIC interrupts to the board files f5c8a18b7116 ARM: dts: qcom: apq8064: move PMIC interrupts to the board files b7510b8da2f6 ARM: dts: qcom: msm8960: fix PMIC node labels 6475671dcca1 ARM: dts: qcom: msm8660: fix PMIC node labels 4dfac4d841ef ARM: dts: qcom: mdm9615: fix PMIC node labels 07091c1b87fb ARM: dts: qcom: apq8064: fix PMIC node labels 155004433670 ARM: dts: qcom: strip prefix from PMIC files 21220b16b281 ARM: dts: qcom: mdm9615-wp8548-mangoh-green: group include clauses 3d3f8059a9f6 ARM: dts: qcom: apq8064-nexus7: move sdcc1 node to proper place b9d136b033b8 ARM: dts: qcom: msm8660-surf: use keypad label directly fc4f79da1abe ARM: dts: qcom: msm8960: introduce label for PMIC keypad 0e33f3448e7c ARM: dts: qcom: apq8064: correct XOADC register address 9bed8b24890a ARM: dts: qcom-sdx65: switch USB QMP PHY to new style of bindings edfbe32172f4 ARM: dts: qcom-sdx55: switch USB QMP PHY to new style of bindings c709366fb89e arm64: dts: qcom: sm8350: switch USB QMP PHY to new style of bindings 29a99a6d955d arm64: dts: qcom: sm8250: switch USB QMP PHY to new style of bindings e13f8dc0ea91 arm64: dts: qcom: sm8150: switch USB QMP PHY to new style of bindings bed6aed8ceec arm64: dts: qcom: sdm845: switch USB QMP PHY to new style of bindings 7cb8dff829b0 arm64: dts: qcom: msm8998: switch USB QMP PHY to new style of bindings 77a8ce42cb30 arm64: dts: qcom: msm8996: switch USB QMP PHY to new style of bindings b92a18870b3e arm64: dts: qcom: ipq8074: switch USB QMP PHY to new style of bindings 18dd153b1c8f arm64: dts: qcom: ipq6018: switch USB QMP PHY to new style of bindings ad3769d7933c Merge tag 'qcom-arm64-for-6.7-2' into arm64-for-6.8 8088e683c89b dt-bindings: i2c: samsung,s3c2410-i2c: add specific compatibles for existing SoC c15df41a0c35 dt-bindings: i2c: exynos5: add specific compatibles for existing SoC d755df63e9df dt-bindings: hwinfo: samsung,exynos-chipid: add specific compatibles for existing SoC 6f4cb3f40711 arm64: dts: renesas: rzg2lc-smarc-som: Enable 4-bit tx support 5ddba1791b2b arm64: dts: renesas: rzg2l-smarc-som: Enable 4-bit tx support 75b8e7f58abe regulator: add under-voltage support (part 2) 791f1550a798 Add DMIC slew rate controls e128625eb7cb dt-bindings: pinctrl: document the SM8650 Top Level Mode Multiplexer c3c85cc965c8 dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: add SM8650 LPASS 6da3c9fd1509 ARM: dts: renesas: marzen: Rename keyboard nodes 2d7a77894ba8 ARM: dts: renesas: iwg22d-sodimm: Fix stmpe node names f4c62eb4fbd6 arm64: dts: renesas: Add missing ADV751[13] power supply properties a94c426db9b8 ARM: dts: renesas: Add missing ADV751[13] power supply properties f213adc3b192 ARM: dts: renesas: rcar-gen2: Fix I2C bus demux node names 127c56414e9f riscv: dts: renesas: Convert isa detection to new properties 9836c1c69324 ARM: dts: renesas: blanche: Add FLASH node d446795daa00 ARM: dts: renesas: marzen: Add FLASH node 9a4a8a78013a spi: add stm32f7-spi compatible e74e9793f9c7 regulator: dt-bindings: Add 'regulator-uv-less-critical-window-ms' property eafbf4f37d51 regulator: dt-bindings: Allow system-critical marking for fixed-regulator 52381ed5b4ac regulator: dt-bindings: Add system-critical-regulator property ec8f058714a6 dt-bindings: regulator: qcom,smd-rpm-regulator: Document PM8937 IC cf118cc80e89 dt-bindings: regulator: qcom,spmi-regulator: Document PM8937 PMIC 2ae471b5eeb2 ASoC: dt-bindings: use "soundwire" as controller's node name in examples caa17228e281 ASoC: dt-bindings: qcom,sm8250: add SM8550 sound card 2d2f997a2bdc dt-bindings: es8328: convert to DT schema format 68e113702391 ASoC: dt-bindings: Simplify port schema eac536a576c7 ASoC: dt-bindings: nau8821: Add DMIC slew rate. 409f501ee9b2 dt-bindings: gpu: v3d: Add BCM2712's compatible 22f7441e8685 dt-bindings: display: ssd132x: Remove '-' before compatible enum a3de98e60ec5 ARM: dts: qcom: add device tree for Nokia Lumia 830 9ad6bcd4499d ARM: dts: qcom: add device tree for Nokia Lumia 735 41ee9ea2aefd ARM: dts: qcom: add device tree for Microsoft Lumia 640 XL 0dc127c0d612 ARM: dts: qcom: add device tree for Microsoft Lumia 640 d30c995f440e ARM: dts: qcom: add common dt for MSM8x26 Lumias along with Nokia Lumia 630 ed92546211d5 dt-bindings: arm: qcom: Document MSM8x26-based Lumia phones d783936fa1dc arm64: dts: qcom: msm8939-longcheer-l9100: Enable RGB LED b14cb550d720 arm64: dts: qcom: msm8916-longcheer-l8910: Enable RGB LED 183a2f447424 arm64: dts: qcom: msm8939-samsung-a7: Add sound and modem 9b7d68606781 arm64: dts: qcom: msm8916-samsung-j5: Add sound and modem f382f197e0c5 arm64: dts: qcom: msm8916-samsung-gt5: Add sound and modem 59a815c1572d arm64: dts: qcom: msm8916-longcheer-l8910: Add sound and modem 582b4cfec9a9 ARM: dts: qcom: msm8226: provide dsi phy clocks to mmcc 1703230be2a6 ARM: dts: qcom: msm8974: sort nodes by reg e23f302820cb ARM: dts: qcom: msm8974: replace incorrect indentation in interconnect 373015625e6b arm64: dts: qcom: msm8916-longcheer-l8150: Add sound and modem c1a66861dc32 arm64: dts: qcom: msm8916-asus-z00l: Add sound and modem 489f91f0dfcc arm64: dts: qcom: msm8916-alcatel-idol347: Add sound and modem 2f81e02a3b04 arm64: dts: qcom: msm8916-wingtech-wt88047: Add sound and modem 07047876d71e arm64: dts: qcom: msm8916-samsung-serranove: Add sound and modem 1d94420f32b0 arm64: dts: qcom: msm8916-samsung-a2015: Add sound and modem 9334b10d351c arm64: dts: qcom: msm8916: Add common msm8916-modem-qdsp6.dtsi 30b857e0f639 arm64: dts: qcom: msm8939: Add QDSP6 5b210c47425a arm64: dts: qcom: msm8916: Add QDSP6 f1aed61c2c48 arm64: dts: qcom: msm8939: Add BAM-DMUX WWAN 702f57c12856 arm64: dts: qcom: sc8280xp-x13s: add missing camera LED pin config d21fc2d89cfd arm64: dts: qcom: pm7250b: Use correct node name for gpios ecc4cb08c0f3 arm64: dts: qcom: sc7280: Add Camera Control Interface busses c01ef95e3aa7 arm64: dts: qcom: sdm845-xiaomi-beryllium: enable flash led fe3ccb41dafa arm64: dts: qcom: sdm845-oneplus: enable flash LED 0f6538f89c64 arm64: dts: qcom: sc8280xp-x13s: Use the correct DP PHY compatible c9e8e85b1afd arm64: dts: qcom: msm8916-*: Fix alphabetic node order 9e38e840740d arm64: dts: qcom: msm8939-longcheer-l9100: Enable wcnss_mem 5cdb05e593ef arm64: dts: qcom: msm8916-samsung-gt5: Enable GPU 0d72dfbbf352 arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox 13c545bfe884 arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox 8b57686e7ad0 arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox 11d8f7a1bf44 arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox 9b0b036ea0de arm64: dts: qcom: ipq9574: populate the opp table based on the eFuse f3636ba1edce arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse 8831b26a6579 arm64: dts: qcom: sdm670: add specific cpufreq compatible 8ce87f299cdb arm64: dts: qcom: sm8150: extend the size of the PDC resource b3cbe4ff9c30 arm64: dts: qcom: ipq5018: add QUP1 SPI controller f330c2991aa0 arm64: dts: qcom: qrb4210-rb2: don't force usb peripheral mode daa68cbafb06 arm64: dts: qcom: Enable tsens and thermal for sa8775p SoC 6232143457ae arm64: dts: qcom: sa8775p: Add RPMh sleep stats 973959c2edf1 arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node 4c021a56b758 arm64: dts: qcom: sm6375-pdx225: Add USBPHY regulators 6fb033b4f60e arm64: dts: qcom: sm6375-pdx225: Enable ATH10K WiFi fa14ce25949b arm64: dts: qcom: sm6375-pdx225: Enable MSS e77ac5cceb8e arm64: dts: qcom: sm6375: Add UART1 dec2e7998de5 arm64: dts: qcom: ipq9574: Enable WPS buttons d3619641203e arm64: dts: qcom: ipq9574: Add common RDP dtsi file 9faa71835343 arm64: dts: qcom: ipq5018: Enable USB 71275274da1f arm64: dts: qcom: ipq5018: Add USB related nodes af8b25f21479 arm64: dts: qcom: sc7280: add TRNG node 00e1b06bb47a arm64: dts: qcom: sa8775p: add TRNG node ac7c5d2655a7 arm64: dts: qcom: sm8450: add TRNG node 0087dcd6513a arm64: dts: qcom: sm8550: add TRNG node git-subtree-dir: dts/upstream git-subtree-split: b35b9bd1d4eed2acf8bc38ec5b1b6eef6261b4f0

commit: 93743d241c64bc1f7ecbf3262d1683176551e11f [log] [tgz]
author: Tom Rini <trini@konsulko.com> Mon Apr 01 09:08:13 2024 -0400
committer: Tom Rini <trini@konsulko.com> Mon Apr 01 09:08:13 2024 -0400
tree: 11abd1331cf3b50d686ebe65a24e69373bac27e4
parent: 53633a893a06bd5a0c807287d9cc29337806eaf7 [diff] [blame]
diff --git a/src/arm64/qcom/sm8650.dtsi b/src/arm64/qcom/sm8650.dtsi
new file mode 100644
index 0000000..2df7712
--- /dev/null
+++ b/src/arm64/qcom/sm8650.dtsi

@@ -0,0 +1,6013 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
+#include <dt-bindings/clock/qcom,sm8650-gcc.h>
+#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
+#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+
+		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+
+		pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a520";
+			reg = <0 0>;
+
+			clocks = <&cpufreq_hw 0>;
+
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			qcom,freq-domain = <&cpufreq_hw 0>;
+
+			#cooling-cells = <2>;
+
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a520";
+			reg = <0 0x100>;
+
+			clocks = <&cpufreq_hw 0>;
+
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			qcom,freq-domain = <&cpufreq_hw 0>;
+
+			#cooling-cells = <2>;
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0 0x200>;
+
+			clocks = <&cpufreq_hw 3>;
+
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_200>;
+			capacity-dmips-mhz = <1792>;
+			dynamic-power-coefficient = <238>;
+
+			qcom,freq-domain = <&cpufreq_hw 3>;
+
+			#cooling-cells = <2>;
+
+			L2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0 0x300>;
+
+			clocks = <&cpufreq_hw 3>;
+
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_200>;
+			capacity-dmips-mhz = <1792>;
+			dynamic-power-coefficient = <238>;
+
+			qcom,freq-domain = <&cpufreq_hw 3>;
+
+			#cooling-cells = <2>;
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0 0x400>;
+
+			clocks = <&cpufreq_hw 3>;
+
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_400>;
+			capacity-dmips-mhz = <1792>;
+			dynamic-power-coefficient = <238>;
+
+			qcom,freq-domain = <&cpufreq_hw 3>;
+
+			#cooling-cells = <2>;
+
+			L2_400: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0 0x500>;
+
+			clocks = <&cpufreq_hw 1>;
+
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_500>;
+			capacity-dmips-mhz = <1792>;
+			dynamic-power-coefficient = <238>;
+
+			qcom,freq-domain = <&cpufreq_hw 1>;
+
+			#cooling-cells = <2>;
+
+			L2_500: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a720";
+			reg = <0 0x600>;
+
+			clocks = <&cpufreq_hw 1>;
+
+			power-domains = <&CPU_PD6>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_600>;
+			capacity-dmips-mhz = <1792>;
+			dynamic-power-coefficient = <238>;
+
+			qcom,freq-domain = <&cpufreq_hw 1>;
+
+			#cooling-cells = <2>;
+
+			L2_600: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-x4";
+			reg = <0 0x700>;
+
+			clocks = <&cpufreq_hw 2>;
+
+			power-domains = <&CPU_PD7>;
+			power-domain-names = "psci";
+
+			enable-method = "psci";
+			next-level-cache = <&L2_700>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <588>;
+
+			qcom,freq-domain = <&cpufreq_hw 2>;
+
+			#cooling-cells = <2>;
+
+			L2_700: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+
+				core4 {
+					cpu = <&CPU4>;
+				};
+
+				core5 {
+					cpu = <&CPU5>;
+				};
+
+				core6 {
+					cpu = <&CPU6>;
+				};
+
+				core7 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <550>;
+				exit-latency-us = <750>;
+				min-residency-us = <6700>;
+				local-timer-stop;
+			};
+
+			GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <600>;
+				exit-latency-us = <1300>;
+				min-residency-us = <8136>;
+				local-timer-stop;
+			};
+
+			GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-plus-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <500>;
+				exit-latency-us = <1350>;
+				min-residency-us = <7480>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <750>;
+				exit-latency-us = <2350>;
+				min-residency-us = <9144>;
+			};
+
+			CLUSTER_SLEEP_1: cluster-sleep-1 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x4100c344>;
+				entry-latency-us = <2800>;
+				exit-latency-us = <4400>;
+				min-residency-us = <10150>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sm8650", "qcom,scm";
+			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+		};
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sm8650-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sm8650-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	memory@a0000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0xa0000000 0 0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+		};
+
+		CPU_PD1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+		};
+
+		CPU_PD2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+		};
+
+		CPU_PD3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+		};
+
+		CPU_PD4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+		};
+
+		CPU_PD5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+		};
+
+		CPU_PD6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+		};
+
+		CPU_PD7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
+		};
+
+		CLUSTER_PD: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_SLEEP_0>,
+					     <&CLUSTER_SLEEP_1>;
+		};
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp@80000000 {
+			reg = <0 0x80000000 0 0xe00000>;
+			no-map;
+		};
+
+		cpusys_vm_mem: cpusys-vm@80e00000 {
+			reg = <0 0x80e00000 0 0x400000>;
+			no-map;
+		};
+
+		/* Merged xbl_dtlog, xbl_ramdump and aop_image regions */
+		xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
+			reg = <0 0x81a00000 0 0x260000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@81c60000 {
+			compatible = "qcom,cmd-db";
+			reg = <0 0x81c60000 0 0x20000>;
+			no-map;
+		};
+
+		/* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
+		aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
+			reg = <0 0x81c80000 0 0x74000>;
+			no-map;
+		};
+
+		/* Secdata region can be reused by apps */
+
+		smem: smem@81d00000 {
+			compatible = "qcom,smem";
+			reg = <0 0x81d00000 0 0x200000>;
+			hwlocks = <&tcsr_mutex 3>;
+			no-map;
+		};
+
+		adsp_mhi_mem: adsp-mhi@81f00000 {
+			reg = <0 0x81f00000 0 0x20000>;
+			no-map;
+		};
+
+		pvmfw_mem: pvmfw@824a0000 {
+			reg = <0 0x824a0000 0 0x100000>;
+			no-map;
+		};
+
+		global_sync_mem: global-sync@82600000 {
+			reg = <0 0x82600000 0 0x100000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@82700000 {
+			reg = <0 0x82700000 0 0x100000>;
+			no-map;
+		};
+
+		qdss_mem: qdss@82800000 {
+			reg = <0 0x82800000 0 0x2000000>;
+			no-map;
+		};
+
+		mpss_dsm_mem: mpss-dsm@86b00000 {
+			reg = <0 0x86b00000 0 0x4900000>;
+			no-map;
+		};
+
+		mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
+			reg = <0 0x8b400000 0 0x800000>;
+			no-map;
+		};
+
+		mpss_mem: mpss@8bc00000 {
+			reg = <0 0x8bc00000 0 0xf400000>;
+			no-map;
+		};
+
+		q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
+			reg = <0 0x9b000000 0 0x80000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@9b080000 {
+			reg = <0 0x9b080000 0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi@9b090000 {
+			reg = <0 0x9b090000 0 0xa000>;
+			no-map;
+		};
+
+		gpu_micro_code_mem: gpu-micro-code@9b09a000 {
+			reg = <0 0x9b09a000 0 0x2000>;
+			no-map;
+		};
+
+		spss_region_mem: spss@9b0a0000 {
+			reg = <0 0x9b0a0000 0 0x1e0000>;
+			no-map;
+		};
+
+		/* First part of the "SPU secure shared memory" region */
+		spu_tz_shared_mem: spu-tz-shared@9b280000 {
+			reg = <0 0x9b280000 0 0x60000>;
+			no-map;
+		};
+
+		/* Second part of the "SPU secure shared memory" region */
+		spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
+			reg = <0 0x9b2e0000 0 0x20000>;
+			no-map;
+		};
+
+		camera_mem: camera@9b300000 {
+			reg = <0 0x9b300000 0 0x800000>;
+			no-map;
+		};
+
+		video_mem: video@9bb00000 {
+			reg = <0 0x9bb00000 0 0x800000>;
+			no-map;
+		};
+
+		cvp_mem: cvp@9c300000 {
+			reg = <0 0x9c300000 0 0x700000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@9ca00000 {
+			reg = <0 0x9ca00000 0 0x1400000>;
+			no-map;
+		};
+
+		q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
+			reg = <0 0x9de00000 0 0x80000>;
+			no-map;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
+			reg = <0 0x9de80000 0 0x80000>;
+			no-map;
+		};
+
+		adspslpi_mem: adspslpi@9df00000 {
+			reg = <0 0x9df00000 0 0x4080000>;
+			no-map;
+		};
+
+		rmtfs_mem: rmtfs@d7c00000 {
+			compatible = "qcom,rmtfs-mem";
+			reg = <0 0xd7c00000 0 0x400000>;
+			no-map;
+
+			qcom,client-id = <1>;
+			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+		};
+
+		/* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */
+		tz_merged_mem: tz-merged@d8000000 {
+			reg = <0 0xd8000000 0 0x800000>;
+			no-map;
+		};
+
+		hwfence_shbuf: hwfence-shbuf@e6440000 {
+			reg = <0 0xe6440000 0 0x2dd000>;
+			no-map;
+		};
+
+		trust_ui_vm_mem: trust-ui-vm@f3800000 {
+			reg = <0 0xf3800000 0 0x4400000>;
+			no-map;
+		};
+
+		oem_vm_mem: oem-vm@f7c00000 {
+			reg = <0 0xf7c00000 0 0x4c00000>;
+			no-map;
+		};
+
+		llcc_lpi_mem: llcc-lpi@ff800000 {
+			reg = <0 0xff800000 0 0x600000>;
+			no-map;
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <443>, <429>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		smp2p_adsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_adsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+
+		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&ipcc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <94>, <432>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		smp2p_cdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_cdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-modem {
+		compatible = "qcom,smp2p";
+
+		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&ipcc IPCC_CLIENT_MPSS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <435>, <428>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		smp2p_modem_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_modem_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		ipa_smp2p_out: ipa-ap-to-modem {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		ipa_smp2p_in: ipa-modem-to-ap {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,sm8650-gcc";
+			reg = <0 0x00100000 0 0x1f4200>;
+
+			clocks = <&bi_tcxo_div2>,
+				 <&bi_tcxo_ao_div2>,
+				 <&sleep_clk>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
+				 <&pcie_1_phy_aux_clk>,
+				 <&ufs_mem_phy 0>,
+				 <&ufs_mem_phy 1>,
+				 <&ufs_mem_phy 2>,
+				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		ipcc: mailbox@406000 {
+			compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
+			reg = <0 0x00406000 0 0x1000>;
+
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			#mbox-cells = <2>;
+		};
+
+		gpi_dma2: dma-controller@800000 {
+			compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0 0x00800000 0 0x60000>;
+
+			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+			dma-channels = <12>;
+			dma-channel-mask = <0x3f>;
+			#dma-cells = <3>;
+
+			iommus = <&apps_smmu 0x436 0>;
+
+			dma-coherent;
+
+			status = "disabled";
+		};
+
+		qupv3_id_1: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x008c0000 0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+
+			iommus = <&apps_smmu 0x423 0>;
+
+			dma-coherent;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c8: i2c@880000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00880000 0 0x4000>;
+
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c8_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi8: spi@880000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00880000 0 0x4000>;
+
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c9: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00884000 0 0x4000>;
+
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c9_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi9: spi@884000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00884000 0 0x4000>;
+
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c10: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00888000 0 0x4000>;
+
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c10_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi10: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00888000 0 0x4000>;
+
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c11: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x0088c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c11_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi11: spi@88c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x0088c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c12: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00890000 0 0x4000>;
+
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c12_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi12: spi@890000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00890000 0 0x4000>;
+
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c13: i2c@894000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00894000 0 0x4000>;
+
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c13_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi13: spi@894000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00894000 0 0x4000>;
+
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart14: serial@898000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00898000 0 0x4000>;
+
+				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+				clock-names = "se";
+
+				interconnects =	<&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+
+			uart15: serial@89c000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x0089c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+				clock-names = "se";
+
+				interconnects =	<&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&qup_uart15_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+		};
+
+		i2c_master_hub_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-i2c-master-hub";
+			reg = <0 0x009c0000 0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+			clock-names = "s-ahb";
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c_hub_0: i2c@980000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x00980000 0 0x4000>;
+
+				interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c0_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_1: i2c@984000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x00984000 0 0x4000>;
+
+				interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c1_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_2: i2c@988000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x00988000 0 0x4000>;
+
+				interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c2_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_3: i2c@98c000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x0098c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c3_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_4: i2c@990000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x00990000 0 0x4000>;
+
+				interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c4_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_5: i2c@994000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x00994000 0 0x4000>;
+
+				interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c5_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_6: i2c@998000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x00998000 0 0x4000>;
+
+				interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c6_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_7: i2c@99c000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x0099c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c7_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_8: i2c@9a0000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x009a0000 0 0x4000>;
+
+				interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c8_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_9: i2c@9a4000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0 0x009a4000 0 0x4000>;
+
+				interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c9_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0 0x00a00000 0 0x60000>;
+
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+
+			dma-channels = <12>;
+			dma-channel-mask = <0xc>;
+			#dma-cells = <3>;
+
+			iommus = <&apps_smmu 0xb6 0>;
+			dma-coherent;
+
+			status = "disabled";
+		};
+
+		qupv3_id_0: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x00ac0000 0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+
+			interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+					 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "qup-core";
+
+			iommus = <&apps_smmu 0xa3 0>;
+
+			dma-coherent;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c0: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a80000 0 0x4000>;
+
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c0_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi0: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a80000 0 0x4000>;
+
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c1: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a84000 0 0x4000>;
+
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi1: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a84000 0 0x4000>;
+
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c2: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a88000 0 0x4000>;
+
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi2: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a88000 0 0x4000>;
+
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c3: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a8c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi3: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a8c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c4: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a90000 0 0x4000>;
+
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi4: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a90000 0 0x4000>;
+
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c5: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a94000 0 0x4000>;
+
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi5: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a94000 0 0x4000>;
+
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c6: i2c@a98000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a98000 0 0x4000>;
+
+				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi6: spi@a98000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a98000 0 0x4000>;
+
+				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c7: i2c@a9c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a9c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c7_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi7: spi@a9c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a9c000 0 0x4000>;
+
+				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt  SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		cnoc_main: interconnect@1500000 {
+			compatible = "qcom,sm8650-cnoc-main";
+			reg = <0 0x01500000 0 0x14080>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		config_noc: interconnect@1600000 {
+			compatible = "qcom,sm8650-config-noc";
+			reg = <0 0x01600000 0 0x6200>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,sm8650-system-noc";
+			reg = <0 0x01680000 0 0x1d080>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		pcie_noc: interconnect@16c0000 {
+			compatible = "qcom,sm8650-pcie-anoc";
+			reg = <0 0x016c0000 0 0x12200>;
+
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			compatible = "qcom,sm8650-aggre1-noc";
+			reg = <0 0x016e0000 0 0x16400>;
+
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sm8650-aggre2-noc";
+			reg = <0 0x01700000 0 0x1e400>;
+
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		mmss_noc: interconnect@1780000 {
+			compatible = "qcom,sm8650-mmss-noc";
+			reg = <0 0x01780000 0 0x5b800>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		rng: rng@10c3000 {
+			compatible = "qcom,sm8650-trng", "qcom,trng";
+			reg = <0 0x010c3000 0 0x1000>;
+		};
+
+		pcie0: pci@1c00000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
+			reg = <0 0x01c00000 0 0x3000>,
+			      <0 0x60000000 0 0xf1d>,
+			      <0 0x60000f20 0 0xa8>,
+			      <0 0x60001000 0 0x1000>,
+			      <0 0x60100000 0 0x100000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config";
+
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+				 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "noc_aggr",
+				      "cnoc_sf_axi";
+
+			resets = <&gcc GCC_PCIE_0_BCR>;
+			reset-names = "pci";
+
+			interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem",
+					     "cpu-pcie";
+
+			power-domains = <&gcc PCIE_0_GDSC>;
+
+			iommu-map = <0     &apps_smmu 0x1400 0x1>,
+				    <0x100 &apps_smmu 0x1401 0x1>;
+
+			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			#interrupt-cells = <1>;
+
+			linux,pci-domain = <0>;
+			num-lanes = <2>;
+			bus-range = <0 0xff>;
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
+				 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
+
+			dma-coherent;
+
+			status = "disabled";
+		};
+
+		pcie0_phy: phy@1c06000 {
+			compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
+			reg = <0 0x01c06000 0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
+				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_0_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "rchng",
+				      "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+			reset-names = "phy";
+
+			power-domains = <&gcc PCIE_0_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie0_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		pcie1: pci@1c08000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
+			reg = <0 0x01c08000 0 0x3000>,
+			      <0 0x40000000 0 0xf1d>,
+			      <0 0x40000f20 0 0xa8>,
+			      <0 0x40001000 0 0x1000>,
+			      <0 0x40100000 0 0x100000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config";
+
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+
+			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+				 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "noc_aggr",
+				      "cnoc_sf_axi";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			resets = <&gcc GCC_PCIE_1_BCR>,
+				 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+			reset-names = "pci",
+				      "link_down";
+
+			interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem",
+					     "cpu-pcie";
+
+			power-domains = <&gcc PCIE_1_GDSC>;
+
+			iommu-map = <0     &apps_smmu 0x1480 0x1>,
+				    <0x100 &apps_smmu 0x1481 0x1>;
+
+			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			#interrupt-cells = <1>;
+
+			linux,pci-domain = <1>;
+			num-lanes = <2>;
+			bus-range = <0 0xff>;
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			dma-coherent;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
+				 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
+
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@1c0e000 {
+			compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
+			reg = <0 0x01c0e000 0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
+				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_1_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "rchng",
+				      "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			resets = <&gcc GCC_PCIE_1_PHY_BCR>,
+				 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_nocsr";
+
+			power-domains = <&gcc PCIE_1_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie1_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		cryptobam: dma-controller@1dc4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0 0x01dc4000 0 0x28000>;
+
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+			#dma-cells = <1>;
+
+			iommus = <&apps_smmu 0x480 0>,
+				 <&apps_smmu 0x481 0>;
+
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
+			reg = <0 0x01dfa000 0 0x6000>;
+
+			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "memory";
+
+			dmas = <&cryptobam 4>, <&cryptobam 5>;
+			dma-names = "rx", "tx";
+
+			iommus = <&apps_smmu 0x480 0>,
+				 <&apps_smmu 0x481 0>;
+		};
+
+		ufs_mem_phy: phy@1d80000 {
+			compatible = "qcom,sm8650-qmp-ufs-phy";
+			reg = <0 0x01d80000 0 0x2000>;
+
+			clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+			clock-names = "ref",
+				      "ref_aux";
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			power-domains = <&gcc UFS_MEM_PHY_GDSC>;
+
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		ufs_mem_hc: ufs@1d84000 {
+			compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0 0x01d84000 0 0x3000>;
+
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "rx_lane1_sync_clk";
+			freq-table-hz = <100000000 403000000>,
+					<0 0>,
+					<0 0>,
+					<100000000 403000000>,
+					<100000000 403000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>;
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ufs-ddr",
+					     "cpu-ufs";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			iommus = <&apps_smmu 0x60 0>;
+
+			lanes-per-direction = <2>;
+			qcom,ice = <&ice>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			#reset-cells = <1>;
+
+			status = "disabled";
+		};
+
+		ice: crypto@1d88000 {
+			compatible = "qcom,sm8650-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0 0x01d88000 0 0x8000>;
+
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0 0x01f40000 0 0x20000>;
+
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: clock-controller@1fc0000 {
+			compatible = "qcom,sm8650-tcsr", "syscon";
+			reg = <0 0x01fc0000 0 0xa0000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,sm8650-gpucc";
+			reg = <0 0x03d90000 0 0xa000>;
+
+			clocks = <&bi_tcxo_div2>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		ipa: ipa@3f40000 {
+			compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
+
+			iommus = <&apps_smmu 0x4a0 0x0>,
+				 <&apps_smmu 0x4a2 0x0>;
+			reg = <0 0x3f40000 0 0x10000>,
+			      <0 0x3f50000 0 0x5000>,
+			      <0 0x3e04000 0 0xfc000>;
+			reg-names = "ipa-reg",
+				    "ipa-shared",
+				    "gsi";
+
+			interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "ipa",
+					  "gsi",
+					  "ipa-clock-query",
+					  "ipa-setup-ready";
+
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
+			clock-names = "core";
+
+			interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
+			interconnect-names = "memory",
+					     "config";
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&ipa_smp2p_out 0>,
+					   <&ipa_smp2p_out 1>;
+			qcom,smem-state-names = "ipa-clock-enabled-valid",
+						"ipa-clock-enabled";
+
+			status = "disabled";
+		};
+
+		remoteproc_mpss: remoteproc@4080000 {
+			compatible = "qcom,sm8650-mpss-pas";
+			reg = <0 0x04080000 0 0x4040>;
+
+			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack",
+					  "shutdown-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MSS>;
+			power-domain-names = "cx",
+					     "mss";
+
+			memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
+					<&mpss_dsm_mem>, <&mpss_dsm_mem_2>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_modem_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&ipcc IPCC_CLIENT_MPSS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				qcom,remote-pid = <1>;
+
+				label = "mpss";
+			};
+		};
+
+		lpass_wsa2macro: codec@6aa0000 {
+			compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+			reg = <0 0x06aa0000 0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk",
+				      "macro",
+				      "dcodec",
+				      "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "wsa2-mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr3: soundwire@6ab0000 {
+			compatible = "qcom,soundwire-v2.0.0";
+			reg = <0 0x06ab0000 0 0x10000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&lpass_wsa2macro>;
+			clock-names = "iface";
+			label = "WSA2";
+
+			pinctrl-0 = <&wsa2_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <4>;
+			qcom,dout-ports = <9>;
+
+			qcom,ports-sinterval =		/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
+			qcom,ports-offset1 =		/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
+			qcom,ports-offset2 =		/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
+			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		lpass_rxmacro: codec@6ac0000 {
+			compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
+			reg = <0 0x06ac0000 0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk",
+				      "macro",
+				      "dcodec",
+				      "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr1: soundwire@6ad0000 {
+			compatible = "qcom,soundwire-v2.0.0";
+			reg = <0 0x06ad0000 0 0x10000>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&lpass_rxmacro>;
+			clock-names = "iface";
+			label = "RX";
+
+			pinctrl-0 = <&rx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <0>;
+			qcom,dout-ports = <11>;
+
+			qcom,ports-sinterval =		/bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
+			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
+			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
+			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
+			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
+			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		lpass_txmacro: codec@6ae0000 {
+			compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
+			reg = <0 0x06ae0000 0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk",
+				      "macro",
+				      "dcodec",
+				      "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		lpass_wsamacro: codec@6b00000 {
+			compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+			reg = <0 0x06b00000 0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk",
+				      "macro",
+				      "dcodec",
+				      "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr0: soundwire@6b10000 {
+			compatible = "qcom,soundwire-v2.0.0";
+			reg = <0 0x06b10000 0 0x10000>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&lpass_wsamacro>;
+			clock-names = "iface";
+			label = "WSA";
+
+			pinctrl-0 = <&wsa_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <4>;
+			qcom,dout-ports = <9>;
+
+			qcom,ports-sinterval =		/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
+			qcom,ports-offset1 =		/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
+			qcom,ports-offset2 =		/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
+			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		swr2: soundwire@6d30000 {
+			compatible = "qcom,soundwire-v2.0.0";
+			reg = <0 0x06d30000 0 0x10000>;
+			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "core", "wakeup";
+			clocks = <&lpass_txmacro>;
+			clock-names = "iface";
+			label = "TX";
+
+			pinctrl-0 = <&tx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <4>;
+			qcom,dout-ports = <0>;
+
+			qcom,ports-sinterval-low =	/bits/ 8 <0x01 0x01 0x03 0x03>;
+			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x01 0x01>;
+			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control =	/bits/ 8 <0x01 0x02 0x00 0x00>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+			status = "disabled";
+		};
+
+		lpass_vamacro: codec@6d44000 {
+			compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
+			reg = <0 0x06d44000 0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "mclk",
+				      "macro",
+				      "dcodec";
+
+			#clock-cells = <0>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+		};
+
+		lpass_tlmm: pinctrl@6e80000 {
+			compatible = "qcom,sm8650-lpass-lpi-pinctrl";
+			reg = <0 0x06e80000 0 0x20000>;
+
+			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "core", "audio";
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+			tx_swr_active: tx-swr-active-state {
+				clk-pins {
+					pins = "gpio0";
+					function = "swr_tx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio1", "gpio2", "gpio14";
+					function = "swr_tx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			rx_swr_active: rx-swr-active-state {
+				clk-pins {
+					pins = "gpio3";
+					function = "swr_rx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio4", "gpio5";
+					function = "swr_rx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			dmic01_default: dmic01-default-state {
+				clk-pins {
+					pins = "gpio6";
+					function = "dmic1_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio7";
+					function = "dmic1_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			dmic02_default: dmic02-default-state {
+				clk-pins {
+					pins = "gpio8";
+					function = "dmic2_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio9";
+					function = "dmic2_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			wsa_swr_active: wsa-swr-active-state {
+				clk-pins {
+					pins = "gpio10";
+					function = "wsa_swr_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio11";
+					function = "wsa_swr_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			wsa2_swr_active: wsa2-swr-active-state {
+				clk-pins {
+					pins = "gpio15";
+					function = "wsa2_swr_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio16";
+					function = "wsa2_swr_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+		};
+
+		lpass_lpiaon_noc: interconnect@7400000 {
+			compatible = "qcom,sm8650-lpass-lpiaon-noc";
+			reg = <0 0x07400000 0 0x19080>;
+
+			#interconnect-cells = <2>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		lpass_lpicx_noc: interconnect@7430000 {
+			compatible = "qcom,sm8650-lpass-lpicx-noc";
+			reg = <0 0x07430000 0 0x3a200>;
+
+			#interconnect-cells = <2>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		lpass_ag_noc: interconnect@7e40000 {
+			compatible = "qcom,sm8650-lpass-ag-noc";
+			reg = <0 0x07e40000 0 0xe080>;
+
+			#interconnect-cells = <2>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		sdhc_2: mmc@8804000 {
+			compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08804000 0 0x1000>;
+
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq",
+					  "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "xo";
+
+			interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "sdhc-ddr",
+					     "cpu-sdhc";
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc2_opp_table>;
+
+			iommus = <&apps_smmu 0x540 0>;
+
+			bus-width = <4>;
+
+			/* Forbid SDR104/SDR50 - broken hw! */
+			sdhci-caps-mask = <0x3 0>;
+
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc2_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+			};
+		};
+
+		mdss: display-subsystem@ae00000 {
+			compatible = "qcom,sm8650-mdss";
+			reg = <0 0x0ae00000 0 0x1000>;
+			reg-names = "mdss";
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+				 <&gcc GCC_DISP_HF_AXI_CLK>,
+				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+					<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "mdp0-mem",
+					     "mdp1-mem";
+
+			power-domains = <&dispcc MDSS_GDSC>;
+
+			iommus = <&apps_smmu 0x1c00 0x2>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			mdss_mdp: display-controller@ae01000 {
+				compatible = "qcom,sm8650-dpu";
+				reg = <0 0x0ae01000 0 0x8f000>,
+				      <0 0x0aeb0000 0 0x2008>;
+				reg-names = "mdp",
+					    "vbif";
+
+				interrupts-extended = <&mdss 0>;
+
+				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "nrt_bus",
+					      "iface",
+					      "lut",
+					      "core",
+					      "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+
+				operating-points-v2 = <&mdp_opp_table>;
+
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						dpu_intf2_out: endpoint {
+							remote-endpoint = <&mdss_dsi1_in>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						dpu_intf0_out: endpoint {
+							remote-endpoint = <&mdss_dp0_in>;
+						};
+					};
+				};
+
+				mdp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-200000000 {
+						opp-hz = /bits/ 64 <200000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-325000000 {
+						opp-hz = /bits/ 64 <325000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-375000000 {
+						opp-hz = /bits/ 64 <375000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-514000000 {
+						opp-hz = /bits/ 64 <514000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@ae94000 {
+				compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae94000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupts-extended = <&mdss 4>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>,
+							 <&mdss_dsi0_phy 1>;
+
+				operating-points-v2 = <&mdss_dsi_opp_table>;
+
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				phys = <&mdss_dsi0_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+
+				mdss_dsi_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-187500000 {
+						opp-hz = /bits/ 64 <187500000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-300000000 {
+						opp-hz = /bits/ 64 <300000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-358000000 {
+						opp-hz = /bits/ 64 <358000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@ae95000 {
+				compatible = "qcom,sm8650-dsi-phy-4nm";
+				reg = <0 0x0ae95000 0 0x200>,
+				      <0 0x0ae95200 0 0x280>,
+				      <0 0x0ae95500 0 0x400>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface",
+					      "ref";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss_dsi1: dsi@ae96000 {
+				compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae96000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupts-extended = <&mdss 5>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+						  <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi1_phy 0>,
+							 <&mdss_dsi1_phy 1>;
+
+				operating-points-v2 = <&mdss_dsi_opp_table>;
+
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				phys = <&mdss_dsi1_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dsi1_in: endpoint {
+							remote-endpoint = <&dpu_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss_dsi1_phy: phy@ae97000 {
+				compatible = "qcom,sm8650-dsi-phy-4nm";
+				reg = <0 0x0ae97000 0 0x200>,
+				      <0 0x0ae97200 0 0x280>,
+				      <0 0x0ae97500 0 0x400>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface",
+					      "ref";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss_dp0: displayport-controller@af54000 {
+				compatible = "qcom,sm8650-dp";
+				reg = <0 0xaf54000 0 0x104>,
+				      <0 0xaf54200 0 0xc0>,
+				      <0 0xaf55000 0 0x770>,
+				      <0 0xaf56000 0 0x9c>,
+				      <0 0xaf57000 0 0x9c>;
+
+				interrupts-extended = <&mdss 12>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+							 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+				operating-points-v2 = <&dp_opp_table>;
+
+				power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+				phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
+				phy-names = "dp";
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				dp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-162000000 {
+						opp-hz = /bits/ 64 <162000000>;
+						required-opps = <&rpmhpd_opp_low_svs_d1>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dp0_in: endpoint {
+							remote-endpoint = <&dpu_intf0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dp0_out: endpoint {
+						};
+					};
+				};
+			};
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,sm8650-dispcc";
+			reg = <0 0x0af00000 0 0x20000>;
+
+			clocks = <&bi_tcxo_div2>,
+				 <&bi_tcxo_ao_div2>,
+				 <&gcc GCC_DISP_AHB_CLK>,
+				 <&sleep_clk>,
+				 <&mdss_dsi0_phy 0>,
+				 <&mdss_dsi0_phy 1>,
+				 <&mdss_dsi1_phy 0>,
+				 <&mdss_dsi1_phy 1>,
+				 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+				 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+				 <0>, /* dp1 */
+				 <0>,
+				 <0>, /* dp2 */
+				 <0>,
+				 <0>, /* dp3 */
+				 <0>;
+
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+
+			status = "disabled";
+		};
+
+		usb_1_hsphy: phy@88e3000 {
+			compatible = "qcom,sm8650-snps-eusb2-phy",
+				     "qcom,sm8550-snps-eusb2-phy";
+			reg = <0 0x088e3000 0 0x154>;
+
+			clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_dp_qmpphy: phy@88e8000 {
+			compatible = "qcom,sm8650-qmp-usb3-dp-phy";
+			reg = <0 0x088e8000 0 0x3000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "com_aux",
+				      "usb3_pipe";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+			reset-names = "phy",
+				      "common";
+
+			power-domains = <&gcc USB3_PHY_GDSC>;
+
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_dp_qmpphy_out: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_dp_qmpphy_usb_ss_in: endpoint {
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usb_dp_qmpphy_dp_in: endpoint {
+					};
+				};
+			};
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
+			reg = <0 0x0a6f8800 0 0x400>;
+
+			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&tcsr TCSR_USB3_CLKREF_EN>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x0a600000 0 0xcd00>;
+
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+
+				iommus = <&apps_smmu 0x40 0>;
+
+				phys = <&usb_1_hsphy>,
+				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+				phy-names = "usb2-phy",
+					    "usb3-phy";
+
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,usb2-gadget-lpm-disable;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,is-utmi-l1-suspend;
+				snps,usb3_lpm_capable;
+				snps,usb2-lpm-disable;
+				snps,has-lpm-erratum;
+				tx-fifo-resize;
+
+				dma-coherent;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						usb_1_dwc3_hs: endpoint {
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						usb_1_dwc3_ss: endpoint {
+						};
+					};
+				};
+			};
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sm8650-pdc", "qcom,pdc";
+			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+
+			interrupt-parent = <&intc>;
+
+			qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+					  <125 63 1>, <126 716 12>,
+					  <138 251 5>, <143 244 4>;
+
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		tsens0: thermal-sensor@c228000 {
+			compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
+			reg = <0 0x0c228000 0 0x1000>, /* TM */
+			      <0 0x0c222000 0 0x1000>; /* SROT */
+
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow",
+					  "critical";
+
+			#qcom,sensors = <15>;
+
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens1: thermal-sensor@c229000 {
+			compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
+			reg = <0 0x0c229000 0 0x1000>, /* TM */
+			      <0 0x0c223000 0 0x1000>; /* SROT */
+
+			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow",
+					  "critical";
+
+			#qcom,sensors = <16>;
+
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens2: thermal-sensor@c22a000 {
+			compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
+			reg = <0 0x0c22a000 0 0x1000>, /* TM */
+			      <0 0x0c224000 0 0x1000>; /* SROT */
+
+			interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow",
+					  "critical";
+
+			#qcom,sensors = <13>;
+
+			#thermal-sensor-cells = <1>;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0 0x0c300000 0 0x400>;
+
+			interrupt-parent = <&ipcc>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+						     IRQ_TYPE_EDGE_RISING>;
+
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+			#clock-cells = <0>;
+		};
+
+		sram@c3f0000 {
+			compatible = "qcom,rpmh-stats";
+			reg = <0 0x0c3f0000 0 0x400>;
+		};
+
+		spmi_bus: spmi@c400000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0 0x0c400000 0 0x3000>,
+			      <0 0x0c500000 0 0x4000000>,
+			      <0 0x0c440000 0 0x80000>,
+			      <0 0x0c4c0000 0 0x20000>,
+			      <0 0x0c42d000 0 0x4000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			qcom,bus-id = <0>;
+
+			interrupt-controller;
+			#interrupt-cells = <4>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,sm8650-tlmm";
+			reg = <0 0x0f100000 0 0x300000>;
+
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			gpio-ranges = <&tlmm 0 0 211>;
+
+			wakeup-parent = <&pdc>;
+
+			hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio64", "gpio65";
+				function = "i2chub0_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio66", "gpio67";
+				function = "i2chub0_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio68", "gpio69";
+				function = "i2chub0_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio70", "gpio71";
+				function = "i2chub0_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio72", "gpio73";
+				function = "i2chub0_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c5_data_clk: hub-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio74", "gpio75";
+				function = "i2chub0_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c6_data_clk: hub-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio76", "gpio77";
+				function = "i2chub0_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c7_data_clk: hub-i2c7-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio78", "gpio79";
+				function = "i2chub0_se7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c8_data_clk: hub-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio206", "gpio207";
+				function = "i2chub0_se8";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c9_data_clk: hub-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio80", "gpio81";
+				function = "i2chub0_se9";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			pcie0_default_state: pcie0-default-state {
+				perst-pins {
+					pins = "gpio94";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio95";
+					function = "pcie0_clk_req_n";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio96";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			pcie1_default_state: pcie1-default-state {
+				perst-pins {
+					pins = "gpio97";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio98";
+					function = "pcie1_clk_req_n";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio99";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio32", "gpio33";
+				function = "qup1_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio36", "gpio37";
+				function = "qup1_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio40", "gpio41";
+				function = "qup1_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio44", "gpio45";
+				function = "qup1_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio48", "gpio49";
+				function = "qup1_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio52", "gpio53";
+				function = "qup1_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio56", "gpio57";
+				function = "qup1_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio60", "gpio61";
+				function = "qup1_se7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio0", "gpio1";
+				function = "qup2_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio4", "gpio5";
+				function = "qup2_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup2_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio12", "gpio13";
+				function = "qup2_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio16", "gpio17";
+				function = "qup2_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio20", "gpio21";
+				function = "qup2_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio24", "gpio25";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_spi0_cs: qup-spi0-cs-state {
+				pins = "gpio35";
+				function = "qup1_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi0_data_clk: qup-spi0-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio32", "gpio33", "gpio34";
+				function = "qup1_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi1_cs: qup-spi1-cs-state {
+				pins = "gpio39";
+				function = "qup1_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi1_data_clk: qup-spi1-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio36", "gpio37", "gpio38";
+				function = "qup1_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio43";
+				function = "qup1_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio40", "gpio41", "gpio42";
+				function = "qup1_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi3_cs: qup-spi3-cs-state {
+				pins = "gpio47";
+				function = "qup1_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi3_data_clk: qup-spi3-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio44", "gpio45", "gpio46";
+				function = "qup1_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi4_cs: qup-spi4-cs-state {
+				pins = "gpio51";
+				function = "qup1_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio48", "gpio49", "gpio50";
+				function = "qup1_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_cs: qup-spi5-cs-state {
+				pins = "gpio55";
+				function = "qup1_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_data_clk: qup-spi5-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio52", "gpio53", "gpio54";
+				function = "qup1_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio59";
+				function = "qup1_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio56", "gpio57", "gpio58";
+				function = "qup1_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi7_cs: qup-spi7-cs-state {
+				pins = "gpio63";
+				function = "qup1_se7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi7_data_clk: qup-spi7-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio60", "gpio61", "gpio62";
+				function = "qup1_se7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_cs: qup-spi8-cs-state {
+				pins = "gpio3";
+				function = "qup2_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_data_clk: qup-spi8-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup2_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_cs: qup-spi9-cs-state {
+				pins = "gpio7";
+				function = "qup2_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_data_clk: qup-spi9-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio4", "gpio5", "gpio6";
+				function = "qup2_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi10_cs: qup-spi10-cs-state {
+				pins = "gpio11";
+				function = "qup2_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi10_data_clk: qup-spi10-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio8", "gpio9", "gpio10";
+				function = "qup2_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi11_cs: qup-spi11-cs-state {
+				pins = "gpio15";
+				function = "qup2_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi11_data_clk: qup-spi11-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio12", "gpio13", "gpio14";
+				function = "qup2_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi12_cs: qup-spi12-cs-state {
+				pins = "gpio19";
+				function = "qup2_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi12_data_clk: qup-spi12-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio16", "gpio17", "gpio18";
+				function = "qup2_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi13_cs: qup-spi13-cs-state {
+				pins = "gpio23";
+				function = "qup2_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi13_data_clk: qup-spi13-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup2_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi14_cs: qup-spi14-cs-state {
+				pins = "gpio27";
+				function = "qup2_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi14_data_clk: qup-spi14-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio24", "gpio25", "gpio26";
+				function = "qup2_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_uart14_default: qup-uart14-default-state {
+				/* TX, RX */
+				pins = "gpio26", "gpio27";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+				/* CTS, RTS */
+				pins = "gpio24", "gpio25";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			qup_uart15_default: qup-uart15-default-state {
+				/* TX, RX */
+				pins = "gpio30", "gpio31";
+				function = "qup2_se7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0 0x15000000 0 0x100000>;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+
+			dma-coherent;
+		};
+
+		intc: interrupt-controller@17100000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0x17100000 0 0x10000>,		/* GICD */
+			      <0 0x17180000 0 0x200000>;	/* GICR * 8 */
+
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+			#interrupt-cells = <3>;
+			interrupt-controller;
+
+			#redistributor-regions = <1>;
+			redistributor-stride = <0 0x40000>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@17140000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0 0x17140000 0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+		};
+
+		timer@17420000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0 0x17420000 0 0x1000>;
+
+			ranges = <0 0 0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17421000 {
+				reg = <0x17421000 0x1000>,
+				      <0x17422000 0x1000>;
+
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <0>;
+			};
+
+			frame@17423000 {
+				reg = <0x17423000 0x1000>;
+
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <1>;
+
+				status = "disabled";
+			};
+
+			frame@17425000 {
+				reg = <0x17425000 0x1000>;
+
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <2>;
+
+				status = "disabled";
+			};
+
+			frame@17427000 {
+				reg = <0x17427000 0x1000>;
+
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <3>;
+
+				status = "disabled";
+			};
+
+			frame@17429000 {
+				reg = <0x17429000 0x1000>;
+
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <4>;
+
+				status = "disabled";
+			};
+
+			frame@1742b000 {
+				reg = <0x1742b000 0x1000>;
+
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <5>;
+
+				status = "disabled";
+			};
+
+			frame@1742d000 {
+				reg = <0x1742d000 0x1000>;
+
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <6>;
+
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@17a00000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0 0x17a00000 0 0x10000>,
+			      <0 0x17a10000 0 0x10000>,
+			      <0 0x17a20000 0 0x10000>,
+			      <0 0x17a30000 0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			power-domains = <&CLUSTER_PD>;
+
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
+					  <WAKE_TCS      2>, <CONTROL_TCS   0>;
+
+			label = "apps_rsc";
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm8650-rpmh-clk";
+
+				clocks = <&xo_board>;
+				clock-names = "xo";
+
+				#clock-cells = <1>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,sm8650-rpmhpd";
+
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				#power-domain-cells = <1>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-16 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-48 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_d2: opp-52 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					};
+
+					rpmhpd_opp_low_svs_d1: opp-56 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					};
+
+					rpmhpd_opp_low_svs_d0: opp-60 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					};
+
+					rpmhpd_opp_low_svs: opp-64 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_l1: opp-80 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					};
+
+					rpmhpd_opp_svs: opp-128 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l0: opp-144 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-192 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp-256 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-320 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-336 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-384 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-416 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		cpufreq_hw: cpufreq@17d91000 {
+			compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
+			reg = <0 0x17d91000 0 0x1000>,
+			      <0 0x17d92000 0 0x1000>,
+			      <0 0x17d93000 0 0x1000>,
+			      <0 0x17d94000 0 0x1000>;
+			reg-names = "freq-domain0",
+				    "freq-domain1",
+				    "freq-domain2",
+				    "freq-domain3";
+
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0",
+					  "dcvsh-irq-1",
+					  "dcvsh-irq-2",
+					  "dcvsh-irq-3";
+
+			clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+
+		pmu@24091000 {
+			compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0 0x24091000 0 0x1000>;
+
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <2086000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <2929000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <5931000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <6515000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <7980000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <10437000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <12157000>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <14060000>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <16113000>;
+				};
+			};
+		};
+
+		pmu@240b7400 {
+			compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0 0x240b7400 0 0x600>;
+
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <4577000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <7110000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <9155000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <12298000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <14236000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <16265000>;
+				};
+			};
+		};
+
+		gem_noc: interconnect@24100000 {
+			compatible = "qcom,sm8650-gem-noc";
+			reg = <0 0x24100000 0 0xc5080>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		system-cache-controller@25000000 {
+			compatible = "qcom,sm8650-llcc";
+			reg = <0 0x25000000 0 0x200000>,
+			      <0 0x25400000 0 0x200000>,
+			      <0 0x25200000 0 0x200000>,
+			      <0 0x25600000 0 0x200000>,
+			      <0 0x25800000 0 0x200000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc2_base",
+				    "llcc3_base",
+				    "llcc_broadcast_base";
+
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		remoteproc_adsp: remoteproc@30000000 {
+			compatible = "qcom,sm8650-adsp-pas";
+			reg = <0 0x30000000 0 0x100>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				qcom,remote-pid = <2>;
+
+				label = "lpass";
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+					label = "adsp";
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1043 0x20>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1044 0x20>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1045 0x20>;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1046 0x20>;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+
+						iommus = <&apps_smmu 0x1007 0x40>,
+							 <&apps_smmu 0x1067 0x0>,
+							 <&apps_smmu 0x1087 0x0>;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
+		nsp_noc: interconnect@320c0000 {
+			compatible = "qcom,sm8650-nsp-noc";
+			reg = <0 0x320c0000 0 0xf080>;
+
+			qcom,bcm-voters = <&apps_bcm_voter>;
+
+			#interconnect-cells = <2>;
+		};
+
+		remoteproc_cdsp: remoteproc@32300000 {
+			compatible = "qcom,sm8650-cdsp-pas";
+			reg = <0 0x32300000 0 0x1400000>;
+
+			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>,
+					<&rpmhpd RPMHPD_NSP>;
+			power-domain-names = "cx",
+					     "mxc",
+					     "nsp";
+
+			memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_cdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&ipcc IPCC_CLIENT_CDSP
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				qcom,remote-pid = <5>;
+
+				label = "cdsp";
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+					label = "cdsp";
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+
+						iommus = <&apps_smmu 0x1961 0x0>,
+							 <&apps_smmu 0x0c01 0x20>,
+							 <&apps_smmu 0x19c1 0x0>;
+					};
+
+					compute-cb@2 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <2>;
+
+						iommus = <&apps_smmu 0x1962 0x0>,
+							 <&apps_smmu 0x0c02 0x20>,
+							 <&apps_smmu 0x19c2 0x0>;
+					};
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+
+						iommus = <&apps_smmu 0x1963 0x0>,
+							 <&apps_smmu 0x0c03 0x20>,
+							 <&apps_smmu 0x19c3 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+
+						iommus = <&apps_smmu 0x1964 0x0>,
+							 <&apps_smmu 0x0c04 0x20>,
+							 <&apps_smmu 0x19c4 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+
+						iommus = <&apps_smmu 0x1965 0x0>,
+							 <&apps_smmu 0x0c05 0x20>,
+							 <&apps_smmu 0x19c5 0x0>;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+
+						iommus = <&apps_smmu 0x1966 0x0>,
+							 <&apps_smmu 0x0c06 0x20>,
+							 <&apps_smmu 0x19c6 0x0>;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+
+						iommus = <&apps_smmu 0x1967 0x0>,
+							 <&apps_smmu 0x0c07 0x20>,
+							 <&apps_smmu 0x19c7 0x0>;
+					};
+
+					compute-cb@8 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <8>;
+
+						iommus = <&apps_smmu 0x1968 0x0>,
+							 <&apps_smmu 0x0c08 0x20>,
+							 <&apps_smmu 0x19c8 0x0>;
+					};
+				};
+			};
+		};
+	};
+
+	thermal-zones {
+		aoss0-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				aoss0-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpuss0-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpuss0-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpuss1-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpuss1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpuss2-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpuss2-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpuss3-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpuss3-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu2-top-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu2-bottom-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu3-top-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu3-bottom-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu4-top-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu4-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu4-bottom-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu4-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu5-top-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu5-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu5-bottom-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu5-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu6-top-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 13>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu6-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu6-bottom-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens0 14>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu6-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		aoss1-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				aoss1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu7-top-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu7-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu7-middle-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu7-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu7-bottom-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu7-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu0-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu0-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu1-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu1-critical {
+					temperature = <110000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nsphvx0-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				nsphvx1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		nsphvx1-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				nsphvx1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		nsphmx0-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				nsphmx0-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		nsphmx1-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				nsphmx1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		nsphmx2-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				nsphmx2-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		nsphmx3-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				nsphmx3-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		video-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				video-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		ddr-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 13>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				ddr-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera0-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 14>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				camera0-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera1-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens1 15>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				camera1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		aoss2-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				aoss2-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss0-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss0-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss1-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss2-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss2-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss3-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss3-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss4-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss4-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss5-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss5-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss6-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss6-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss7-thermal {
+			polling-delay-passive = <10>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				gpuss7-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		modem0-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				modem0-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		modem1-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				modem1-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		modem2-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				modem2-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		modem3-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&tsens2 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				modem3-critical {
+					temperature = <110000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
commit	93743d241c64bc1f7ecbf3262d1683176551e11f	[log] [tgz]
author	Tom Rini <trini@konsulko.com>	Mon Apr 01 09:08:13 2024 -0400
committer	Tom Rini <trini@konsulko.com>	Mon Apr 01 09:08:13 2024 -0400
tree	11abd1331cf3b50d686ebe65a24e69373bac27e4
parent	53633a893a06bd5a0c807287d9cc29337806eaf7 [diff] [blame]