/* SPDX-License-Identifier: BSD-3-Clause */ | |
/* | |
* Cadence DDR Driver | |
* | |
* Copyright (C) 2012-2022 Cadence Design Systems, Inc. | |
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ | |
*/ | |
#ifndef LPDDR4_J721E_H | |
#define LPDDR4_J721E_H | |
#include "lpddr4_j721e_ctl_regs_rw_masks.h" | |
#define DSLICE_NUM (4U) | |
#define ASLICE_NUM (1U) | |
#define DSLICE0_REG_COUNT (140U) | |
#define DSLICE1_REG_COUNT (140U) | |
#define DSLICE2_REG_COUNT (140U) | |
#define DSLICE3_REG_COUNT (140U) | |
#define ASLICE0_REG_COUNT (52U) | |
#define PHY_CORE_REG_COUNT (140U) | |
#endif /* LPDDR4_J721E_H */ |