commit 932413838214174e1bc3eb043c60ba1f6e39a1e3
author Richard Retanubun <RichardRetanubun@RuggedCom.com> Thu Mar 24 08:58:11 2011 +0000
committer jason <jason@jason-ThinkPad-T61.(none)> Thu Sep 20 20:39:27 2012 +0800
tree eef4fe1f59521cf6a2096434f0c600b1e82fc138
parent 8d8dac9f0e34f2436f4f033859bcf71412ff3058

ColdFire: Queued SPI driver

This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>

arch/m68k/include/asm/coldfire/qspi.h

diff --git a/arch/m68k/include/asm/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h
index 8bcd2e4..9fd98f6 100644
--- a/arch/m68k/include/asm/coldfire/qspi.h
+++ b/arch/m68k/include/asm/coldfire/qspi.h
@@ -98,7 +98,7 @@
 #define QSPI_QAR_RECV			(0x0010)
 #define QSPI_QAR_CMD			(0x0020)
 
-/* DR */
+/* DR with RAM command word definitions */
 #define QSPI_QDR_CONT			(0x8000)
 #define QSPI_QDR_BITSE			(0x4000)
 #define QSPI_QDR_DT			(0x2000)