ColdFire: Queued SPI driver
This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.
Tested with MCF5270 which have 4 chip selects.
Activate by #define CONFIG_CF_QSPI in board config.
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
diff --git a/arch/m68k/include/asm/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h
index 8bcd2e4..9fd98f6 100644
--- a/arch/m68k/include/asm/coldfire/qspi.h
+++ b/arch/m68k/include/asm/coldfire/qspi.h
@@ -98,7 +98,7 @@
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
-/* DR */
+/* DR with RAM command word definitions */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h
index d25261b..b2bc051 100644
--- a/arch/m68k/include/asm/m5271.h
+++ b/arch/m68k/include/asm/m5271.h
@@ -171,6 +171,32 @@
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
+/* Bit definitions and macros for PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F
+#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0
+#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80
+#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF
+#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20
+#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7
+#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18
+#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10
+#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB
+#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04
+#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00
+#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC
+#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03
+#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02
+#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00
+
+/* Bit definitions and macros for PAR_TIMER for QSPI */
+#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF
+#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000
+#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F
+#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040
+
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040