/* | |
* Port Masks | |
*/ | |
#ifndef __BFIN_PERIPHERAL_PORT__ | |
#define __BFIN_PERIPHERAL_PORT__ | |
/* PORT_MUX Masks */ | |
#define PJSE 0x0001 | |
#define PJCE_MASK 0x0006 | |
#define PJCE_SPORT 0x0000 | |
#define PJCE_CAN 0x0001 | |
#define PJCE_SPI 0x0002 | |
#define PFDE 0x0008 | |
#define PFTE 0x0010 | |
#define PFS6E 0x0020 | |
#define PFS5E 0x0040 | |
#define PFS4E 0x0080 | |
#define PFFE 0x0100 | |
#define PGSE 0x0200 | |
#define PGRE 0x0400 | |
#define PGTE 0x0800 | |
/* Port F Masks */ | |
#define PF0 0x0001 | |
#define PF1 0x0002 | |
#define PF2 0x0004 | |
#define PF3 0x0008 | |
#define PF4 0x0010 | |
#define PF5 0x0020 | |
#define PF6 0x0040 | |
#define PF7 0x0080 | |
#define PF8 0x0100 | |
#define PF9 0x0200 | |
#define PF10 0x0400 | |
#define PF11 0x0800 | |
#define PF12 0x1000 | |
#define PF13 0x2000 | |
#define PF14 0x4000 | |
#define PF15 0x8000 | |
/* Port G Masks */ | |
#define PG0 0x0001 | |
#define PG1 0x0002 | |
#define PG2 0x0004 | |
#define PG3 0x0008 | |
#define PG4 0x0010 | |
#define PG5 0x0020 | |
#define PG6 0x0040 | |
#define PG7 0x0080 | |
#define PG8 0x0100 | |
#define PG9 0x0200 | |
#define PG10 0x0400 | |
#define PG11 0x0800 | |
#define PG12 0x1000 | |
#define PG13 0x2000 | |
#define PG14 0x4000 | |
#define PG15 0x8000 | |
/* Port H Masks */ | |
#define PH0 0x0001 | |
#define PH1 0x0002 | |
#define PH2 0x0004 | |
#define PH3 0x0008 | |
#define PH4 0x0010 | |
#define PH5 0x0020 | |
#define PH6 0x0040 | |
#define PH7 0x0080 | |
#define PH8 0x0100 | |
#define PH9 0x0200 | |
#define PH10 0x0400 | |
#define PH11 0x0800 | |
#define PH12 0x1000 | |
#define PH13 0x2000 | |
#define PH14 0x4000 | |
#define PH15 0x8000 | |
#endif |