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git01.mediatek.com / filogic / uboot / 8d1ce4bf6d333c9d4af6cb18d19adb0a4f829463 / . / board / freescale / t104xrdb / t1042_pi_spi_rcw.cfg
blob: b1d8b4c65afd7fc380f5479801f1a29fe55a47f4 [file] [log] [blame]
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x06
0c18000e 0e000000 00000000 00000000
06000002 00400002 58106000 01000000
00000000 00000000 00000000 00030810
00000000 01fe0a06 00000000 00000000