| /* |
| * Copyright (C) 2016 Amarula Solutions B.V. |
| * Copyright (C) 2016 Engicam S.r.l. |
| * Author: Jagan Teki <jagan@amarulasolutions.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <common.h> |
| #include <mmc.h> |
| |
| #include <asm/io.h> |
| #include <asm/gpio.h> |
| #include <linux/sizes.h> |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/imx-common/iomux-v3.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #ifdef CONFIG_NAND_MXS |
| |
| #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_SRE_FAST) |
| #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| |
| static iomux_v3_cfg_t const nand_pads[] = { |
| MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), |
| }; |
| |
| static void setup_gpmi_nand(void) |
| { |
| struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| /* config gpmi nand iomux */ |
| imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); |
| |
| clrbits_le32(&mxc_ccm->CCGR4, |
| MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| |
| /* |
| * config gpmi and bch clock to 100 MHz |
| * bch/gpmi select PLL2 PFD2 400M |
| * 100M = 400M / 4 |
| */ |
| clrbits_le32(&mxc_ccm->cscmr1, |
| MXC_CCM_CSCMR1_BCH_CLK_SEL | |
| MXC_CCM_CSCMR1_GPMI_CLK_SEL); |
| clrsetbits_le32(&mxc_ccm->cscdr1, |
| MXC_CCM_CSCDR1_BCH_PODF_MASK | |
| MXC_CCM_CSCDR1_GPMI_PODF_MASK, |
| (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | |
| (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); |
| |
| /* enable gpmi and bch clock gating */ |
| setbits_le32(&mxc_ccm->CCGR4, |
| MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); |
| |
| /* enable apbh clock gating */ |
| setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| } |
| #endif /* CONFIG_NAND_MXS */ |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| int board_mmc_get_env_dev(int devno) |
| { |
| /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ |
| return (devno == 0) ? 0 : 1; |
| } |
| |
| static void mmc_late_init(void) |
| { |
| char cmd[32]; |
| char mmcblk[32]; |
| u32 dev_no = mmc_get_env_dev(); |
| |
| setenv_ulong("mmcdev", dev_no); |
| |
| /* Set mmcblk env */ |
| sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); |
| setenv("mmcroot", mmcblk); |
| |
| sprintf(cmd, "mmc dev %d", dev_no); |
| run_command(cmd, 0); |
| } |
| #endif |
| |
| int board_late_init(void) |
| { |
| switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> |
| IMX6_BMODE_SHIFT) { |
| case IMX6_BMODE_SD: |
| case IMX6_BMODE_ESD: |
| case IMX6_BMODE_MMC: |
| case IMX6_BMODE_EMMC: |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| mmc_late_init(); |
| #endif |
| setenv("modeboot", "mmcboot"); |
| break; |
| case IMX6_BMODE_NAND: |
| setenv("modeboot", "nandboot"); |
| break; |
| default: |
| setenv("modeboot", ""); |
| break; |
| } |
| |
| if (is_mx6ul()) { |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| setenv("fdt_file", "imx6ul-isiot-emmc.dtb"); |
| #else |
| setenv("fdt_file", "imx6ul-isiot-nand.dtb"); |
| #endif |
| } |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| #ifdef CONFIG_NAND_MXS |
| setup_gpmi_nand(); |
| #endif |
| return 0; |
| } |
| |
| int dram_init(void) |
| { |
| gd->ram_size = imx_ddr_size(); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_SPL_BUILD |
| #include <libfdt.h> |
| #include <spl.h> |
| |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/mx6-ddr.h> |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| static iomux_v3_cfg_t const uart1_pads[] = { |
| MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| /* MMC board initialization is needed till adding DM support in SPL */ |
| #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) |
| #include <mmc.h> |
| #include <fsl_esdhc.h> |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| static iomux_v3_cfg_t const usdhc1_pads[] = { |
| MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| |
| /* VSELECT */ |
| MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| /* CD */ |
| MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| /* RST_B */ |
| MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const usdhc2_pads[] = { |
| MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) |
| #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) |
| |
| struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| {USDHC1_BASE_ADDR, 0, 4}, |
| {USDHC2_BASE_ADDR, 0, 8}, |
| }; |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC1_BASE_ADDR: |
| ret = !gpio_get_value(USDHC1_CD_GPIO); |
| break; |
| case USDHC2_BASE_ADDR: |
| ret = !gpio_get_value(USDHC2_CD_GPIO); |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| int i, ret; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-boot device node) (Physical Port) |
| * mmc0 USDHC1 |
| * mmc1 USDHC2 |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); |
| gpio_direction_input(USDHC1_CD_GPIO); |
| usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| break; |
| case 1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc1_pads, ARRAY_SIZE(usdhc2_pads)); |
| gpio_direction_input(USDHC2_CD_GPIO); |
| usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| break; |
| default: |
| printf("Warning - USDHC%d controller not supporting\n", |
| i + 1); |
| return 0; |
| } |
| |
| ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| if (ret) { |
| printf("Warning: failed to initialize mmc dev %d\n", i); |
| return ret; |
| } |
| } |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| void board_boot_order(u32 *spl_boot_list) |
| { |
| u32 bmode = imx6_src_get_boot_mode(); |
| u8 boot_dev = BOOT_DEVICE_MMC1; |
| |
| switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { |
| case IMX6_BMODE_SD: |
| case IMX6_BMODE_ESD: |
| /* SD/eSD - BOOT_DEVICE_MMC1 */ |
| break; |
| case IMX6_BMODE_MMC: |
| case IMX6_BMODE_EMMC: |
| /* MMC/eMMC */ |
| boot_dev = BOOT_DEVICE_MMC2; |
| break; |
| default: |
| /* Default - BOOT_DEVICE_MMC1 */ |
| printf("Wrong board boot order\n"); |
| break; |
| } |
| |
| spl_boot_list[0] = boot_dev; |
| } |
| #endif |
| #endif /* CONFIG_FSL_ESDHC */ |
| |
| static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { |
| .grp_addds = 0x00000030, |
| .grp_ddrmode_ctl = 0x00020000, |
| .grp_b0ds = 0x00000030, |
| .grp_ctlds = 0x00000030, |
| .grp_b1ds = 0x00000030, |
| .grp_ddrpke = 0x00000000, |
| .grp_ddrmode = 0x00020000, |
| .grp_ddr_type = 0x000c0000, |
| }; |
| |
| static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { |
| .dram_dqm0 = 0x00000030, |
| .dram_dqm1 = 0x00000030, |
| .dram_ras = 0x00000030, |
| .dram_cas = 0x00000030, |
| .dram_odt0 = 0x00000030, |
| .dram_odt1 = 0x00000030, |
| .dram_sdba2 = 0x00000000, |
| .dram_sdclk_0 = 0x00000008, |
| .dram_sdqs0 = 0x00000038, |
| .dram_sdqs1 = 0x00000030, |
| .dram_reset = 0x00000030, |
| }; |
| |
| static struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| .p0_mpwldectrl0 = 0x00070007, |
| .p0_mpdgctrl0 = 0x41490145, |
| .p0_mprddlctl = 0x40404546, |
| .p0_mpwrdlctl = 0x4040524D, |
| }; |
| |
| struct mx6_ddr_sysinfo ddr_sysinfo = { |
| .dsize = 0, |
| .cs_density = 20, |
| .ncs = 1, |
| .cs1_mirror = 0, |
| .rtt_wr = 2, |
| .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ |
| .walat = 1, /* Write additional latency */ |
| .ralat = 5, /* Read additional latency */ |
| .mif3_mode = 3, /* Command prediction working mode */ |
| .bi_on = 1, /* Bank interleaving enabled */ |
| .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| .ddr_type = DDR_TYPE_DDR3, |
| }; |
| |
| static struct mx6_ddr3_cfg mem_ddr = { |
| .mem_speed = 800, |
| .density = 4, |
| .width = 16, |
| .banks = 8, |
| .rowaddr = 15, |
| .coladdr = 10, |
| .pagesz = 2, |
| .trcd = 1375, |
| .trcmin = 4875, |
| .trasmin = 3500, |
| }; |
| |
| static void ccgr_init(void) |
| { |
| struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| |
| writel(0x00c03f3f, &ccm->CCGR0); |
| writel(0xfcffff00, &ccm->CCGR1); |
| writel(0x0cffffcc, &ccm->CCGR2); |
| writel(0x3f3c3030, &ccm->CCGR3); |
| writel(0xff00fffc, &ccm->CCGR4); |
| writel(0x033f30ff, &ccm->CCGR5); |
| writel(0x00c00fff, &ccm->CCGR6); |
| } |
| |
| static void spl_dram_init(void) |
| { |
| mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| } |
| |
| void board_init_f(ulong dummy) |
| { |
| /* setup AIPS and disable watchdog */ |
| arch_cpu_init(); |
| |
| ccgr_init(); |
| |
| /* iomux and setup of i2c */ |
| imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| |
| /* setup GP timer */ |
| timer_init(); |
| |
| /* UART clocks enabled and gd valid - init serial console */ |
| preloader_console_init(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| /* load/boot image from boot device */ |
| board_init_r(NULL, 0); |
| } |
| #endif /* CONFIG_SPL_BUILD */ |