| * Exynos DWC_mobile_storage |
| |
| The Exynos provides DWC_mobile_storage interface which supports |
| . Embedded Multimedia Cards (EMMC-version 4.5) |
| . Secure Digital memory (SD mem-version 2.0) |
| . Secure Digital I/O (SDIO-version 3.0) |
| . Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1) |
| |
| The Exynos DWC_mobile_storage provides four channels. |
| SOC specific and Board specific properties are channel specific. |
| |
| Required SoC Specific Properties: |
| |
| - compatible: should be |
| - samsung,exynos4412-dw-mshc: for Exynos4 platforms |
| - samsung,exynos-dwmmc: for Exynos5 platforms |
| - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block) |
| |
| - reg: physical base address of the controller and length of memory mapped |
| region. |
| |
| - interrupts: The interrupt number to the cpu. |
| |
| Required Board Specific Properties: |
| |
| - #address-cells: should be 1. |
| - #size-cells: should be 0. |
| - bus-width: The width of the bus used to interface the devices |
| supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO). |
| . Typically the bus width is 4 or 8. |
| - samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu) |
| clock (0..7). |
| - samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode |
| operation. |
| . First value is CIU clock phase shift value for TX mode (0..7). |
| . Second value is CIU clock phase shift value for RX mode (0..7). |
| - samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode |
| operation. If missing, values from samsung,dw-mshc-sdr-timing are used. |
| . First value is CIU clock phase shift value for TX mode (0..7). |
| . Second value is CIU clock phase shift value for RX mode (0..7). |
| |
| Example: |
| |
| mmc@12200000 { |
| bus-width = <8>; |
| non-removable; |
| samsung,dw-mshc-ciu-div = <3>; |
| samsung,dw-mshc-sdr-timing = <1 3>; |
| samsung,dw-mshc-ddr-timing = <0 2>; |
| }; |
| |
| In the above example, |
| . The bus width is 8 |
| . Divider value for CLKSEL register is 3. The CIU clock rate will be |
| calculated as SDCLKIN / (3 + 1). |
| . SDR and DDR timings are comprised of 2 values as explained below |
| 1 - SelClk_sample |
| 3 - SelClk_drv |
| . The 'non-removable' flag indicates whether the particular device |
| cannot be removed (always present) or it is a removable device. |
| Flag is present - Indicates that the device cannot be removed. |
| Flag is not present - Indicates that the device is removable. |