Update of new NAND code
Patch by Ladislav Michl, 13 Sep 2005
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index c2b69fb..648a10d 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -58,6 +58,14 @@
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
+#define writeb(v,a) __arch_putb(v,a)
+#define writew(v,a) __arch_putw(v,a)
+#define writel(v,a) __arch_putl(v,a)
+
+#define readb(a) __arch_getb(a)
+#define readw(a) __arch_getw(a)
+#define readl(a) __arch_getl(a)
+
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
new file mode 100644
index 0000000..30d2654
--- /dev/null
+++ b/include/configs/netstar.h
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * Configuation settings for the TI OMAP NetStar board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/omap1510.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP1510 1 /* which is in a 5910 */
+
+/* Input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
+#define CONFIG_XTAL_FREQ 12000000
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R /* There is nothing to really init */
+#define BOARD_LATE_INIT /* but we flash the LEDs here */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CFG_DEVICE_NULLDEV 1 /* enable null device */
+#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+/*
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS 1
+#if (PHYS_SDRAM_1_SIZE == SZ_32M)
+/*#if 1*/
+#define CFG_FLASH_CFI /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT 128
+#else
+#define PHYS_FLASH_1_SIZE SZ_1M
+#define CFG_MAX_FLASH_SECT 19
+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
+#endif
+
+#define CFG_MONITOR_BASE PHYS_FLASH_1
+#define CFG_MONITOR_LEN SZ_256K
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH
+#define ENV_IS_SOLITARY
+#define CFG_ENV_ADDR 0x4000
+#define CFG_ENV_SIZE SZ_8K
+#define CFG_ENV_SECT_SIZE SZ_8K
+#define CFG_ENV_ADDR_REDUND 0x6000
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/
+#define CFG_MALLOC_LEN SZ_4M
+
+/*
+ * The stack size is set up in start.S using the settings below
+ */
+/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
+#define CONFIG_STACKSIZE SZ_1M /* regular stack */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE 0x04000300
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE (-4)
+#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
+/*#define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * NAND flash
+ */
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x04000000 + (2 << 23)
+#define CONFIG_NEW_NAND_CODE
+
+/*
+ * JFFS2 partitions (mtdparts command line support)
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
+
+#if 0
+#define CONFIG_COMMANDS (CFG_CMD_BDI | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ENV | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_IMI | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_NET | \
+ CFG_CMD_MEMORY | \
+ CFG_CMD_PING | \
+ CFG_CMD_RUN)
+
+#else
+#define CONFIG_COMMANDS (CFG_CMD_BDI | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ENV | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_NAND | \
+ CFG_CMD_IMI | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_NET | \
+ CFG_CMD_MEMORY | \
+ CFG_CMD_PING | \
+ CFG_CMD_RUN)
+
+#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
+#endif
+
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+#define CONFIG_LOOPW
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CFG_AUTOLOAD "n" /* No autoload */
+#define CONFIG_BOOTCOMMAND "run nboot"
+#define CONFIG_PREBOOT "run setup"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "setup=setenv bootargs console=ttyS0,$baudrate " \
+ "$mtdparts\0" \
+ "ospart=0\0" \
+ "setpart=" \
+ "if test -n $swapos; then " \
+ "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
+ "setenv swapos; saveenv; " \
+ "else " \
+ "chpart nand0,$ospart; " \
+ "fi\0" \
+ "nfsargs=setenv bootargs $bootargs " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+ "nfsroot=$rootpath root=/dev/nfs\0" \
+ "flashargs=run setpart;setenv bootargs $bootargs " \
+ "root=/dev/mtdblock$partition ro " \
+ "rootfstype=jffs2\0" \
+ "initrdargs=setenv bootargs $bootargs " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+ "iboot=bootp;run initrdargs;tftp;bootm\0" \
+ "fboot=run flashargs;fsload /boot/uImage;bootm\0" \
+ "nboot=bootp;run nfsargs;tftp;bootm\0"
+
+#if 0 /* feel free to disable for development */
+#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
+#define CONFIG_BOOT_RETRY_TIME 30
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "# " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+
+#define CFG_MEMTEST_START PHYS_SDRAM_1
+#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
+
+/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+ * This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE OMAP1510_TIMER1_BASE
+#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+#define OMAP5910_DPLL_DIV 1
+#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
+ (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+
+#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
+#define OMAP5910_LCD_DIV 2 /* CKL/4 */
+#define OMAP5910_ARM_DIV 0 /* CKL/1 */
+#define OMAP5910_DSP_DIV 0 /* CKL/1 */
+#define OMAP5910_TC_DIV 1 /* CKL/2 */
+#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
+#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
+
+#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
+#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
+ (OMAP5910_LCD_DIV << 2) | \
+ (OMAP5910_ARM_DIV << 4) | \
+ (OMAP5910_DSP_DIV << 6) | \
+ (OMAP5910_TC_DIV << 8) | \
+ (OMAP5910_DSP_MMU_DIV << 10) | \
+ (OMAP5910_ARM_TIM_SEL << 12))
+
+#endif /* __CONFIG_H */
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index afe96b5..3d1d416 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -1,7 +1,7 @@
/*
* $Id: mtd-abi.h,v 1.7 2004/11/23 15:37:32 gleixner Exp $
*
- * Portions of MTD ABI definition which are shared by kernel and user space
+ * Portions of MTD ABI definition which are shared by kernel and user space
*/
#ifndef __MTD_ABI_H__
@@ -27,17 +27,17 @@
#define MTD_OTHER 14
#define MTD_UNKNOWN 15
-#define MTD_CLEAR_BITS 1 // Bits can be cleared (flash)
-#define MTD_SET_BITS 2 // Bits can be set
-#define MTD_ERASEABLE 4 // Has an erase function
-#define MTD_WRITEB_WRITEABLE 8 // Direct IO is possible
-#define MTD_VOLATILE 16 // Set for RAMs
-#define MTD_XIP 32 // eXecute-In-Place possible
-#define MTD_OOB 64 // Out-of-band data (NAND flash)
-#define MTD_ECC 128 // Device capable of automatic ECC
-#define MTD_NO_VIRTBLOCKS 256 // Virtual blocks not allowed
+#define MTD_CLEAR_BITS 1 /* Bits can be cleared (flash) */
+#define MTD_SET_BITS 2 /* Bits can be set */
+#define MTD_ERASEABLE 4 /* Has an erase function */
+#define MTD_WRITEB_WRITEABLE 8 /* Direct IO is possible */
+#define MTD_VOLATILE 16 /* Set for RAMs */
+#define MTD_XIP 32 /* eXecute-In-Place possible */
+#define MTD_OOB 64 /* Out-of-band data (NAND flash) */
+#define MTD_ECC 128 /* Device capable of automatic ECC */
+#define MTD_NO_VIRTBLOCKS 256 /* Virtual blocks not allowed */
-// Some common devices / combinations of capabilities
+/* Some common devices / combinations of capabilities */
#define MTD_CAP_ROM 0
#define MTD_CAP_RAM (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE)
#define MTD_CAP_NORFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE)
@@ -45,31 +45,31 @@
#define MTD_WRITEABLE (MTD_CLEAR_BITS|MTD_SET_BITS)
-// Types of automatic ECC/Checksum available
-#define MTD_ECC_NONE 0 // No automatic ECC available
-#define MTD_ECC_RS_DiskOnChip 1 // Automatic ECC on DiskOnChip
-#define MTD_ECC_SW 2 // SW ECC for Toshiba & Samsung devices
+/* Types of automatic ECC/Checksum available */
+#define MTD_ECC_NONE 0 /* No automatic ECC available */
+#define MTD_ECC_RS_DiskOnChip 1 /* Automatic ECC on DiskOnChip */
+#define MTD_ECC_SW 2 /* SW ECC for Toshiba & Samsung devices */
/* ECC byte placement */
-#define MTD_NANDECC_OFF 0 // Switch off ECC (Not recommended)
-#define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode)
-#define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme
-#define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read)
-#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default
+#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */
+#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */
+#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */
+#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */
+#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */
struct mtd_info_user {
uint8_t type;
uint32_t flags;
- uint32_t size; // Total size of the MTD
+ uint32_t size; /* Total size of the MTD */
uint32_t erasesize;
- uint32_t oobblock; // Size of OOB blocks (e.g. 512)
- uint32_t oobsize; // Amount of OOB data per block (e.g. 16)
+ uint32_t oobblock; /* Size of OOB blocks (e.g. 512) */
+ uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */
uint32_t ecctype;
uint32_t eccsize;
};
struct region_info_user {
- uint32_t offset; /* At which this region starts,
+ uint32_t offset; /* At which this region starts,
* from the beginning of the MTD */
uint32_t erasesize; /* For this region */
uint32_t numblocks; /* Number of blocks in this region */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 9ef4cce..13e9080 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -1,4 +1,4 @@
-/*
+/*
* $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $
*
* Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
@@ -46,7 +46,7 @@
struct mtd_info {
u_char type;
u_int32_t flags;
- u_int32_t size; // Total size of the MTD
+ u_int32_t size; /* Total size of the MTD */
/* "Major" erase size for the device. Naïve users may take this
* to be the only erase size available, or may use the more detailed
@@ -54,25 +54,25 @@
*/
u_int32_t erasesize;
- u_int32_t oobblock; // Size of OOB blocks (e.g. 512)
- u_int32_t oobsize; // Amount of OOB data per block (e.g. 16)
- u_int32_t oobavail; // Number of bytes in OOB area available for fs
+ u_int32_t oobblock; /* Size of OOB blocks (e.g. 512) */
+ u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */
+ u_int32_t oobavail; /* Number of bytes in OOB area available for fs */
u_int32_t ecctype;
u_int32_t eccsize;
-
- // Kernel-only stuff starts here.
+
+ /* Kernel-only stuff starts here. */
char *name;
int index;
- // oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO)
+ /* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */
struct nand_oobinfo oobinfo;
/* Data for variable erase regions. If numeraseregions is zero,
- * it means that the whole device has erasesize as given above.
+ * it means that the whole device has erasesize as given above.
*/
int numeraseregions;
- struct mtd_erase_region_info *eraseregions;
+ struct mtd_erase_region_info *eraseregions;
/* This really shouldn't be here. It can go away in 2.5 */
u_int32_t bank_size;
@@ -95,10 +95,10 @@
int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
- /*
- * Methods to access the protection register area, present in some
+ /*
+ * Methods to access the protection register area, present in some
* flash devices. The user data is one time programmable but the
- * factory data is read only.
+ * factory data is read only.
*/
int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf);
@@ -109,14 +109,14 @@
#if 0
/* kvec-based read/write methods. We need these especially for NAND flash,
with its limited number of write cycles per erase.
- NB: The 'count' parameter is the number of _vectors_, each of
+ NB: The 'count' parameter is the number of _vectors_, each of
which contains an (ofs, len) tuple.
*/
int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen);
- int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from,
+ int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from,
size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen);
- int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to,
+ int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to,
size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
#endif
/* Sync */
@@ -179,7 +179,7 @@
#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args)
#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args)
#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args)
-#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0)
+#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0)
#ifdef CONFIG_MTD_PARTITIONS
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 9a0108f..065e1cb 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -24,7 +24,7 @@
* bat later if I did something naughty.
* 10-11-2000 SJH Added private NAND flash structure for driver
* 10-24-2000 SJH Added prototype for 'nand_scan' function
- * 10-29-2001 TG changed nand_chip structure to support
+ * 10-29-2001 TG changed nand_chip structure to support
* hardwarespecific function for accessing control lines
* 02-21-2002 TG added support for different read/write adress and
* ready/busy line access function
@@ -36,14 +36,14 @@
* CONFIG_MTD_NAND_ECC_JFFS2 is not set
* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
*
- * 08-29-2002 tglx nand_chip structure: data_poi for selecting
+ * 08-29-2002 tglx nand_chip structure: data_poi for selecting
* internal / fs-driver buffer
* support for 6byte/512byte hardware ECC
* read_ecc, write_ecc extended for different oob-layout
* oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
* NAND_YAFFS_OOB
* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
- * Split manufacturer and device ID structures
+ * Split manufacturer and device ID structures
*
* 02-08-2004 tglx added option field to nand structure for chip anomalities
* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
@@ -120,7 +120,7 @@
#define NAND_STATUS_READY 0x40
#define NAND_STATUS_WP 0x80
-/*
+/*
* Constants for ECC_MODES
*/
@@ -162,12 +162,12 @@
#define NAND_CACHEPRG 0x00000008
/* Chip has copy back function */
#define NAND_COPYBACK 0x00000010
-/* AND Chip which has 4 banks and a confusing page / block
+/* AND Chip which has 4 banks and a confusing page / block
* assignment. See Renesas datasheet for further information */
#define NAND_IS_AND 0x00000020
/* Chip has a array of 4 pages which can be read without
* additional ready /busy waits */
-#define NAND_4PAGE_ARRAY 0x00000040
+#define NAND_4PAGE_ARRAY 0x00000040
/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS \
@@ -186,8 +186,8 @@
/* Use a flash based bad block table. This option is passed to the
* default bad block table function. */
#define NAND_USE_FLASH_BBT 0x00010000
-/* The hw ecc generator provides a syndrome instead a ecc value on read
- * This can only work if we have the ecc bytes directly behind the
+/* The hw ecc generator provides a syndrome instead a ecc value on read
+ * This can only work if we have the ecc bytes directly behind the
* data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
#define NAND_HWECC_SYNDROME 0x00020000
@@ -218,7 +218,7 @@
#if 0
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
- * @lock: protection lock
+ * @lock: protection lock
* @active: the mtd device which holds the controller currently
*/
struct nand_hw_control {
@@ -229,8 +229,8 @@
/**
* struct nand_chip - NAND Private Flash Chip Data
- * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
- * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
* @read_byte: [REPLACEABLE] read one byte from the chip
* @write_byte: [REPLACEABLE] write one byte to the chip
* @read_word: [REPLACEABLE] read one word from the chip
@@ -253,7 +253,7 @@
* be provided if a hardware ECC is available
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
- * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
+ * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
* @eccsize: [INTERN] databytes used per ecc-calculation
* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsteps: [INTERN] number of ecc calculation steps per page
@@ -265,7 +265,7 @@
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
* @chip_shift: [INTERN] number of address bits in one chip
- * @data_buf: [INTERN] internal buffer for one page + oob
+ * @data_buf: [INTERN] internal buffer for one page + oob
* @oob_buf: [INTERN] oob buffer for one eraseblock
* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
* @data_poi: [INTERN] pointer to a data buffer
@@ -280,20 +280,20 @@
* @bbt: [INTERN] bad block table pointer
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
- * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
* @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
* @priv: [OPTIONAL] pointer to private chip date
*/
-
+
struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
-
+
u_char (*read_byte)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, u_char byte);
u16 (*read_word)(struct mtd_info *mtd);
void (*write_word)(struct mtd_info *mtd, u16 word);
-
+
void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
@@ -358,7 +358,7 @@
* @name: Identify the device type
* @id: device ID code
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
- * If the pagesize is 0, then the real pagesize
+ * If the pagesize is 0, then the real pagesize
* and the eraseize are determined from the
* extended id bytes in the chip
* @erasesize: Size of an erase block in the flash device.
@@ -387,7 +387,7 @@
extern struct nand_flash_dev nand_flash_ids[];
extern struct nand_manufacturers nand_manuf_ids[];
-/**
+/**
* struct nand_bbt_descr - bad block table descriptor
* @options: options for this descriptor
* @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
@@ -398,14 +398,14 @@
* @version: version read from the bbt page during scan
* @len: length of the pattern, if 0 no pattern check is performed
* @maxblocks: maximum number of blocks to search for a bbt. This number of
- * blocks is reserved at the end of the device where the tables are
+ * blocks is reserved at the end of the device where the tables are
* written.
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
* bad) block in the stored bbt
- * @pattern: pattern to identify bad block table or factory marked good /
+ * @pattern: pattern to identify bad block table or factory marked good /
* bad blocks, can be NULL, if len = 0
*
- * Descriptor for the bad block table marker and the descriptor for the
+ * Descriptor for the bad block table marker and the descriptor for the
* pattern which identifies good and bad blocks. The assumption is made
* that the pattern and the version count are always located in the oob area
* of the first block.
diff --git a/include/nand.h b/include/nand.h
index 29580da..6dbaa42 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -24,7 +24,7 @@
#ifndef _NAND_H_
#define _NAND_H_
-#include <linux_compat.h>
+#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>