dts/upstream/Bindings/clock/sprd,ums512-clk.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UMS512 Soc clock controller

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  compatible:
    enum:
      - sprd,ums512-apahb-gate
      - sprd,ums512-ap-clk
      - sprd,ums512-aonapb-clk
      - sprd,ums512-pmu-gate
      - sprd,ums512-g0-pll
      - sprd,ums512-g2-pll
      - sprd,ums512-g3-pll
      - sprd,ums512-gc-pll
      - sprd,ums512-aon-gate
      - sprd,ums512-audcpapb-gate
      - sprd,ums512-audcpahb-gate
      - sprd,ums512-gpu-clk
      - sprd,ums512-mm-clk
      - sprd,ums512-mm-gate-clk
      - sprd,ums512-apapb-gate

  "#clock-cells":
    const: 1

  clocks:
    minItems: 1
    maxItems: 4
    description: |
      The input parent clock(s) phandle for the clock, only list
      fixed clocks which are declared in devicetree.

  clock-names:
    minItems: 1
    items:
      - const: ext-26m
      - const: ext-32k
      - const: ext-4m
      - const: rco-100m

  reg:
    maxItems: 1

required:
  - compatible
  - '#clock-cells'
  - reg

additionalProperties: false

examples:
  - |
    ap_clk: clock-controller@20200000 {
      compatible = "sprd,ums512-ap-clk";
      reg = <0x20200000 0x1000>;
      clocks = <&ext_26m>;
      clock-names = "ext-26m";
      #clock-cells = <1>;
    };
...