arch/arm/dts/imx8mm-icore-mx8mm.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 NXP
 * Copyright (c) 2019 Engicam srl
 * Copyright (c) 2020 Amarula Solutons(India)
 */

/ {
	compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
};

&A53_0 {
	cpu-supply = <&reg_buck4>;
};

&A53_1 {
	cpu-supply = <&reg_buck4>;
};

&A53_2 {
	cpu-supply = <&reg_buck4>;
};

&A53_3 {
	cpu-supply = <&reg_buck4>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@3 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <3>;
			reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@8 {
		compatible = "nxp,pf8121a";
		reg = <0x08>;

		regulators {
			reg_ldo1: ldo1 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <5000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_ldo2: ldo2 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <5000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_ldo3: ldo3 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <5000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_ldo4: ldo4 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <5000000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck1: buck1 {
				regulator-min-microvolt =  <400000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck2: buck2 {
				regulator-min-microvolt =  <400000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck3: buck3 {
				regulator-min-microvolt =  <400000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck4: buck4 {
				regulator-min-microvolt =  <400000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck5: buck5 {
				regulator-min-microvolt =  <400000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck6: buck6 {
				regulator-min-microvolt =  <400000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_buck7: buck7 {
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};

			reg_vsnvs: vsnvs {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7		0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
		>;
	};
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};