Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst
index 4b58567..8edbf04 100644
--- a/doc/board/google/chromebook_coral.rst
+++ b/doc/board/google/chromebook_coral.rst
@@ -250,7 +250,7 @@
known issue with Intel SoCs with modern DRAM and apparently cannot be improved.
The MRC caches are used to work around this.
-Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which
+Once SPL is finished it loads U-Boot into SDRAM at CONFIG_TEXT_BASE, which
is normally 1110000. Note that CAR is still active.
@@ -355,7 +355,7 @@
f0000 CONFIG_ROM_TABLE_ADDR
120000 BSS (defined in u-boot-spl.lds)
200000 FSP-S (which is run after U-Boot is relocated)
- 1110000 CONFIG_SYS_TEXT_BASE
+ 1110000 CONFIG_TEXT_BASE
Speeding up SPL for development
diff --git a/doc/board/google/chromebook_samus.rst b/doc/board/google/chromebook_samus.rst
index eab1128..822ba57 100644
--- a/doc/board/google/chromebook_samus.rst
+++ b/doc/board/google/chromebook_samus.rst
@@ -91,7 +91,7 @@
:fffd8000: TPL_TEXT_BASE
:fffa0000: X86_MRC_ADDR
:fff90000: VGA_BIOS_ADDR
- :ffed0000: SYS_TEXT_BASE
+ :ffed0000: TEXT_BASE
:ffea0000: X86_REFCODE_ADDR
:ffe70000: SPL_TEXT_BASE
:ffbf8000: CONFIG_ENV_OFFSET (environemnt offset)