Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().
Rename it to resolve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 3792f9e..4a5f101 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -26,7 +26,7 @@
$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
-f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
-Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
+Make sure 0x1110000 matches CONFIG_TEXT_BASE, which is the symbol address
of _x86boot_start (in arch/x86/cpu/start.S).
If you want to use ELF as the coreboot payload, change U-Boot configuration to
@@ -64,7 +64,7 @@
10000000 Memory reserved by coreboot for mapping PCI devices
(typical size 2151000, includes framebuffer)
1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup
- 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc)
+ 1110000 CONFIG_TEXT_BASE (start address of U-Boot code, before reloc)
110000 CONFIG_BLOBLIST_ADDR (before being relocated)
100000 CONFIG_PRE_CON_BUF_ADDR
f0000 ACPI tables set up by U-Boot
diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst
index 4b58567..8edbf04 100644
--- a/doc/board/google/chromebook_coral.rst
+++ b/doc/board/google/chromebook_coral.rst
@@ -250,7 +250,7 @@
known issue with Intel SoCs with modern DRAM and apparently cannot be improved.
The MRC caches are used to work around this.
-Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which
+Once SPL is finished it loads U-Boot into SDRAM at CONFIG_TEXT_BASE, which
is normally 1110000. Note that CAR is still active.
@@ -355,7 +355,7 @@
f0000 CONFIG_ROM_TABLE_ADDR
120000 BSS (defined in u-boot-spl.lds)
200000 FSP-S (which is run after U-Boot is relocated)
- 1110000 CONFIG_SYS_TEXT_BASE
+ 1110000 CONFIG_TEXT_BASE
Speeding up SPL for development
diff --git a/doc/board/google/chromebook_samus.rst b/doc/board/google/chromebook_samus.rst
index eab1128..822ba57 100644
--- a/doc/board/google/chromebook_samus.rst
+++ b/doc/board/google/chromebook_samus.rst
@@ -91,7 +91,7 @@
:fffd8000: TPL_TEXT_BASE
:fffa0000: X86_MRC_ADDR
:fff90000: VGA_BIOS_ADDR
- :ffed0000: SYS_TEXT_BASE
+ :ffed0000: TEXT_BASE
:ffea0000: X86_REFCODE_ADDR
:ffe70000: SPL_TEXT_BASE
:ffbf8000: CONFIG_ENV_OFFSET (environemnt offset)
diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst
index 0281217..1ba25b5 100644
--- a/doc/board/intel/minnowmax.rst
+++ b/doc/board/intel/minnowmax.rst
@@ -56,7 +56,7 @@
500000 <spare>
6ef000 Environment CONFIG_ENV_OFFSET
6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
-700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
+700000 u-boot-dtb.bin CONFIG_TEXT_BASE
7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
7c0000 fsp.bin CONFIG_FSP_ADDR
7f8000 <spare> (depends on size of fsp.bin)
diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst
index 18f1cc0..87d71a5 100644
--- a/doc/board/intel/slimbootloader.rst
+++ b/doc/board/intel/slimbootloader.rst
@@ -69,7 +69,7 @@
+GEN_CFG_DATA.PayloadId | 'U-BT'
2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot
- CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig.
+ CONFIG_TEXT_BASE in board/intel/slimbootloader/Kconfig.
PAYLOAD_LOAD_HIGH must be 0::
$ vi Platform/QemuBoardPkg/BoardConfig.py
@@ -122,7 +122,7 @@
2. Update payload text base.
-* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE
+* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_TEXT_BASE
in board/intel/slimbootloader/Kconfig.
* PAYLOAD_LOAD_HIGH must be 0::
diff --git a/doc/board/nxp/mx6ul_14x14_evk.rst b/doc/board/nxp/mx6ul_14x14_evk.rst
index 8298bf8..3e57ba1 100644
--- a/doc/board/nxp/mx6ul_14x14_evk.rst
+++ b/doc/board/nxp/mx6ul_14x14_evk.rst
@@ -74,9 +74,9 @@
SDPU: jump -addr 0x877fffc0
SDPU: done
-Please note that the address above is calculated based on SYS_TEXT_BASE address:
+Please note that the address above is calculated based on TEXT_BASE address:
-0x877fffc0 = 0x87800000 (SYS_TEXT_BASE) - 0x40 (U-Boot proper Header size)
+0x877fffc0 = 0x87800000 (TEXT_BASE) - 0x40 (U-Boot proper Header size)
Power on the target and run the following command from U-Boot root directory:
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
index 903f883..4568bb3 100644
--- a/doc/board/sipeed/maix.rst
+++ b/doc/board/sipeed/maix.rst
@@ -93,7 +93,7 @@
As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base.
Furthermore we have to enable building U-Boot for S-mode::
- CONFIG_SYS_TEXT_BASE=0x80020000
+ CONFIG_TEXT_BASE=0x80020000
CONFIG_RISCV_SMODE=y
Both settings are contained in sipeed_maix_smode_defconfig so we can build
@@ -115,7 +115,7 @@
FW_PAYLOAD_OFFSET=0x20000 \
FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin
-The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000.
+The value of FW_PAYLOAD_OFFSET must match CONFIG_TEXT_BASE - 0x80000000.
The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.