Merge patch series "airoha: Add initial support AN7581"
Christian Marangi <ansuelsmth@gmail.com> says:
This little series adds initial support for Airoha AN7581 SoC.
With the help of some backport patch, this use OF_UPSTREAM
directly.
Posting this to have the targer and the very basic driver.
Ethernet, SNAND and eMMC support is already ready downstream
and will be posted shortly after this gets approved.
Having the first driver ready permits to separately push
dedicate series for SNAND, eMMC and Ethrnet as they all depends
on basic support of clock and reset and nothing else.
Link: https://lore.kernel.org/r/20250314185941.27834-1-ansuelsmth@gmail.com
diff --git a/MAINTAINERS b/MAINTAINERS
index e2339ec..92d4a15 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -315,6 +315,7 @@
F: board/freescale/common/
F: common/spl/spl_imx_container.c
F: doc/imx/
+F: drivers/mailbox/imx-mailbox.c
F: drivers/serial/serial_mxc.c
F: include/imx_container.h
diff --git a/Makefile b/Makefile
index ea6ca42..6209968 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
diff --git a/README b/README
index 067c1ee..334bbcf 100644
--- a/README
+++ b/README
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0+
+ # SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000 - 2013
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfeeceb..3ed829e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1124,6 +1124,8 @@
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
+ select SYSRESET
+ select SYSRESET_PSCI
imply OF_UPSTREAM
imply CMD_DM
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 939869b..f7707ac 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -63,9 +63,12 @@
1: wfi
b 1b
+fel_stash_addr: // must immediately precede back_in_32:
+ .word 0x00000000 // receives fel_stash addr, by AA64 code above
+
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
- .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
+ .word 0xe51f000c // ldr r0, [pc, #-12] ; load fel_stash address
.word 0xe5901008 // ldr r1, [r0, #8]
.word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
@@ -77,6 +80,4 @@
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
.word 0xe12fff1e // bx lr ; return to FEL
-fel_stash_addr:
- .word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7323182..fcfff5b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,6 +113,7 @@
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
tegra30-microsoft-surface-rt.dtb \
+ tegra30-ouya.dtb \
tegra30-tec-ng.dtb \
tegra30-wexler-qc750.dtb \
tegra114-dalmore.dtb \
@@ -1112,7 +1113,8 @@
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
-dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
+dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
+ k3-am67a-r5-beagley-ai.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
index 740a24d..300e355 100644
--- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
@@ -27,11 +27,6 @@
};
};
-®_usb_otg_vbus {
- gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-};
-
&wdog1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
new file mode 100644
index 0000000..390e233
--- /dev/null
+++ b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+ /* Will be removed when SMEM parsing is updated */
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x40000000>,
+ <0x0 0x4a500000 0x0 0x00100000>;
+ };
+};
+
+&sdhc_1 {
+ sdhci-caps-mask = <0x0 0x04000000>;
+ sdhci-caps = <0x0 0x04000000>; /* SDHCI_CAN_VDD_180 */
+
+ /*
+ * This reset is needed to clear out the settings done by
+ * previous boot loader. Without this the SDHCI_RESET_ALL
+ * reset done sdhci_init() times out.
+ */
+ resets = <&gcc GCC_SDCC_BCR>;
+};
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 2bc5acb..52c9caf 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -177,6 +177,10 @@
bootph-all;
};
+&usb0_phy_ctrl {
+ bootph-all;
+};
+
&vcc_3v3_mmc {
bootph-all;
};
diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
index 640361e..325702e 100644
--- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
@@ -142,7 +142,21 @@
};
};
};
-#endif
+
+#include "k3-binman-capsule-r5.dtsi"
+
+&capsule_tiboot3 {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am62a7-r5-phycore-som-2gb.dtb PHYCORE_AM62AX_TIBOOT3
+ */
+ image-guid = "07CA7DD0-85FF-597E-A485-B2423D3AE6C1";
+ };
+};
+
+#endif /* CONFIG_TARGET_PHYCORE_AM62AX_R5 */
#ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53
@@ -306,6 +320,66 @@
description = "U-Boot for AM62Ax board";
};
+ som-no-rtc {
+ description = "k3-am6xx-phycore-disable-rtc";
+ type = "flat_dt";
+ compression = "none";
+ load = <0x8F000000>;
+ arch = "arm";
+ ti-secure {
+ content = <&am6xx_phycore_disable_rtc_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_rtc_dtbo: blob-ext {
+ filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
+ };
+ };
+
+ som-no-spi {
+ description = "k3-am6xx-phycore-disable-spi-nor";
+ type = "flat_dt";
+ compression = "none";
+ load = <0x8F001000>;
+ arch = "arm";
+ ti-secure {
+ content = <&am6xx_phycore_disable_spi_not_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_spi_not_dtbo: blob-ext {
+ filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
+ };
+ };
+
+ som-no-eth {
+ description = "k3-am6xx-phycore-disable-eth-phy";
+ type = "flat_dt";
+ compression = "none";
+ load = <0x8F002000>;
+ arch = "arm";
+ ti-secure {
+ content = <&am6xx_phycore_disable_eth_phy_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_eth_phy_dtbo: blob-ext {
+ filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
+ };
+ };
+
+ som-qspi {
+ description = "k3-am6xx-phycore-qspi-nor";
+ type = "flat_dt";
+ compression = "none";
+ load = <0x8F003000>;
+ arch = "arm";
+ ti-secure {
+ content = <&am6xx_phycore_disable_qspi_nor_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_qspi_nor_dtbo: blob-ext {
+ filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
+ };
+ };
+
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
@@ -330,7 +404,11 @@
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "uboot";
- loadables = "uboot";
+ loadables = "uboot",
+ "som-no-rtc",
+ "som-no-spi",
+ "som-no-eth",
+ "som-qspi";
fdt = "fdt-0";
};
};
@@ -451,4 +529,29 @@
};
};
};
+
+#include "k3-binman-capsule.dtsi"
+
+&capsule_tispl {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am62a7-phyboard-lyra-rdk.dtb PHYCORE_AM62AX_SPL
+ */
+ image-guid = "14F968A2-7C3A-50AD-9356-192F07AD2A9C";
+ };
+};
+
+&capsule_uboot {
+ efi-capsule {
+ /*
+ * The GUID is generated dynamically by taking a namespace UUID and hashing
+ * it with the board compatible and fw_image name:
+ * mkeficapsule guidgen k3-am62a7-phyboard-lyra-rdk.dtb PHYCORE_AM62AX_UBOOT
+ */
+ image-guid = "1F1148C5-2785-5E7C-9C58-C5B1EC0DC80C";
+ };
+};
-#endif
+
+#endif /* CONFIG_TARGET_PHYCORE_AM62AX_A53 */
diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
index 41692c8..5a52f3d 100644
--- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -239,6 +239,10 @@
bootph-all;
};
+&usb0_phy_ctrl {
+ bootph-all;
+};
+
&vcc_3v3_mmc {
bootph-all;
};
diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
new file mode 100644
index 0000000..6c52038
--- /dev/null
+++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common AM67A BeagleY-AI dts file for SPLs
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-binman.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &main_timer0;
+ };
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+};
+
+&dmsc {
+ bootph-pre-ram;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
+};
+
+&usbss0 {
+ bootph-pre-ram;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ bootph-pre-ram;
+};
+
+&usbss1 {
+ status = "disabled";
+};
+
+&usb1 {
+ status = "disabled";
+};
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_R5_BEAGLEY_AI)
+
+&binman {
+ tiboot3-j722s-hs-evm.bin {
+ filename = "tiboot3-j722s-hs-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+ <&combined_dm_cfg>, <&sysfw_inner_cert>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl>;
+ content-sysfw = <&ti_fs_enc>;
+ content-sysfw-data = <&combined_tifs_cfg>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert>;
+ content-dm-data = <&combined_dm_cfg>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c7a800>;
+ };
+
+ u_boot_spl: u-boot-spl {
+ no-expanded;
+ };
+
+ ti_fs_enc: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_tifs_cfg: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+
+ sysfw_inner_cert: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_dm_cfg: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
+&binman {
+ tiboot3-j722s-hs-fs-evm.bin {
+ filename = "tiboot3-j722s-hs-fs-evm.bin";
+ symlink = "tiboot3.bin";
+
+ ti-secure-rom {
+ content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+ <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+ combined;
+ dm-data;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <&u_boot_spl_fs>;
+ content-sysfw = <&ti_fs_enc_fs>;
+ content-sysfw-data = <&combined_tifs_cfg_fs>;
+ content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+ content-dm-data = <&combined_dm_cfg_fs>;
+ load = <0x43c00000>;
+ load-sysfw = <0x40000>;
+ load-sysfw-data = <0x67000>;
+ load-dm-data = <0x43c7a800>;
+ };
+
+ u_boot_spl_fs: u-boot-spl {
+ no-expanded;
+ };
+
+ ti_fs_enc_fs: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+
+ sysfw_inner_cert_fs: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+
+ combined_dm_cfg_fs: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+#endif /* CONFIG_TARGET_J722S_R5_BEAGLEY_AI */
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_A53_BEAGLEY_AI)
+
+#define SPL_BEAGLEY_AI_DTB "spl/dts/ti/k3-am67a-beagley-ai.dtb"
+#define BEAGLEY_AI_DTB "u-boot.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+
+ blob-ext {
+ filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ optional;
+ };
+ };
+
+ ti-spl {
+ insert-template = <&ti_spl_template>;
+
+ fit {
+ images {
+ dm {
+ ti-secure {
+ content = <&dm>;
+ keyfile = "custMpk.pem";
+ };
+
+ dm: ti-dm {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am67a-beagley-ai";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ ti-secure {
+ content = <&spl_beagley_ai_dtb>;
+ keyfile = "custMpk.pem";
+ };
+
+ spl_beagley_ai_dtb: blob-ext {
+ filename = "spl/dts/ti/k3-am67a-beagley-ai.dtb";
+ };
+
+ };
+
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am67a-beagley-ai";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+
+&binman {
+ u-boot {
+ insert-template = <&u_boot_template>;
+
+ fit {
+ images {
+ uboot {
+ description = "U-Boot for BeagleY-AI";
+ };
+
+ fdt-0 {
+ description = "k3-am67a-beagley-ai";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+
+ ti-secure {
+ content = <&beagley_ai_dtb>;
+ keyfile = "custMpk.pem";
+ };
+
+ beagley_ai_dtb: blob-ext {
+ filename = "u-boot.dtb";
+ };
+
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-k3-am67a-beagley-ai";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+
+ };
+ };
+ };
+};
+#endif /* CONFIG_TARGET_J722S_A53_BEAGLEY_AI */
diff --git a/arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi b/arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi
new file mode 100644
index 0000000..6949a3a
--- /dev/null
+++ b/arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi
@@ -0,0 +1,2801 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DDR Configuration file
+ * DDR: Kingston_B3221PM3BDGUI-U
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
+ *
+ * This file was generated with the Jacinto7_DDRSS_RegConfigTool, Revision: J722S - v0.0.1
+ * This file was generated on Tue Mar 12 2024 14:14:02 GMT+0800
+*/
+
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_0 25000000
+#define DDRSS_PLL_FREQUENCY_1 933000000
+#define DDRSS_PLL_FREQUENCY_2 933000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x0005B18F
+#define DDRSS_CTL_12_DATA 0x0038EF90
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000E94
+#define DDRSS_CTL_15_DATA 0x0005B18F
+#define DDRSS_CTL_16_DATA 0x0038EF90
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000E94
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00004B4B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x00000000
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000040C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_45_DATA 0x00000000
+#define DDRSS_CTL_46_DATA 0x05000804
+#define DDRSS_CTL_47_DATA 0x00000800
+#define DDRSS_CTL_48_DATA 0x09090004
+#define DDRSS_CTL_49_DATA 0x00000204
+#define DDRSS_CTL_50_DATA 0x007A0012
+#define DDRSS_CTL_51_DATA 0x09140054
+#define DDRSS_CTL_52_DATA 0x00003A26
+#define DDRSS_CTL_53_DATA 0x007A0012
+#define DDRSS_CTL_54_DATA 0x09140054
+#define DDRSS_CTL_55_DATA 0x09003A26
+#define DDRSS_CTL_56_DATA 0x000A0A09
+#define DDRSS_CTL_57_DATA 0x0400036D
+#define DDRSS_CTL_58_DATA 0x090F2005
+#define DDRSS_CTL_59_DATA 0x00001B13
+#define DDRSS_CTL_60_DATA 0x0E007FE6
+#define DDRSS_CTL_61_DATA 0x090F200F
+#define DDRSS_CTL_62_DATA 0x00001B13
+#define DDRSS_CTL_63_DATA 0x0E007FE6
+#define DDRSS_CTL_64_DATA 0x0304200F
+#define DDRSS_CTL_65_DATA 0x04050002
+#define DDRSS_CTL_66_DATA 0x24262426
+#define DDRSS_CTL_67_DATA 0x01010008
+#define DDRSS_CTL_68_DATA 0x044A4A08
+#define DDRSS_CTL_69_DATA 0x042B2B04
+#define DDRSS_CTL_70_DATA 0x00002B2B
+#define DDRSS_CTL_71_DATA 0x00000101
+#define DDRSS_CTL_72_DATA 0x00000000
+#define DDRSS_CTL_73_DATA 0x01000000
+#define DDRSS_CTL_74_DATA 0x00130803
+#define DDRSS_CTL_75_DATA 0x00000059
+#define DDRSS_CTL_76_DATA 0x000002C5
+#define DDRSS_CTL_77_DATA 0x00000E2E
+#define DDRSS_CTL_78_DATA 0x000002C5
+#define DDRSS_CTL_79_DATA 0x00000E2E
+#define DDRSS_CTL_80_DATA 0x00000005
+#define DDRSS_CTL_81_DATA 0x0000000A
+#define DDRSS_CTL_82_DATA 0x00000010
+#define DDRSS_CTL_83_DATA 0x00000163
+#define DDRSS_CTL_84_DATA 0x00000386
+#define DDRSS_CTL_85_DATA 0x00000163
+#define DDRSS_CTL_86_DATA 0x00000386
+#define DDRSS_CTL_87_DATA 0x03004000
+#define DDRSS_CTL_88_DATA 0x00001201
+#define DDRSS_CTL_89_DATA 0x000E0005
+#define DDRSS_CTL_90_DATA 0x2908000E
+#define DDRSS_CTL_91_DATA 0x0A050529
+#define DDRSS_CTL_92_DATA 0x1B0E0A03
+#define DDRSS_CTL_93_DATA 0x1B0E0A04
+#define DDRSS_CTL_94_DATA 0x04010104
+#define DDRSS_CTL_95_DATA 0x00010401
+#define DDRSS_CTL_96_DATA 0x00140014
+#define DDRSS_CTL_97_DATA 0x02D302D3
+#define DDRSS_CTL_98_DATA 0x02D302D3
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x03030000
+#define DDRSS_CTL_101_DATA 0x05050501
+#define DDRSS_CTL_102_DATA 0x04041C04
+#define DDRSS_CTL_103_DATA 0x0E0A0E0A
+#define DDRSS_CTL_104_DATA 0x0A04041C
+#define DDRSS_CTL_105_DATA 0x030E0A0E
+#define DDRSS_CTL_106_DATA 0x00000404
+#define DDRSS_CTL_107_DATA 0x00000301
+#define DDRSS_CTL_108_DATA 0x00000001
+#define DDRSS_CTL_109_DATA 0x00000000
+#define DDRSS_CTL_110_DATA 0x40020100
+#define DDRSS_CTL_111_DATA 0x00038010
+#define DDRSS_CTL_112_DATA 0x00050004
+#define DDRSS_CTL_113_DATA 0x00000004
+#define DDRSS_CTL_114_DATA 0x00040003
+#define DDRSS_CTL_115_DATA 0x00040005
+#define DDRSS_CTL_116_DATA 0x00030000
+#define DDRSS_CTL_117_DATA 0x00050004
+#define DDRSS_CTL_118_DATA 0x00000004
+#define DDRSS_CTL_119_DATA 0x00001640
+#define DDRSS_CTL_120_DATA 0x00001640
+#define DDRSS_CTL_121_DATA 0x00001640
+#define DDRSS_CTL_122_DATA 0x00001640
+#define DDRSS_CTL_123_DATA 0x00001640
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000026F
+#define DDRSS_CTL_126_DATA 0x00038B80
+#define DDRSS_CTL_127_DATA 0x00038B80
+#define DDRSS_CTL_128_DATA 0x00038B80
+#define DDRSS_CTL_129_DATA 0x00038B80
+#define DDRSS_CTL_130_DATA 0x00038B80
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00006342
+#define DDRSS_CTL_133_DATA 0x00038B80
+#define DDRSS_CTL_134_DATA 0x00038B80
+#define DDRSS_CTL_135_DATA 0x00038B80
+#define DDRSS_CTL_136_DATA 0x00038B80
+#define DDRSS_CTL_137_DATA 0x00038B80
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00006342
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000000
+#define DDRSS_CTL_157_DATA 0x00000000
+#define DDRSS_CTL_158_DATA 0x03050000
+#define DDRSS_CTL_159_DATA 0x040A040A
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x07010A09
+#define DDRSS_CTL_162_DATA 0x000E0A09
+#define DDRSS_CTL_163_DATA 0x010A0900
+#define DDRSS_CTL_164_DATA 0x0E0A0907
+#define DDRSS_CTL_165_DATA 0x0A090000
+#define DDRSS_CTL_166_DATA 0x0A090701
+#define DDRSS_CTL_167_DATA 0x0000000E
+#define DDRSS_CTL_168_DATA 0x00040003
+#define DDRSS_CTL_169_DATA 0x00000007
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x01000000
+#define DDRSS_CTL_177_DATA 0x00000000
+#define DDRSS_CTL_178_DATA 0x00001700
+#define DDRSS_CTL_179_DATA 0x0000100E
+#define DDRSS_CTL_180_DATA 0x00000002
+#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_182_DATA 0x00000001
+#define DDRSS_CTL_183_DATA 0x00000002
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00008000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00008000
+#define DDRSS_CTL_188_DATA 0x00000C00
+#define DDRSS_CTL_189_DATA 0x00008000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x0005000A
+#define DDRSS_CTL_196_DATA 0x0404000D
+#define DDRSS_CTL_197_DATA 0x0000000D
+#define DDRSS_CTL_198_DATA 0x00BB0176
+#define DDRSS_CTL_199_DATA 0x0E0E01D3
+#define DDRSS_CTL_200_DATA 0x000001D3
+#define DDRSS_CTL_201_DATA 0x00BB0176
+#define DDRSS_CTL_202_DATA 0x0E0E01D3
+#define DDRSS_CTL_203_DATA 0x000001D3
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000084
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x000000E4
+#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x000000E4
+#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000084
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x000000E4
+#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x000000E4
+#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000033
+#define DDRSS_CTL_228_DATA 0x00000033
+#define DDRSS_CTL_229_DATA 0x00000033
+#define DDRSS_CTL_230_DATA 0x00000033
+#define DDRSS_CTL_231_DATA 0x00000033
+#define DDRSS_CTL_232_DATA 0x00000033
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x35000000
+#define DDRSS_CTL_257_DATA 0x35353535
+#define DDRSS_CTL_258_DATA 0x00002735
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000027
+#define DDRSS_CTL_262_DATA 0x00000027
+#define DDRSS_CTL_263_DATA 0x00000027
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x0000000F
+#define DDRSS_CTL_270_DATA 0x0000000F
+#define DDRSS_CTL_271_DATA 0x0000000F
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00001600
+#define DDRSS_CTL_274_DATA 0x00000016
+#define DDRSS_CTL_275_DATA 0x00000016
+#define DDRSS_CTL_276_DATA 0x00000016
+#define DDRSS_CTL_277_DATA 0x00000016
+#define DDRSS_CTL_278_DATA 0x00000016
+#define DDRSS_CTL_279_DATA 0x00000020
+#define DDRSS_CTL_280_DATA 0x00010000
+#define DDRSS_CTL_281_DATA 0x00000100
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000101
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x00000000
+#define DDRSS_CTL_291_DATA 0x00000000
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x0C181511
+#define DDRSS_CTL_297_DATA 0x00000304
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00020000
+#define DDRSS_CTL_312_DATA 0x00400100
+#define DDRSS_CTL_313_DATA 0x00080032
+#define DDRSS_CTL_314_DATA 0x01000200
+#define DDRSS_CTL_315_DATA 0x074A0040
+#define DDRSS_CTL_316_DATA 0x00020038
+#define DDRSS_CTL_317_DATA 0x00400100
+#define DDRSS_CTL_318_DATA 0x0038074A
+#define DDRSS_CTL_319_DATA 0x00030000
+#define DDRSS_CTL_320_DATA 0x005E005E
+#define DDRSS_CTL_321_DATA 0x00000100
+#define DDRSS_CTL_322_DATA 0x01010000
+#define DDRSS_CTL_323_DATA 0x00000000
+#define DDRSS_CTL_324_DATA 0x3FFF0000
+#define DDRSS_CTL_325_DATA 0x000FFF00
+#define DDRSS_CTL_326_DATA 0xFFFFFFFF
+#define DDRSS_CTL_327_DATA 0x00FFFF00
+#define DDRSS_CTL_328_DATA 0x0B000000
+#define DDRSS_CTL_329_DATA 0x0001FFFF
+#define DDRSS_CTL_330_DATA 0x01010101
+#define DDRSS_CTL_331_DATA 0x01010101
+#define DDRSS_CTL_332_DATA 0x00000118
+#define DDRSS_CTL_333_DATA 0x00000C01
+#define DDRSS_CTL_334_DATA 0x00040100
+#define DDRSS_CTL_335_DATA 0x00040100
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x01030303
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00000000
+#define DDRSS_CTL_378_DATA 0x00000000
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x01000101
+#define DDRSS_CTL_384_DATA 0x01010001
+#define DDRSS_CTL_385_DATA 0x00010101
+#define DDRSS_CTL_386_DATA 0x01090903
+#define DDRSS_CTL_387_DATA 0x05020201
+#define DDRSS_CTL_388_DATA 0x0E081B1B
+#define DDRSS_CTL_389_DATA 0x0009040E
+#define DDRSS_CTL_390_DATA 0x0B0D040F
+#define DDRSS_CTL_391_DATA 0x0B0D0406
+#define DDRSS_CTL_392_DATA 0x0D0D0906
+#define DDRSS_CTL_393_DATA 0x01000000
+#define DDRSS_CTL_394_DATA 0x07030701
+#define DDRSS_CTL_395_DATA 0x04000103
+#define DDRSS_CTL_396_DATA 0x1B000004
+#define DDRSS_CTL_397_DATA 0x000000B2
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00000321
+#define DDRSS_CTL_403_DATA 0x000006F4
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_406_DATA 0x00001C5C
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00000200
+#define DDRSS_CTL_411_DATA 0x00007F9E
+#define DDRSS_CTL_412_DATA 0x00011B98
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x37200C09
+#define DDRSS_CTL_415_DATA 0x00001C5C
+#define DDRSS_CTL_416_DATA 0x00000200
+#define DDRSS_CTL_417_DATA 0x00000200
+#define DDRSS_CTL_418_DATA 0x00000200
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x00007F9E
+#define DDRSS_CTL_421_DATA 0x00011B98
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
+#define DDRSS_CTL_424_DATA 0x00000000
+#define DDRSS_CTL_425_DATA 0x02000A00
+#define DDRSS_CTL_426_DATA 0x00050003
+#define DDRSS_CTL_427_DATA 0x00010101
+#define DDRSS_CTL_428_DATA 0x00010101
+#define DDRSS_CTL_429_DATA 0x00010001
+#define DDRSS_CTL_430_DATA 0x00000101
+#define DDRSS_CTL_431_DATA 0x02000201
+#define DDRSS_CTL_432_DATA 0x02010000
+#define DDRSS_CTL_433_DATA 0x06000200
+#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00050001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x01010000
+#define DDRSS_PI_27_DATA 0x0A000100
+#define DDRSS_PI_28_DATA 0x00000028
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_30_DATA 0x00320000
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x00000000
+#define DDRSS_PI_36_DATA 0x00000000
+#define DDRSS_PI_37_DATA 0x00000001
+#define DDRSS_PI_38_DATA 0x000000AA
+#define DDRSS_PI_39_DATA 0x00000055
+#define DDRSS_PI_40_DATA 0x000000B5
+#define DDRSS_PI_41_DATA 0x0000004A
+#define DDRSS_PI_42_DATA 0x00000056
+#define DDRSS_PI_43_DATA 0x000000A9
+#define DDRSS_PI_44_DATA 0x000000A9
+#define DDRSS_PI_45_DATA 0x000000B5
+#define DDRSS_PI_46_DATA 0x00000000
+#define DDRSS_PI_47_DATA 0x00000000
+#define DDRSS_PI_48_DATA 0x00050500
+#define DDRSS_PI_49_DATA 0x0000001A
+#define DDRSS_PI_50_DATA 0x000007D0
+#define DDRSS_PI_51_DATA 0x00000300
+#define DDRSS_PI_52_DATA 0x00000000
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x01000000
+#define DDRSS_PI_55_DATA 0x00010101
+#define DDRSS_PI_56_DATA 0x01000000
+#define DDRSS_PI_57_DATA 0x03000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00001705
+#define DDRSS_PI_60_DATA 0x00000000
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x00000000
+#define DDRSS_PI_63_DATA 0x0A0A140A
+#define DDRSS_PI_64_DATA 0x10020101
+#define DDRSS_PI_65_DATA 0x01000210
+#define DDRSS_PI_66_DATA 0x05000404
+#define DDRSS_PI_67_DATA 0x00010001
+#define DDRSS_PI_68_DATA 0x0001000E
+#define DDRSS_PI_69_DATA 0x01010500
+#define DDRSS_PI_70_DATA 0x00010000
+#define DDRSS_PI_71_DATA 0x00000034
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x0000FFFF
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x00000000
+#define DDRSS_PI_77_DATA 0x00000000
+#define DDRSS_PI_78_DATA 0x00000000
+#define DDRSS_PI_79_DATA 0x01000000
+#define DDRSS_PI_80_DATA 0x00010001
+#define DDRSS_PI_81_DATA 0x02000008
+#define DDRSS_PI_82_DATA 0x01000200
+#define DDRSS_PI_83_DATA 0x00000100
+#define DDRSS_PI_84_DATA 0x02000100
+#define DDRSS_PI_85_DATA 0x02000200
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000000
+#define DDRSS_PI_92_DATA 0x00000000
+#define DDRSS_PI_93_DATA 0x00000000
+#define DDRSS_PI_94_DATA 0x00000000
+#define DDRSS_PI_95_DATA 0x00000000
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00000000
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x01000400
+#define DDRSS_PI_100_DATA 0x0E0D0F12
+#define DDRSS_PI_101_DATA 0x08111413
+#define DDRSS_PI_102_DATA 0x01000009
+#define DDRSS_PI_103_DATA 0x00000302
+#define DDRSS_PI_104_DATA 0x00000008
+#define DDRSS_PI_105_DATA 0x08000000
+#define DDRSS_PI_106_DATA 0x00000100
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x0000AA00
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00010000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000008
+#define DDRSS_PI_137_DATA 0x00000000
+#define DDRSS_PI_138_DATA 0x00000000
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x00000000
+#define DDRSS_PI_145_DATA 0x00010000
+#define DDRSS_PI_146_DATA 0x00000000
+#define DDRSS_PI_147_DATA 0x00000000
+#define DDRSS_PI_148_DATA 0x0000000A
+#define DDRSS_PI_149_DATA 0x000186A0
+#define DDRSS_PI_150_DATA 0x00000100
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00000000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x01000000
+#define DDRSS_PI_157_DATA 0x00010003
+#define DDRSS_PI_158_DATA 0x02000101
+#define DDRSS_PI_159_DATA 0x01030001
+#define DDRSS_PI_160_DATA 0x00010400
+#define DDRSS_PI_161_DATA 0x06000105
+#define DDRSS_PI_162_DATA 0x01070001
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000000
+#define DDRSS_PI_165_DATA 0x00000000
+#define DDRSS_PI_166_DATA 0x00010001
+#define DDRSS_PI_167_DATA 0x00000000
+#define DDRSS_PI_168_DATA 0x00000000
+#define DDRSS_PI_169_DATA 0x00000000
+#define DDRSS_PI_170_DATA 0x00000000
+#define DDRSS_PI_171_DATA 0x00010000
+#define DDRSS_PI_172_DATA 0x00000004
+#define DDRSS_PI_173_DATA 0x00000000
+#define DDRSS_PI_174_DATA 0x00010000
+#define DDRSS_PI_175_DATA 0x00000000
+#define DDRSS_PI_176_DATA 0x00080000
+#define DDRSS_PI_177_DATA 0x01180118
+#define DDRSS_PI_178_DATA 0x00262601
+#define DDRSS_PI_179_DATA 0x00000034
+#define DDRSS_PI_180_DATA 0x0000005E
+#define DDRSS_PI_181_DATA 0x0002005E
+#define DDRSS_PI_182_DATA 0x02000200
+#define DDRSS_PI_183_DATA 0x00000004
+#define DDRSS_PI_184_DATA 0x0000100C
+#define DDRSS_PI_185_DATA 0x00104000
+#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_187_DATA 0x00000013
+#define DDRSS_PI_188_DATA 0x00000059
+#define DDRSS_PI_189_DATA 0x000002C5
+#define DDRSS_PI_190_DATA 0x00000E2E
+#define DDRSS_PI_191_DATA 0x000002C5
+#define DDRSS_PI_192_DATA 0x04000E2E
+#define DDRSS_PI_193_DATA 0x01010404
+#define DDRSS_PI_194_DATA 0x00001501
+#define DDRSS_PI_195_DATA 0x00270027
+#define DDRSS_PI_196_DATA 0x01000100
+#define DDRSS_PI_197_DATA 0x00000100
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x05090903
+#define DDRSS_PI_200_DATA 0x01011B1B
+#define DDRSS_PI_201_DATA 0x01010101
+#define DDRSS_PI_202_DATA 0x000C0C0A
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x04000000
+#define DDRSS_PI_206_DATA 0x0C021212
+#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_208_DATA 0x00090031
+#define DDRSS_PI_209_DATA 0x001B0043
+#define DDRSS_PI_210_DATA 0x001B0043
+#define DDRSS_PI_211_DATA 0x01010101
+#define DDRSS_PI_212_DATA 0x0003000D
+#define DDRSS_PI_213_DATA 0x000301D3
+#define DDRSS_PI_214_DATA 0x010001D3
+#define DDRSS_PI_215_DATA 0x000E000E
+#define DDRSS_PI_216_DATA 0x01D40100
+#define DDRSS_PI_217_DATA 0x010001D4
+#define DDRSS_PI_218_DATA 0x01D401D4
+#define DDRSS_PI_219_DATA 0x32103200
+#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_221_DATA 0x0A070601
+#define DDRSS_PI_222_DATA 0x1C11090D
+#define DDRSS_PI_223_DATA 0x1C110913
+#define DDRSS_PI_224_DATA 0x000C0013
+#define DDRSS_PI_225_DATA 0x00001000
+#define DDRSS_PI_226_DATA 0x00000C00
+#define DDRSS_PI_227_DATA 0x00001000
+#define DDRSS_PI_228_DATA 0x00000C00
+#define DDRSS_PI_229_DATA 0x02001000
+#define DDRSS_PI_230_DATA 0x0021000D
+#define DDRSS_PI_231_DATA 0x002101D3
+#define DDRSS_PI_232_DATA 0x000001D3
+#define DDRSS_PI_233_DATA 0x00001900
+#define DDRSS_PI_234_DATA 0x32000056
+#define DDRSS_PI_235_DATA 0x06000301
+#define DDRSS_PI_236_DATA 0x00300204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x17000301
+#define DDRSS_PI_239_DATA 0x00300C12
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x17000301
+#define DDRSS_PI_242_DATA 0x00000C12
+#define DDRSS_PI_243_DATA 0x05040900
+#define DDRSS_PI_244_DATA 0x00040900
+#define DDRSS_PI_245_DATA 0x00000315
+#define DDRSS_PI_246_DATA 0x20010004
+#define DDRSS_PI_247_DATA 0x0A0A0A03
+#define DDRSS_PI_248_DATA 0x2B0F0000
+#define DDRSS_PI_249_DATA 0x24140026
+#define DDRSS_PI_250_DATA 0x0000731B
+#define DDRSS_PI_251_DATA 0x20070054
+#define DDRSS_PI_252_DATA 0x1B131B1C
+#define DDRSS_PI_253_DATA 0x2B0F0000
+#define DDRSS_PI_254_DATA 0x24140026
+#define DDRSS_PI_255_DATA 0x0000731B
+#define DDRSS_PI_256_DATA 0x20070054
+#define DDRSS_PI_257_DATA 0x1B131B1C
+#define DDRSS_PI_258_DATA 0x00000000
+#define DDRSS_PI_259_DATA 0x000000B2
+#define DDRSS_PI_260_DATA 0x000006F4
+#define DDRSS_PI_261_DATA 0x00001C5C
+#define DDRSS_PI_262_DATA 0x00011B98
+#define DDRSS_PI_263_DATA 0x00001C5C
+#define DDRSS_PI_264_DATA 0x00011B98
+#define DDRSS_PI_265_DATA 0x02D30014
+#define DDRSS_PI_266_DATA 0x030302D3
+#define DDRSS_PI_267_DATA 0x00000003
+#define DDRSS_PI_268_DATA 0x00000000
+#define DDRSS_PI_269_DATA 0x0A040503
+#define DDRSS_PI_270_DATA 0x00000A04
+#define DDRSS_PI_271_DATA 0x00002710
+#define DDRSS_PI_272_DATA 0x000186A0
+#define DDRSS_PI_273_DATA 0x00000005
+#define DDRSS_PI_274_DATA 0x00000064
+#define DDRSS_PI_275_DATA 0x00000014
+#define DDRSS_PI_276_DATA 0x0005B18F
+#define DDRSS_PI_277_DATA 0x000186A0
+#define DDRSS_PI_278_DATA 0x00000005
+#define DDRSS_PI_279_DATA 0x00000E94
+#define DDRSS_PI_280_DATA 0x000002D3
+#define DDRSS_PI_281_DATA 0x0005B18F
+#define DDRSS_PI_282_DATA 0x000186A0
+#define DDRSS_PI_283_DATA 0x00000005
+#define DDRSS_PI_284_DATA 0x00000E94
+#define DDRSS_PI_285_DATA 0x010002D3
+#define DDRSS_PI_286_DATA 0x00320040
+#define DDRSS_PI_287_DATA 0x00010008
+#define DDRSS_PI_288_DATA 0x074A0040
+#define DDRSS_PI_289_DATA 0x00010038
+#define DDRSS_PI_290_DATA 0x074A0040
+#define DDRSS_PI_291_DATA 0x00000338
+#define DDRSS_PI_292_DATA 0x0028005D
+#define DDRSS_PI_293_DATA 0x03040404
+#define DDRSS_PI_294_DATA 0x00000303
+#define DDRSS_PI_295_DATA 0x01010000
+#define DDRSS_PI_296_DATA 0x04040202
+#define DDRSS_PI_297_DATA 0x67670808
+#define DDRSS_PI_298_DATA 0x67676767
+#define DDRSS_PI_299_DATA 0x67676767
+#define DDRSS_PI_300_DATA 0x67676767
+#define DDRSS_PI_301_DATA 0x00006767
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x55000000
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x3C00005A
+#define DDRSS_PI_309_DATA 0x00005500
+#define DDRSS_PI_310_DATA 0x00005A00
+#define DDRSS_PI_311_DATA 0x0055003C
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x3C00005A
+#define DDRSS_PI_314_DATA 0x00005500
+#define DDRSS_PI_315_DATA 0x00005A00
+#define DDRSS_PI_316_DATA 0x1716153C
+#define DDRSS_PI_317_DATA 0x13100A18
+#define DDRSS_PI_318_DATA 0x06050414
+#define DDRSS_PI_319_DATA 0x02010007
+#define DDRSS_PI_320_DATA 0x00000003
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x01000000
+#define DDRSS_PI_324_DATA 0x04020201
+#define DDRSS_PI_325_DATA 0x00080804
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000084
+#define DDRSS_PI_330_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x00000033
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x35000000
+#define DDRSS_PI_335_DATA 0x20160F27
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x000000E4
+#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_339_DATA 0x00000033
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x35000000
+#define DDRSS_PI_343_DATA 0x20160F27
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PI_345_DATA 0x000000E4
+#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_347_DATA 0x00000033
+#define DDRSS_PI_348_DATA 0x00000000
+#define DDRSS_PI_349_DATA 0x00000000
+#define DDRSS_PI_350_DATA 0x35000000
+#define DDRSS_PI_351_DATA 0x20160F27
+#define DDRSS_PI_352_DATA 0x00000000
+#define DDRSS_PI_353_DATA 0x00000084
+#define DDRSS_PI_354_DATA 0x00000000
+#define DDRSS_PI_355_DATA 0x00000033
+#define DDRSS_PI_356_DATA 0x00000000
+#define DDRSS_PI_357_DATA 0x00000000
+#define DDRSS_PI_358_DATA 0x35000000
+#define DDRSS_PI_359_DATA 0x20160F27
+#define DDRSS_PI_360_DATA 0x00000000
+#define DDRSS_PI_361_DATA 0x000000E4
+#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_363_DATA 0x00000033
+#define DDRSS_PI_364_DATA 0x00000000
+#define DDRSS_PI_365_DATA 0x00000000
+#define DDRSS_PI_366_DATA 0x35000000
+#define DDRSS_PI_367_DATA 0x20160F27
+#define DDRSS_PI_368_DATA 0x00000000
+#define DDRSS_PI_369_DATA 0x000000E4
+#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_371_DATA 0x00000033
+#define DDRSS_PI_372_DATA 0x00000000
+#define DDRSS_PI_373_DATA 0x00000000
+#define DDRSS_PI_374_DATA 0x35000000
+#define DDRSS_PI_375_DATA 0x20160F27
+#define DDRSS_PI_376_DATA 0x00000000
+#define DDRSS_PI_377_DATA 0x00000084
+#define DDRSS_PI_378_DATA 0x00000000
+#define DDRSS_PI_379_DATA 0x00000033
+#define DDRSS_PI_380_DATA 0x00000000
+#define DDRSS_PI_381_DATA 0x00000000
+#define DDRSS_PI_382_DATA 0x35000000
+#define DDRSS_PI_383_DATA 0x20160F27
+#define DDRSS_PI_384_DATA 0x00000000
+#define DDRSS_PI_385_DATA 0x000000E4
+#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_387_DATA 0x00000033
+#define DDRSS_PI_388_DATA 0x00000000
+#define DDRSS_PI_389_DATA 0x00000000
+#define DDRSS_PI_390_DATA 0x35000000
+#define DDRSS_PI_391_DATA 0x20160F27
+#define DDRSS_PI_392_DATA 0x00000000
+#define DDRSS_PI_393_DATA 0x000000E4
+#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_395_DATA 0x00000033
+#define DDRSS_PI_396_DATA 0x00000000
+#define DDRSS_PI_397_DATA 0x00000000
+#define DDRSS_PI_398_DATA 0x35000000
+#define DDRSS_PI_399_DATA 0x20160F27
+#define DDRSS_PI_400_DATA 0x00000000
+#define DDRSS_PI_401_DATA 0x00000084
+#define DDRSS_PI_402_DATA 0x00000000
+#define DDRSS_PI_403_DATA 0x00000033
+#define DDRSS_PI_404_DATA 0x00000000
+#define DDRSS_PI_405_DATA 0x00000000
+#define DDRSS_PI_406_DATA 0x35000000
+#define DDRSS_PI_407_DATA 0x20160F27
+#define DDRSS_PI_408_DATA 0x00000000
+#define DDRSS_PI_409_DATA 0x000000E4
+#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_411_DATA 0x00000033
+#define DDRSS_PI_412_DATA 0x00000000
+#define DDRSS_PI_413_DATA 0x00000000
+#define DDRSS_PI_414_DATA 0x35000000
+#define DDRSS_PI_415_DATA 0x20160F27
+#define DDRSS_PI_416_DATA 0x00000000
+#define DDRSS_PI_417_DATA 0x000000E4
+#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_419_DATA 0x00000033
+#define DDRSS_PI_420_DATA 0x00000000
+#define DDRSS_PI_421_DATA 0x00000000
+#define DDRSS_PI_422_DATA 0x35000000
+#define DDRSS_PI_423_DATA 0x20160F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01030000
+#define DDRSS_PHY_6_DATA 0x00010000
+#define DDRSS_PHY_7_DATA 0x01030004
+#define DDRSS_PHY_8_DATA 0x01000000
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x00000000
+#define DDRSS_PHY_12_DATA 0x01010000
+#define DDRSS_PHY_13_DATA 0x00010000
+#define DDRSS_PHY_14_DATA 0x00C00001
+#define DDRSS_PHY_15_DATA 0x00CC0008
+#define DDRSS_PHY_16_DATA 0x00660601
+#define DDRSS_PHY_17_DATA 0x00000003
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x00000301
+#define DDRSS_PHY_20_DATA 0x0000AAAA
+#define DDRSS_PHY_21_DATA 0x00005555
+#define DDRSS_PHY_22_DATA 0x0000B5B5
+#define DDRSS_PHY_23_DATA 0x00004A4A
+#define DDRSS_PHY_24_DATA 0x00005656
+#define DDRSS_PHY_25_DATA 0x0000A9A9
+#define DDRSS_PHY_26_DATA 0x0000B7B7
+#define DDRSS_PHY_27_DATA 0x00004848
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x00000000
+#define DDRSS_PHY_30_DATA 0x08000000
+#define DDRSS_PHY_31_DATA 0x0F000008
+#define DDRSS_PHY_32_DATA 0x00000F0F
+#define DDRSS_PHY_33_DATA 0x00E4E400
+#define DDRSS_PHY_34_DATA 0x00071040
+#define DDRSS_PHY_35_DATA 0x000C0020
+#define DDRSS_PHY_36_DATA 0x00062000
+#define DDRSS_PHY_37_DATA 0x00000000
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x55555555
+#define DDRSS_PHY_41_DATA 0xAAAAAAAA
+#define DDRSS_PHY_42_DATA 0x00005555
+#define DDRSS_PHY_43_DATA 0x01000100
+#define DDRSS_PHY_44_DATA 0x00800180
+#define DDRSS_PHY_45_DATA 0x00000001
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x081F07FF
+#define DDRSS_PHY_75_DATA 0x10200080
+#define DDRSS_PHY_76_DATA 0x00000008
+#define DDRSS_PHY_77_DATA 0x00000401
+#define DDRSS_PHY_78_DATA 0x00000000
+#define DDRSS_PHY_79_DATA 0x01CC0C01
+#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_81_DATA 0x20000140
+#define DDRSS_PHY_82_DATA 0x07FF0200
+#define DDRSS_PHY_83_DATA 0x0000DD01
+#define DDRSS_PHY_84_DATA 0x00100303
+#define DDRSS_PHY_85_DATA 0x00000000
+#define DDRSS_PHY_86_DATA 0x00000000
+#define DDRSS_PHY_87_DATA 0x00041000
+#define DDRSS_PHY_88_DATA 0x00100010
+#define DDRSS_PHY_89_DATA 0x00100010
+#define DDRSS_PHY_90_DATA 0x00100010
+#define DDRSS_PHY_91_DATA 0x00100010
+#define DDRSS_PHY_92_DATA 0x02000010
+#define DDRSS_PHY_93_DATA 0x00000005
+#define DDRSS_PHY_94_DATA 0x51516042
+#define DDRSS_PHY_95_DATA 0x31C06000
+#define DDRSS_PHY_96_DATA 0x07AB0340
+#define DDRSS_PHY_97_DATA 0x00C0C001
+#define DDRSS_PHY_98_DATA 0x0D000000
+#define DDRSS_PHY_99_DATA 0x000D0C0C
+#define DDRSS_PHY_100_DATA 0x42100010
+#define DDRSS_PHY_101_DATA 0x010C073E
+#define DDRSS_PHY_102_DATA 0x000F0C32
+#define DDRSS_PHY_103_DATA 0x01000140
+#define DDRSS_PHY_104_DATA 0x011E0120
+#define DDRSS_PHY_105_DATA 0x00000C00
+#define DDRSS_PHY_106_DATA 0x000002DD
+#define DDRSS_PHY_107_DATA 0x00030200
+#define DDRSS_PHY_108_DATA 0x02800000
+#define DDRSS_PHY_109_DATA 0x80800000
+#define DDRSS_PHY_110_DATA 0x000D2010
+#define DDRSS_PHY_111_DATA 0x76543210
+#define DDRSS_PHY_112_DATA 0x00000008
+#define DDRSS_PHY_113_DATA 0x045D045D
+#define DDRSS_PHY_114_DATA 0x045D045D
+#define DDRSS_PHY_115_DATA 0x045D045D
+#define DDRSS_PHY_116_DATA 0x045D045D
+#define DDRSS_PHY_117_DATA 0x0000045D
+#define DDRSS_PHY_118_DATA 0x0000A000
+#define DDRSS_PHY_119_DATA 0x00A000A0
+#define DDRSS_PHY_120_DATA 0x00A000A0
+#define DDRSS_PHY_121_DATA 0x00A000A0
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00B200A0
+#define DDRSS_PHY_128_DATA 0x01000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00080200
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x20202020
+#define DDRSS_PHY_134_DATA 0x20202020
+#define DDRSS_PHY_135_DATA 0xF0F02020
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x00000000
+#define DDRSS_PHY_268_DATA 0x01010000
+#define DDRSS_PHY_269_DATA 0x00010000
+#define DDRSS_PHY_270_DATA 0x00C00001
+#define DDRSS_PHY_271_DATA 0x00CC0008
+#define DDRSS_PHY_272_DATA 0x00660601
+#define DDRSS_PHY_273_DATA 0x00000003
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x00000301
+#define DDRSS_PHY_276_DATA 0x0000AAAA
+#define DDRSS_PHY_277_DATA 0x00005555
+#define DDRSS_PHY_278_DATA 0x0000B5B5
+#define DDRSS_PHY_279_DATA 0x00004A4A
+#define DDRSS_PHY_280_DATA 0x00005656
+#define DDRSS_PHY_281_DATA 0x0000A9A9
+#define DDRSS_PHY_282_DATA 0x0000B7B7
+#define DDRSS_PHY_283_DATA 0x00004848
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x00000000
+#define DDRSS_PHY_286_DATA 0x08000000
+#define DDRSS_PHY_287_DATA 0x0F000008
+#define DDRSS_PHY_288_DATA 0x00000F0F
+#define DDRSS_PHY_289_DATA 0x00E4E400
+#define DDRSS_PHY_290_DATA 0x00071040
+#define DDRSS_PHY_291_DATA 0x000C0020
+#define DDRSS_PHY_292_DATA 0x00062000
+#define DDRSS_PHY_293_DATA 0x00000000
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x55555555
+#define DDRSS_PHY_297_DATA 0xAAAAAAAA
+#define DDRSS_PHY_298_DATA 0x00005555
+#define DDRSS_PHY_299_DATA 0x01000100
+#define DDRSS_PHY_300_DATA 0x00800180
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x081F07FF
+#define DDRSS_PHY_331_DATA 0x10200080
+#define DDRSS_PHY_332_DATA 0x00000008
+#define DDRSS_PHY_333_DATA 0x00000401
+#define DDRSS_PHY_334_DATA 0x00000000
+#define DDRSS_PHY_335_DATA 0x01CC0C01
+#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_337_DATA 0x20000140
+#define DDRSS_PHY_338_DATA 0x07FF0200
+#define DDRSS_PHY_339_DATA 0x0000DD01
+#define DDRSS_PHY_340_DATA 0x00100303
+#define DDRSS_PHY_341_DATA 0x00000000
+#define DDRSS_PHY_342_DATA 0x00000000
+#define DDRSS_PHY_343_DATA 0x00041000
+#define DDRSS_PHY_344_DATA 0x00100010
+#define DDRSS_PHY_345_DATA 0x00100010
+#define DDRSS_PHY_346_DATA 0x00100010
+#define DDRSS_PHY_347_DATA 0x00100010
+#define DDRSS_PHY_348_DATA 0x02000010
+#define DDRSS_PHY_349_DATA 0x00000005
+#define DDRSS_PHY_350_DATA 0x51516042
+#define DDRSS_PHY_351_DATA 0x31C06000
+#define DDRSS_PHY_352_DATA 0x07AB0340
+#define DDRSS_PHY_353_DATA 0x00C0C001
+#define DDRSS_PHY_354_DATA 0x0D000000
+#define DDRSS_PHY_355_DATA 0x000D0C0C
+#define DDRSS_PHY_356_DATA 0x42100010
+#define DDRSS_PHY_357_DATA 0x010C073E
+#define DDRSS_PHY_358_DATA 0x000F0C32
+#define DDRSS_PHY_359_DATA 0x01000140
+#define DDRSS_PHY_360_DATA 0x011E0120
+#define DDRSS_PHY_361_DATA 0x00000C00
+#define DDRSS_PHY_362_DATA 0x000002DD
+#define DDRSS_PHY_363_DATA 0x00030200
+#define DDRSS_PHY_364_DATA 0x02800000
+#define DDRSS_PHY_365_DATA 0x80800000
+#define DDRSS_PHY_366_DATA 0x000D2010
+#define DDRSS_PHY_367_DATA 0x76543210
+#define DDRSS_PHY_368_DATA 0x00000008
+#define DDRSS_PHY_369_DATA 0x045D045D
+#define DDRSS_PHY_370_DATA 0x045D045D
+#define DDRSS_PHY_371_DATA 0x045D045D
+#define DDRSS_PHY_372_DATA 0x045D045D
+#define DDRSS_PHY_373_DATA 0x0000045D
+#define DDRSS_PHY_374_DATA 0x0000A000
+#define DDRSS_PHY_375_DATA 0x00A000A0
+#define DDRSS_PHY_376_DATA 0x00A000A0
+#define DDRSS_PHY_377_DATA 0x00A000A0
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00B200A0
+#define DDRSS_PHY_384_DATA 0x01000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00080200
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x20202020
+#define DDRSS_PHY_390_DATA 0x20202020
+#define DDRSS_PHY_391_DATA 0xF0F02020
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x04F00000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x01010000
+#define DDRSS_PHY_525_DATA 0x00010000
+#define DDRSS_PHY_526_DATA 0x00C00001
+#define DDRSS_PHY_527_DATA 0x00CC0008
+#define DDRSS_PHY_528_DATA 0x00660601
+#define DDRSS_PHY_529_DATA 0x00000003
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000301
+#define DDRSS_PHY_532_DATA 0x0000AAAA
+#define DDRSS_PHY_533_DATA 0x00005555
+#define DDRSS_PHY_534_DATA 0x0000B5B5
+#define DDRSS_PHY_535_DATA 0x00004A4A
+#define DDRSS_PHY_536_DATA 0x00005656
+#define DDRSS_PHY_537_DATA 0x0000A9A9
+#define DDRSS_PHY_538_DATA 0x0000B7B7
+#define DDRSS_PHY_539_DATA 0x00004848
+#define DDRSS_PHY_540_DATA 0x00000000
+#define DDRSS_PHY_541_DATA 0x00000000
+#define DDRSS_PHY_542_DATA 0x08000000
+#define DDRSS_PHY_543_DATA 0x0F000008
+#define DDRSS_PHY_544_DATA 0x00000F0F
+#define DDRSS_PHY_545_DATA 0x00E4E400
+#define DDRSS_PHY_546_DATA 0x00071040
+#define DDRSS_PHY_547_DATA 0x000C0020
+#define DDRSS_PHY_548_DATA 0x00062000
+#define DDRSS_PHY_549_DATA 0x00000000
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x55555555
+#define DDRSS_PHY_553_DATA 0xAAAAAAAA
+#define DDRSS_PHY_554_DATA 0x00005555
+#define DDRSS_PHY_555_DATA 0x01000100
+#define DDRSS_PHY_556_DATA 0x00800180
+#define DDRSS_PHY_557_DATA 0x00000001
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x081F07FF
+#define DDRSS_PHY_587_DATA 0x10200080
+#define DDRSS_PHY_588_DATA 0x00000008
+#define DDRSS_PHY_589_DATA 0x00000401
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x01CC0C01
+#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_593_DATA 0x20000140
+#define DDRSS_PHY_594_DATA 0x07FF0200
+#define DDRSS_PHY_595_DATA 0x0000DD01
+#define DDRSS_PHY_596_DATA 0x00100303
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00041000
+#define DDRSS_PHY_600_DATA 0x00100010
+#define DDRSS_PHY_601_DATA 0x00100010
+#define DDRSS_PHY_602_DATA 0x00100010
+#define DDRSS_PHY_603_DATA 0x00100010
+#define DDRSS_PHY_604_DATA 0x02000010
+#define DDRSS_PHY_605_DATA 0x00000005
+#define DDRSS_PHY_606_DATA 0x51516042
+#define DDRSS_PHY_607_DATA 0x31C06000
+#define DDRSS_PHY_608_DATA 0x07AB0340
+#define DDRSS_PHY_609_DATA 0x00C0C001
+#define DDRSS_PHY_610_DATA 0x0D000000
+#define DDRSS_PHY_611_DATA 0x000D0C0C
+#define DDRSS_PHY_612_DATA 0x42100010
+#define DDRSS_PHY_613_DATA 0x010C073E
+#define DDRSS_PHY_614_DATA 0x000F0C32
+#define DDRSS_PHY_615_DATA 0x01000140
+#define DDRSS_PHY_616_DATA 0x011E0120
+#define DDRSS_PHY_617_DATA 0x00000C00
+#define DDRSS_PHY_618_DATA 0x000002DD
+#define DDRSS_PHY_619_DATA 0x00030200
+#define DDRSS_PHY_620_DATA 0x02800000
+#define DDRSS_PHY_621_DATA 0x80800000
+#define DDRSS_PHY_622_DATA 0x000D2010
+#define DDRSS_PHY_623_DATA 0x76543210
+#define DDRSS_PHY_624_DATA 0x00000008
+#define DDRSS_PHY_625_DATA 0x045D045D
+#define DDRSS_PHY_626_DATA 0x045D045D
+#define DDRSS_PHY_627_DATA 0x045D045D
+#define DDRSS_PHY_628_DATA 0x045D045D
+#define DDRSS_PHY_629_DATA 0x0000045D
+#define DDRSS_PHY_630_DATA 0x0000A000
+#define DDRSS_PHY_631_DATA 0x00A000A0
+#define DDRSS_PHY_632_DATA 0x00A000A0
+#define DDRSS_PHY_633_DATA 0x00A000A0
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00B200A0
+#define DDRSS_PHY_640_DATA 0x01000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00080200
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x20202020
+#define DDRSS_PHY_646_DATA 0x20202020
+#define DDRSS_PHY_647_DATA 0xF0F02020
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x04F00000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x01010000
+#define DDRSS_PHY_781_DATA 0x00010000
+#define DDRSS_PHY_782_DATA 0x00C00001
+#define DDRSS_PHY_783_DATA 0x00CC0008
+#define DDRSS_PHY_784_DATA 0x00660601
+#define DDRSS_PHY_785_DATA 0x00000003
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000301
+#define DDRSS_PHY_788_DATA 0x0000AAAA
+#define DDRSS_PHY_789_DATA 0x00005555
+#define DDRSS_PHY_790_DATA 0x0000B5B5
+#define DDRSS_PHY_791_DATA 0x00004A4A
+#define DDRSS_PHY_792_DATA 0x00005656
+#define DDRSS_PHY_793_DATA 0x0000A9A9
+#define DDRSS_PHY_794_DATA 0x0000B7B7
+#define DDRSS_PHY_795_DATA 0x00004848
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x08000000
+#define DDRSS_PHY_799_DATA 0x0F000008
+#define DDRSS_PHY_800_DATA 0x00000F0F
+#define DDRSS_PHY_801_DATA 0x00E4E400
+#define DDRSS_PHY_802_DATA 0x00071040
+#define DDRSS_PHY_803_DATA 0x000C0020
+#define DDRSS_PHY_804_DATA 0x00062000
+#define DDRSS_PHY_805_DATA 0x00000000
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x55555555
+#define DDRSS_PHY_809_DATA 0xAAAAAAAA
+#define DDRSS_PHY_810_DATA 0x00005555
+#define DDRSS_PHY_811_DATA 0x01000100
+#define DDRSS_PHY_812_DATA 0x00800180
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x081F07FF
+#define DDRSS_PHY_843_DATA 0x10200080
+#define DDRSS_PHY_844_DATA 0x00000008
+#define DDRSS_PHY_845_DATA 0x00000401
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x01CC0C01
+#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_849_DATA 0x20000140
+#define DDRSS_PHY_850_DATA 0x07FF0200
+#define DDRSS_PHY_851_DATA 0x0000DD01
+#define DDRSS_PHY_852_DATA 0x00100303
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00041000
+#define DDRSS_PHY_856_DATA 0x00100010
+#define DDRSS_PHY_857_DATA 0x00100010
+#define DDRSS_PHY_858_DATA 0x00100010
+#define DDRSS_PHY_859_DATA 0x00100010
+#define DDRSS_PHY_860_DATA 0x02000010
+#define DDRSS_PHY_861_DATA 0x00000005
+#define DDRSS_PHY_862_DATA 0x51516042
+#define DDRSS_PHY_863_DATA 0x31C06000
+#define DDRSS_PHY_864_DATA 0x07AB0340
+#define DDRSS_PHY_865_DATA 0x00C0C001
+#define DDRSS_PHY_866_DATA 0x0D000000
+#define DDRSS_PHY_867_DATA 0x000D0C0C
+#define DDRSS_PHY_868_DATA 0x42100010
+#define DDRSS_PHY_869_DATA 0x010C073E
+#define DDRSS_PHY_870_DATA 0x000F0C32
+#define DDRSS_PHY_871_DATA 0x01000140
+#define DDRSS_PHY_872_DATA 0x011E0120
+#define DDRSS_PHY_873_DATA 0x00000C00
+#define DDRSS_PHY_874_DATA 0x000002DD
+#define DDRSS_PHY_875_DATA 0x00030200
+#define DDRSS_PHY_876_DATA 0x02800000
+#define DDRSS_PHY_877_DATA 0x80800000
+#define DDRSS_PHY_878_DATA 0x000D2010
+#define DDRSS_PHY_879_DATA 0x76543210
+#define DDRSS_PHY_880_DATA 0x00000008
+#define DDRSS_PHY_881_DATA 0x045D045D
+#define DDRSS_PHY_882_DATA 0x045D045D
+#define DDRSS_PHY_883_DATA 0x045D045D
+#define DDRSS_PHY_884_DATA 0x045D045D
+#define DDRSS_PHY_885_DATA 0x0000045D
+#define DDRSS_PHY_886_DATA 0x0000A000
+#define DDRSS_PHY_887_DATA 0x00A000A0
+#define DDRSS_PHY_888_DATA 0x00A000A0
+#define DDRSS_PHY_889_DATA 0x00A000A0
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00B200A0
+#define DDRSS_PHY_896_DATA 0x01000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00080200
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x20202020
+#define DDRSS_PHY_902_DATA 0x20202020
+#define DDRSS_PHY_903_DATA 0xF0F02020
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x0A418820
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x000405CC
+#define DDRSS_PHY_1062_DATA 0x03000004
+#define DDRSS_PHY_1063_DATA 0x00030000
+#define DDRSS_PHY_1064_DATA 0x00000300
+#define DDRSS_PHY_1065_DATA 0x00000300
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x42080010
+#define DDRSS_PHY_1069_DATA 0x0000803E
+#define DDRSS_PHY_1070_DATA 0x00000001
+#define DDRSS_PHY_1071_DATA 0x01000002
+#define DDRSS_PHY_1072_DATA 0x00008000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000000
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000100
+#define DDRSS_PHY_1286_DATA 0x00000200
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00400000
+#define DDRSS_PHY_1292_DATA 0x00000080
+#define DDRSS_PHY_1293_DATA 0x00DCBA98
+#define DDRSS_PHY_1294_DATA 0x03000000
+#define DDRSS_PHY_1295_DATA 0x00200000
+#define DDRSS_PHY_1296_DATA 0x00000000
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x00000000
+#define DDRSS_PHY_1300_DATA 0x00000000
+#define DDRSS_PHY_1301_DATA 0x0000002A
+#define DDRSS_PHY_1302_DATA 0x00000015
+#define DDRSS_PHY_1303_DATA 0x00000015
+#define DDRSS_PHY_1304_DATA 0x0000002A
+#define DDRSS_PHY_1305_DATA 0x00000033
+#define DDRSS_PHY_1306_DATA 0x0000000C
+#define DDRSS_PHY_1307_DATA 0x0000000C
+#define DDRSS_PHY_1308_DATA 0x00000033
+#define DDRSS_PHY_1309_DATA 0x0A418820
+#define DDRSS_PHY_1310_DATA 0x00000000
+#define DDRSS_PHY_1311_DATA 0x000F0000
+#define DDRSS_PHY_1312_DATA 0x20202003
+#define DDRSS_PHY_1313_DATA 0x00202020
+#define DDRSS_PHY_1314_DATA 0x20008008
+#define DDRSS_PHY_1315_DATA 0x00000810
+#define DDRSS_PHY_1316_DATA 0x00000F00
+#define DDRSS_PHY_1317_DATA 0x000405CC
+#define DDRSS_PHY_1318_DATA 0x03000004
+#define DDRSS_PHY_1319_DATA 0x00030000
+#define DDRSS_PHY_1320_DATA 0x00000300
+#define DDRSS_PHY_1321_DATA 0x00000300
+#define DDRSS_PHY_1322_DATA 0x00000300
+#define DDRSS_PHY_1323_DATA 0x00000300
+#define DDRSS_PHY_1324_DATA 0x42080010
+#define DDRSS_PHY_1325_DATA 0x0000803E
+#define DDRSS_PHY_1326_DATA 0x00000001
+#define DDRSS_PHY_1327_DATA 0x01000002
+#define DDRSS_PHY_1328_DATA 0x00008000
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000000
+#define DDRSS_PHY_1331_DATA 0x00000000
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x00000000
+#define DDRSS_PHY_1346_DATA 0x00000000
+#define DDRSS_PHY_1347_DATA 0x00000000
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00000000
+#define DDRSS_PHY_1375_DATA 0x00000000
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x00000000
+#define DDRSS_PHY_1383_DATA 0x00000000
+#define DDRSS_PHY_1384_DATA 0x00000000
+#define DDRSS_PHY_1385_DATA 0x00000000
+#define DDRSS_PHY_1386_DATA 0x00000000
+#define DDRSS_PHY_1387_DATA 0x00000000
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x00000000
+#define DDRSS_PHY_1394_DATA 0x00000000
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00000000
+#define DDRSS_PHY_1397_DATA 0x00000000
+#define DDRSS_PHY_1398_DATA 0x00000000
+#define DDRSS_PHY_1399_DATA 0x00000000
+#define DDRSS_PHY_1400_DATA 0x00000000
+#define DDRSS_PHY_1401_DATA 0x00000000
+#define DDRSS_PHY_1402_DATA 0x00000000
+#define DDRSS_PHY_1403_DATA 0x00000000
+#define DDRSS_PHY_1404_DATA 0x00000000
+#define DDRSS_PHY_1405_DATA 0x00000000
+#define DDRSS_PHY_1406_DATA 0x00000000
+#define DDRSS_PHY_1407_DATA 0x00000000
+#define DDRSS_PHY_1408_DATA 0x00000000
+#define DDRSS_PHY_1409_DATA 0x00000000
+#define DDRSS_PHY_1410_DATA 0x00000000
+#define DDRSS_PHY_1411_DATA 0x00000000
+#define DDRSS_PHY_1412_DATA 0x00000000
+#define DDRSS_PHY_1413_DATA 0x00000000
+#define DDRSS_PHY_1414_DATA 0x00000000
+#define DDRSS_PHY_1415_DATA 0x00000000
+#define DDRSS_PHY_1416_DATA 0x00000000
+#define DDRSS_PHY_1417_DATA 0x00000000
+#define DDRSS_PHY_1418_DATA 0x00000000
+#define DDRSS_PHY_1419_DATA 0x00000000
+#define DDRSS_PHY_1420_DATA 0x00000000
+#define DDRSS_PHY_1421_DATA 0x00000000
+#define DDRSS_PHY_1422_DATA 0x00000000
+#define DDRSS_PHY_1423_DATA 0x00000000
+#define DDRSS_PHY_1424_DATA 0x00000000
+#define DDRSS_PHY_1425_DATA 0x00000000
+#define DDRSS_PHY_1426_DATA 0x00000000
+#define DDRSS_PHY_1427_DATA 0x00000000
+#define DDRSS_PHY_1428_DATA 0x00000000
+#define DDRSS_PHY_1429_DATA 0x00000000
+#define DDRSS_PHY_1430_DATA 0x00000000
+#define DDRSS_PHY_1431_DATA 0x00000000
+#define DDRSS_PHY_1432_DATA 0x00000000
+#define DDRSS_PHY_1433_DATA 0x00000000
+#define DDRSS_PHY_1434_DATA 0x00000000
+#define DDRSS_PHY_1435_DATA 0x00000000
+#define DDRSS_PHY_1436_DATA 0x00000000
+#define DDRSS_PHY_1437_DATA 0x00000000
+#define DDRSS_PHY_1438_DATA 0x00000000
+#define DDRSS_PHY_1439_DATA 0x00000000
+#define DDRSS_PHY_1440_DATA 0x00000000
+#define DDRSS_PHY_1441_DATA 0x00000000
+#define DDRSS_PHY_1442_DATA 0x00000000
+#define DDRSS_PHY_1443_DATA 0x00000000
+#define DDRSS_PHY_1444_DATA 0x00000000
+#define DDRSS_PHY_1445_DATA 0x00000000
+#define DDRSS_PHY_1446_DATA 0x00000000
+#define DDRSS_PHY_1447_DATA 0x00000000
+#define DDRSS_PHY_1448_DATA 0x00000000
+#define DDRSS_PHY_1449_DATA 0x00000000
+#define DDRSS_PHY_1450_DATA 0x00000000
+#define DDRSS_PHY_1451_DATA 0x00000000
+#define DDRSS_PHY_1452_DATA 0x00000000
+#define DDRSS_PHY_1453_DATA 0x00000000
+#define DDRSS_PHY_1454_DATA 0x00000000
+#define DDRSS_PHY_1455_DATA 0x00000000
+#define DDRSS_PHY_1456_DATA 0x00000000
+#define DDRSS_PHY_1457_DATA 0x00000000
+#define DDRSS_PHY_1458_DATA 0x00000000
+#define DDRSS_PHY_1459_DATA 0x00000000
+#define DDRSS_PHY_1460_DATA 0x00000000
+#define DDRSS_PHY_1461_DATA 0x00000000
+#define DDRSS_PHY_1462_DATA 0x00000000
+#define DDRSS_PHY_1463_DATA 0x00000000
+#define DDRSS_PHY_1464_DATA 0x00000000
+#define DDRSS_PHY_1465_DATA 0x00000000
+#define DDRSS_PHY_1466_DATA 0x00000000
+#define DDRSS_PHY_1467_DATA 0x00000000
+#define DDRSS_PHY_1468_DATA 0x00000000
+#define DDRSS_PHY_1469_DATA 0x00000000
+#define DDRSS_PHY_1470_DATA 0x00000000
+#define DDRSS_PHY_1471_DATA 0x00000000
+#define DDRSS_PHY_1472_DATA 0x00000000
+#define DDRSS_PHY_1473_DATA 0x00000000
+#define DDRSS_PHY_1474_DATA 0x00000000
+#define DDRSS_PHY_1475_DATA 0x00000000
+#define DDRSS_PHY_1476_DATA 0x00000000
+#define DDRSS_PHY_1477_DATA 0x00000000
+#define DDRSS_PHY_1478_DATA 0x00000000
+#define DDRSS_PHY_1479_DATA 0x00000000
+#define DDRSS_PHY_1480_DATA 0x00000000
+#define DDRSS_PHY_1481_DATA 0x00000000
+#define DDRSS_PHY_1482_DATA 0x00000000
+#define DDRSS_PHY_1483_DATA 0x00000000
+#define DDRSS_PHY_1484_DATA 0x00000000
+#define DDRSS_PHY_1485_DATA 0x00000000
+#define DDRSS_PHY_1486_DATA 0x00000000
+#define DDRSS_PHY_1487_DATA 0x00000000
+#define DDRSS_PHY_1488_DATA 0x00000000
+#define DDRSS_PHY_1489_DATA 0x00000000
+#define DDRSS_PHY_1490_DATA 0x00000000
+#define DDRSS_PHY_1491_DATA 0x00000000
+#define DDRSS_PHY_1492_DATA 0x00000000
+#define DDRSS_PHY_1493_DATA 0x00000000
+#define DDRSS_PHY_1494_DATA 0x00000000
+#define DDRSS_PHY_1495_DATA 0x00000000
+#define DDRSS_PHY_1496_DATA 0x00000000
+#define DDRSS_PHY_1497_DATA 0x00000000
+#define DDRSS_PHY_1498_DATA 0x00000000
+#define DDRSS_PHY_1499_DATA 0x00000000
+#define DDRSS_PHY_1500_DATA 0x00000000
+#define DDRSS_PHY_1501_DATA 0x00000000
+#define DDRSS_PHY_1502_DATA 0x00000000
+#define DDRSS_PHY_1503_DATA 0x00000000
+#define DDRSS_PHY_1504_DATA 0x00000000
+#define DDRSS_PHY_1505_DATA 0x00000000
+#define DDRSS_PHY_1506_DATA 0x00000000
+#define DDRSS_PHY_1507_DATA 0x00000000
+#define DDRSS_PHY_1508_DATA 0x00000000
+#define DDRSS_PHY_1509_DATA 0x00000000
+#define DDRSS_PHY_1510_DATA 0x00000000
+#define DDRSS_PHY_1511_DATA 0x00000000
+#define DDRSS_PHY_1512_DATA 0x00000000
+#define DDRSS_PHY_1513_DATA 0x00000000
+#define DDRSS_PHY_1514_DATA 0x00000000
+#define DDRSS_PHY_1515_DATA 0x00000000
+#define DDRSS_PHY_1516_DATA 0x00000000
+#define DDRSS_PHY_1517_DATA 0x00000000
+#define DDRSS_PHY_1518_DATA 0x00000000
+#define DDRSS_PHY_1519_DATA 0x00000000
+#define DDRSS_PHY_1520_DATA 0x00000000
+#define DDRSS_PHY_1521_DATA 0x00000000
+#define DDRSS_PHY_1522_DATA 0x00000000
+#define DDRSS_PHY_1523_DATA 0x00000000
+#define DDRSS_PHY_1524_DATA 0x00000000
+#define DDRSS_PHY_1525_DATA 0x00000000
+#define DDRSS_PHY_1526_DATA 0x00000000
+#define DDRSS_PHY_1527_DATA 0x00000000
+#define DDRSS_PHY_1528_DATA 0x00000000
+#define DDRSS_PHY_1529_DATA 0x00000000
+#define DDRSS_PHY_1530_DATA 0x00000000
+#define DDRSS_PHY_1531_DATA 0x00000000
+#define DDRSS_PHY_1532_DATA 0x00000000
+#define DDRSS_PHY_1533_DATA 0x00000000
+#define DDRSS_PHY_1534_DATA 0x00000000
+#define DDRSS_PHY_1535_DATA 0x00000000
+#define DDRSS_PHY_1536_DATA 0x00000000
+#define DDRSS_PHY_1537_DATA 0x00000000
+#define DDRSS_PHY_1538_DATA 0x00000000
+#define DDRSS_PHY_1539_DATA 0x00000000
+#define DDRSS_PHY_1540_DATA 0x00000000
+#define DDRSS_PHY_1541_DATA 0x00000100
+#define DDRSS_PHY_1542_DATA 0x00000200
+#define DDRSS_PHY_1543_DATA 0x00000000
+#define DDRSS_PHY_1544_DATA 0x00000000
+#define DDRSS_PHY_1545_DATA 0x00000000
+#define DDRSS_PHY_1546_DATA 0x00000000
+#define DDRSS_PHY_1547_DATA 0x00400000
+#define DDRSS_PHY_1548_DATA 0x00000080
+#define DDRSS_PHY_1549_DATA 0x00DCBA98
+#define DDRSS_PHY_1550_DATA 0x03000000
+#define DDRSS_PHY_1551_DATA 0x00200000
+#define DDRSS_PHY_1552_DATA 0x00000000
+#define DDRSS_PHY_1553_DATA 0x00000000
+#define DDRSS_PHY_1554_DATA 0x00000000
+#define DDRSS_PHY_1555_DATA 0x00000000
+#define DDRSS_PHY_1556_DATA 0x00000000
+#define DDRSS_PHY_1557_DATA 0x0000002A
+#define DDRSS_PHY_1558_DATA 0x00000015
+#define DDRSS_PHY_1559_DATA 0x00000015
+#define DDRSS_PHY_1560_DATA 0x0000002A
+#define DDRSS_PHY_1561_DATA 0x00000033
+#define DDRSS_PHY_1562_DATA 0x0000000C
+#define DDRSS_PHY_1563_DATA 0x0000000C
+#define DDRSS_PHY_1564_DATA 0x00000033
+#define DDRSS_PHY_1565_DATA 0x0A418820
+#define DDRSS_PHY_1566_DATA 0x10000000
+#define DDRSS_PHY_1567_DATA 0x000F0000
+#define DDRSS_PHY_1568_DATA 0x20202003
+#define DDRSS_PHY_1569_DATA 0x00202020
+#define DDRSS_PHY_1570_DATA 0x20008008
+#define DDRSS_PHY_1571_DATA 0x00000810
+#define DDRSS_PHY_1572_DATA 0x00000F00
+#define DDRSS_PHY_1573_DATA 0x000405CC
+#define DDRSS_PHY_1574_DATA 0x03000004
+#define DDRSS_PHY_1575_DATA 0x00030000
+#define DDRSS_PHY_1576_DATA 0x00000300
+#define DDRSS_PHY_1577_DATA 0x00000300
+#define DDRSS_PHY_1578_DATA 0x00000300
+#define DDRSS_PHY_1579_DATA 0x00000300
+#define DDRSS_PHY_1580_DATA 0x42080010
+#define DDRSS_PHY_1581_DATA 0x0000803E
+#define DDRSS_PHY_1582_DATA 0x00000001
+#define DDRSS_PHY_1583_DATA 0x01000002
+#define DDRSS_PHY_1584_DATA 0x00008000
+#define DDRSS_PHY_1585_DATA 0x00000000
+#define DDRSS_PHY_1586_DATA 0x00000000
+#define DDRSS_PHY_1587_DATA 0x00000000
+#define DDRSS_PHY_1588_DATA 0x00000000
+#define DDRSS_PHY_1589_DATA 0x00000000
+#define DDRSS_PHY_1590_DATA 0x00000000
+#define DDRSS_PHY_1591_DATA 0x00000000
+#define DDRSS_PHY_1592_DATA 0x00000000
+#define DDRSS_PHY_1593_DATA 0x00000000
+#define DDRSS_PHY_1594_DATA 0x00000000
+#define DDRSS_PHY_1595_DATA 0x00000000
+#define DDRSS_PHY_1596_DATA 0x00000000
+#define DDRSS_PHY_1597_DATA 0x00000000
+#define DDRSS_PHY_1598_DATA 0x00000000
+#define DDRSS_PHY_1599_DATA 0x00000000
+#define DDRSS_PHY_1600_DATA 0x00000000
+#define DDRSS_PHY_1601_DATA 0x00000000
+#define DDRSS_PHY_1602_DATA 0x00000000
+#define DDRSS_PHY_1603_DATA 0x00000000
+#define DDRSS_PHY_1604_DATA 0x00000000
+#define DDRSS_PHY_1605_DATA 0x00000000
+#define DDRSS_PHY_1606_DATA 0x00000000
+#define DDRSS_PHY_1607_DATA 0x00000000
+#define DDRSS_PHY_1608_DATA 0x00000000
+#define DDRSS_PHY_1609_DATA 0x00000000
+#define DDRSS_PHY_1610_DATA 0x00000000
+#define DDRSS_PHY_1611_DATA 0x00000000
+#define DDRSS_PHY_1612_DATA 0x00000000
+#define DDRSS_PHY_1613_DATA 0x00000000
+#define DDRSS_PHY_1614_DATA 0x00000000
+#define DDRSS_PHY_1615_DATA 0x00000000
+#define DDRSS_PHY_1616_DATA 0x00000000
+#define DDRSS_PHY_1617_DATA 0x00000000
+#define DDRSS_PHY_1618_DATA 0x00000000
+#define DDRSS_PHY_1619_DATA 0x00000000
+#define DDRSS_PHY_1620_DATA 0x00000000
+#define DDRSS_PHY_1621_DATA 0x00000000
+#define DDRSS_PHY_1622_DATA 0x00000000
+#define DDRSS_PHY_1623_DATA 0x00000000
+#define DDRSS_PHY_1624_DATA 0x00000000
+#define DDRSS_PHY_1625_DATA 0x00000000
+#define DDRSS_PHY_1626_DATA 0x00000000
+#define DDRSS_PHY_1627_DATA 0x00000000
+#define DDRSS_PHY_1628_DATA 0x00000000
+#define DDRSS_PHY_1629_DATA 0x00000000
+#define DDRSS_PHY_1630_DATA 0x00000000
+#define DDRSS_PHY_1631_DATA 0x00000000
+#define DDRSS_PHY_1632_DATA 0x00000000
+#define DDRSS_PHY_1633_DATA 0x00000000
+#define DDRSS_PHY_1634_DATA 0x00000000
+#define DDRSS_PHY_1635_DATA 0x00000000
+#define DDRSS_PHY_1636_DATA 0x00000000
+#define DDRSS_PHY_1637_DATA 0x00000000
+#define DDRSS_PHY_1638_DATA 0x00000000
+#define DDRSS_PHY_1639_DATA 0x00000000
+#define DDRSS_PHY_1640_DATA 0x00000000
+#define DDRSS_PHY_1641_DATA 0x00000000
+#define DDRSS_PHY_1642_DATA 0x00000000
+#define DDRSS_PHY_1643_DATA 0x00000000
+#define DDRSS_PHY_1644_DATA 0x00000000
+#define DDRSS_PHY_1645_DATA 0x00000000
+#define DDRSS_PHY_1646_DATA 0x00000000
+#define DDRSS_PHY_1647_DATA 0x00000000
+#define DDRSS_PHY_1648_DATA 0x00000000
+#define DDRSS_PHY_1649_DATA 0x00000000
+#define DDRSS_PHY_1650_DATA 0x00000000
+#define DDRSS_PHY_1651_DATA 0x00000000
+#define DDRSS_PHY_1652_DATA 0x00000000
+#define DDRSS_PHY_1653_DATA 0x00000000
+#define DDRSS_PHY_1654_DATA 0x00000000
+#define DDRSS_PHY_1655_DATA 0x00000000
+#define DDRSS_PHY_1656_DATA 0x00000000
+#define DDRSS_PHY_1657_DATA 0x00000000
+#define DDRSS_PHY_1658_DATA 0x00000000
+#define DDRSS_PHY_1659_DATA 0x00000000
+#define DDRSS_PHY_1660_DATA 0x00000000
+#define DDRSS_PHY_1661_DATA 0x00000000
+#define DDRSS_PHY_1662_DATA 0x00000000
+#define DDRSS_PHY_1663_DATA 0x00000000
+#define DDRSS_PHY_1664_DATA 0x00000000
+#define DDRSS_PHY_1665_DATA 0x00000000
+#define DDRSS_PHY_1666_DATA 0x00000000
+#define DDRSS_PHY_1667_DATA 0x00000000
+#define DDRSS_PHY_1668_DATA 0x00000000
+#define DDRSS_PHY_1669_DATA 0x00000000
+#define DDRSS_PHY_1670_DATA 0x00000000
+#define DDRSS_PHY_1671_DATA 0x00000000
+#define DDRSS_PHY_1672_DATA 0x00000000
+#define DDRSS_PHY_1673_DATA 0x00000000
+#define DDRSS_PHY_1674_DATA 0x00000000
+#define DDRSS_PHY_1675_DATA 0x00000000
+#define DDRSS_PHY_1676_DATA 0x00000000
+#define DDRSS_PHY_1677_DATA 0x00000000
+#define DDRSS_PHY_1678_DATA 0x00000000
+#define DDRSS_PHY_1679_DATA 0x00000000
+#define DDRSS_PHY_1680_DATA 0x00000000
+#define DDRSS_PHY_1681_DATA 0x00000000
+#define DDRSS_PHY_1682_DATA 0x00000000
+#define DDRSS_PHY_1683_DATA 0x00000000
+#define DDRSS_PHY_1684_DATA 0x00000000
+#define DDRSS_PHY_1685_DATA 0x00000000
+#define DDRSS_PHY_1686_DATA 0x00000000
+#define DDRSS_PHY_1687_DATA 0x00000000
+#define DDRSS_PHY_1688_DATA 0x00000000
+#define DDRSS_PHY_1689_DATA 0x00000000
+#define DDRSS_PHY_1690_DATA 0x00000000
+#define DDRSS_PHY_1691_DATA 0x00000000
+#define DDRSS_PHY_1692_DATA 0x00000000
+#define DDRSS_PHY_1693_DATA 0x00000000
+#define DDRSS_PHY_1694_DATA 0x00000000
+#define DDRSS_PHY_1695_DATA 0x00000000
+#define DDRSS_PHY_1696_DATA 0x00000000
+#define DDRSS_PHY_1697_DATA 0x00000000
+#define DDRSS_PHY_1698_DATA 0x00000000
+#define DDRSS_PHY_1699_DATA 0x00000000
+#define DDRSS_PHY_1700_DATA 0x00000000
+#define DDRSS_PHY_1701_DATA 0x00000000
+#define DDRSS_PHY_1702_DATA 0x00000000
+#define DDRSS_PHY_1703_DATA 0x00000000
+#define DDRSS_PHY_1704_DATA 0x00000000
+#define DDRSS_PHY_1705_DATA 0x00000000
+#define DDRSS_PHY_1706_DATA 0x00000000
+#define DDRSS_PHY_1707_DATA 0x00000000
+#define DDRSS_PHY_1708_DATA 0x00000000
+#define DDRSS_PHY_1709_DATA 0x00000000
+#define DDRSS_PHY_1710_DATA 0x00000000
+#define DDRSS_PHY_1711_DATA 0x00000000
+#define DDRSS_PHY_1712_DATA 0x00000000
+#define DDRSS_PHY_1713_DATA 0x00000000
+#define DDRSS_PHY_1714_DATA 0x00000000
+#define DDRSS_PHY_1715_DATA 0x00000000
+#define DDRSS_PHY_1716_DATA 0x00000000
+#define DDRSS_PHY_1717_DATA 0x00000000
+#define DDRSS_PHY_1718_DATA 0x00000000
+#define DDRSS_PHY_1719_DATA 0x00000000
+#define DDRSS_PHY_1720_DATA 0x00000000
+#define DDRSS_PHY_1721_DATA 0x00000000
+#define DDRSS_PHY_1722_DATA 0x00000000
+#define DDRSS_PHY_1723_DATA 0x00000000
+#define DDRSS_PHY_1724_DATA 0x00000000
+#define DDRSS_PHY_1725_DATA 0x00000000
+#define DDRSS_PHY_1726_DATA 0x00000000
+#define DDRSS_PHY_1727_DATA 0x00000000
+#define DDRSS_PHY_1728_DATA 0x00000000
+#define DDRSS_PHY_1729_DATA 0x00000000
+#define DDRSS_PHY_1730_DATA 0x00000000
+#define DDRSS_PHY_1731_DATA 0x00000000
+#define DDRSS_PHY_1732_DATA 0x00000000
+#define DDRSS_PHY_1733_DATA 0x00000000
+#define DDRSS_PHY_1734_DATA 0x00000000
+#define DDRSS_PHY_1735_DATA 0x00000000
+#define DDRSS_PHY_1736_DATA 0x00000000
+#define DDRSS_PHY_1737_DATA 0x00000000
+#define DDRSS_PHY_1738_DATA 0x00000000
+#define DDRSS_PHY_1739_DATA 0x00000000
+#define DDRSS_PHY_1740_DATA 0x00000000
+#define DDRSS_PHY_1741_DATA 0x00000000
+#define DDRSS_PHY_1742_DATA 0x00000000
+#define DDRSS_PHY_1743_DATA 0x00000000
+#define DDRSS_PHY_1744_DATA 0x00000000
+#define DDRSS_PHY_1745_DATA 0x00000000
+#define DDRSS_PHY_1746_DATA 0x00000000
+#define DDRSS_PHY_1747_DATA 0x00000000
+#define DDRSS_PHY_1748_DATA 0x00000000
+#define DDRSS_PHY_1749_DATA 0x00000000
+#define DDRSS_PHY_1750_DATA 0x00000000
+#define DDRSS_PHY_1751_DATA 0x00000000
+#define DDRSS_PHY_1752_DATA 0x00000000
+#define DDRSS_PHY_1753_DATA 0x00000000
+#define DDRSS_PHY_1754_DATA 0x00000000
+#define DDRSS_PHY_1755_DATA 0x00000000
+#define DDRSS_PHY_1756_DATA 0x00000000
+#define DDRSS_PHY_1757_DATA 0x00000000
+#define DDRSS_PHY_1758_DATA 0x00000000
+#define DDRSS_PHY_1759_DATA 0x00000000
+#define DDRSS_PHY_1760_DATA 0x00000000
+#define DDRSS_PHY_1761_DATA 0x00000000
+#define DDRSS_PHY_1762_DATA 0x00000000
+#define DDRSS_PHY_1763_DATA 0x00000000
+#define DDRSS_PHY_1764_DATA 0x00000000
+#define DDRSS_PHY_1765_DATA 0x00000000
+#define DDRSS_PHY_1766_DATA 0x00000000
+#define DDRSS_PHY_1767_DATA 0x00000000
+#define DDRSS_PHY_1768_DATA 0x00000000
+#define DDRSS_PHY_1769_DATA 0x00000000
+#define DDRSS_PHY_1770_DATA 0x00000000
+#define DDRSS_PHY_1771_DATA 0x00000000
+#define DDRSS_PHY_1772_DATA 0x00000000
+#define DDRSS_PHY_1773_DATA 0x00000000
+#define DDRSS_PHY_1774_DATA 0x00000000
+#define DDRSS_PHY_1775_DATA 0x00000000
+#define DDRSS_PHY_1776_DATA 0x00000000
+#define DDRSS_PHY_1777_DATA 0x00000000
+#define DDRSS_PHY_1778_DATA 0x00000000
+#define DDRSS_PHY_1779_DATA 0x00000000
+#define DDRSS_PHY_1780_DATA 0x00000000
+#define DDRSS_PHY_1781_DATA 0x00000000
+#define DDRSS_PHY_1782_DATA 0x00000000
+#define DDRSS_PHY_1783_DATA 0x00000000
+#define DDRSS_PHY_1784_DATA 0x00000000
+#define DDRSS_PHY_1785_DATA 0x00000000
+#define DDRSS_PHY_1786_DATA 0x00000000
+#define DDRSS_PHY_1787_DATA 0x00000000
+#define DDRSS_PHY_1788_DATA 0x00000000
+#define DDRSS_PHY_1789_DATA 0x00000000
+#define DDRSS_PHY_1790_DATA 0x00000000
+#define DDRSS_PHY_1791_DATA 0x00000000
+#define DDRSS_PHY_1792_DATA 0x00000000
+#define DDRSS_PHY_1793_DATA 0x00010100
+#define DDRSS_PHY_1794_DATA 0x00000000
+#define DDRSS_PHY_1795_DATA 0x00000000
+#define DDRSS_PHY_1796_DATA 0x00000000
+#define DDRSS_PHY_1797_DATA 0x00000000
+#define DDRSS_PHY_1798_DATA 0x00050000
+#define DDRSS_PHY_1799_DATA 0x04000000
+#define DDRSS_PHY_1800_DATA 0x00000055
+#define DDRSS_PHY_1801_DATA 0x00000000
+#define DDRSS_PHY_1802_DATA 0x00000000
+#define DDRSS_PHY_1803_DATA 0x00000000
+#define DDRSS_PHY_1804_DATA 0x00000000
+#define DDRSS_PHY_1805_DATA 0x00002001
+#define DDRSS_PHY_1806_DATA 0x00004003
+#define DDRSS_PHY_1807_DATA 0x50020028
+#define DDRSS_PHY_1808_DATA 0x01010000
+#define DDRSS_PHY_1809_DATA 0x80080001
+#define DDRSS_PHY_1810_DATA 0x10200000
+#define DDRSS_PHY_1811_DATA 0x00000008
+#define DDRSS_PHY_1812_DATA 0x00000000
+#define DDRSS_PHY_1813_DATA 0x06000000
+#define DDRSS_PHY_1814_DATA 0x010F0F0E
+#define DDRSS_PHY_1815_DATA 0x00040101
+#define DDRSS_PHY_1816_DATA 0x0000010F
+#define DDRSS_PHY_1817_DATA 0x00000000
+#define DDRSS_PHY_1818_DATA 0x00000064
+#define DDRSS_PHY_1819_DATA 0x00000000
+#define DDRSS_PHY_1820_DATA 0x00000000
+#define DDRSS_PHY_1821_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1822_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1823_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1824_DATA 0x02010804
+#define DDRSS_PHY_1825_DATA 0x00800120
+#define DDRSS_PHY_1826_DATA 0x00041B42
+#define DDRSS_PHY_1827_DATA 0x00004201
+#define DDRSS_PHY_1828_DATA 0x00000000
+#define DDRSS_PHY_1829_DATA 0x00000000
+#define DDRSS_PHY_1830_DATA 0x00000000
+#define DDRSS_PHY_1831_DATA 0x00000000
+#define DDRSS_PHY_1832_DATA 0x00000000
+#define DDRSS_PHY_1833_DATA 0x00000000
+#define DDRSS_PHY_1834_DATA 0x03010100
+#define DDRSS_PHY_1835_DATA 0x00540007
+#define DDRSS_PHY_1836_DATA 0x000040A2
+#define DDRSS_PHY_1837_DATA 0x00024410
+#define DDRSS_PHY_1838_DATA 0x00004410
+#define DDRSS_PHY_1839_DATA 0x00004410
+#define DDRSS_PHY_1840_DATA 0x00004410
+#define DDRSS_PHY_1841_DATA 0x00004410
+#define DDRSS_PHY_1842_DATA 0x00004410
+#define DDRSS_PHY_1843_DATA 0x00004410
+#define DDRSS_PHY_1844_DATA 0x00004410
+#define DDRSS_PHY_1845_DATA 0x00004410
+#define DDRSS_PHY_1846_DATA 0x00004410
+#define DDRSS_PHY_1847_DATA 0x00000000
+#define DDRSS_PHY_1848_DATA 0x00000076
+#define DDRSS_PHY_1849_DATA 0x00000400
+#define DDRSS_PHY_1850_DATA 0x00000008
+#define DDRSS_PHY_1851_DATA 0x00000000
+#define DDRSS_PHY_1852_DATA 0x00000000
+#define DDRSS_PHY_1853_DATA 0x00000000
+#define DDRSS_PHY_1854_DATA 0x00000000
+#define DDRSS_PHY_1855_DATA 0x00000000
+#define DDRSS_PHY_1856_DATA 0x03000000
+#define DDRSS_PHY_1857_DATA 0x00000000
+#define DDRSS_PHY_1858_DATA 0x00000000
+#define DDRSS_PHY_1859_DATA 0x00000000
+#define DDRSS_PHY_1860_DATA 0x04102006
+#define DDRSS_PHY_1861_DATA 0x00041020
+#define DDRSS_PHY_1862_DATA 0x01C98C98
+#define DDRSS_PHY_1863_DATA 0x3F400000
+#define DDRSS_PHY_1864_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1865_DATA 0x0000001F
+#define DDRSS_PHY_1866_DATA 0x00000000
+#define DDRSS_PHY_1867_DATA 0x00000000
+#define DDRSS_PHY_1868_DATA 0x00000000
+#define DDRSS_PHY_1869_DATA 0x00000001
+#define DDRSS_PHY_1870_DATA 0x00000000
+#define DDRSS_PHY_1871_DATA 0x00000000
+#define DDRSS_PHY_1872_DATA 0x00000000
+#define DDRSS_PHY_1873_DATA 0x00000000
+#define DDRSS_PHY_1874_DATA 0x76543210
+#define DDRSS_PHY_1875_DATA 0x06010198
+#define DDRSS_PHY_1876_DATA 0x00000000
+#define DDRSS_PHY_1877_DATA 0x00000000
+#define DDRSS_PHY_1878_DATA 0x00000000
+#define DDRSS_PHY_1879_DATA 0x00040700
+#define DDRSS_PHY_1880_DATA 0x00000000
+#define DDRSS_PHY_1881_DATA 0x00000000
+#define DDRSS_PHY_1882_DATA 0x00000000
+#define DDRSS_PHY_1883_DATA 0x00000000
+#define DDRSS_PHY_1884_DATA 0x00000000
+#define DDRSS_PHY_1885_DATA 0x00000002
+#define DDRSS_PHY_1886_DATA 0x00000000
+#define DDRSS_PHY_1887_DATA 0x00000000
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
+#define DDRSS_PHY_1889_DATA 0x04000004
+#define DDRSS_PHY_1890_DATA 0x00000000
+#define DDRSS_PHY_1891_DATA 0x00001142
+#define DDRSS_PHY_1892_DATA 0x01020000
+#define DDRSS_PHY_1893_DATA 0x00000080
+#define DDRSS_PHY_1894_DATA 0x03900390
+#define DDRSS_PHY_1895_DATA 0x03900390
+#define DDRSS_PHY_1896_DATA 0x03900390
+#define DDRSS_PHY_1897_DATA 0x03900390
+#define DDRSS_PHY_1898_DATA 0x03000300
+#define DDRSS_PHY_1899_DATA 0x03000300
+#define DDRSS_PHY_1900_DATA 0x00000300
+#define DDRSS_PHY_1901_DATA 0x00000300
+#define DDRSS_PHY_1902_DATA 0x00000300
+#define DDRSS_PHY_1903_DATA 0x00000300
+#define DDRSS_PHY_1904_DATA 0x00000005
+#define DDRSS_PHY_1905_DATA 0x3183BF77
+#define DDRSS_PHY_1906_DATA 0x00000000
+#define DDRSS_PHY_1907_DATA 0x0C000DFF
+#define DDRSS_PHY_1908_DATA 0x30000DFF
+#define DDRSS_PHY_1909_DATA 0x3F0DFF11
+#define DDRSS_PHY_1910_DATA 0x00EF0000
+#define DDRSS_PHY_1911_DATA 0x780DFFCC
+#define DDRSS_PHY_1912_DATA 0x00000C11
+#define DDRSS_PHY_1913_DATA 0x00018011
+#define DDRSS_PHY_1914_DATA 0x0089FF00
+#define DDRSS_PHY_1915_DATA 0x000C3F11
+#define DDRSS_PHY_1916_DATA 0x01990000
+#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1918_DATA 0x01990000
+#define DDRSS_PHY_1919_DATA 0x3F0DFF11
+#define DDRSS_PHY_1920_DATA 0x00EF0000
+#define DDRSS_PHY_1921_DATA 0x00018011
+#define DDRSS_PHY_1922_DATA 0x0089FF00
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts
new file mode 100644
index 0000000..664be35
--- /dev/null
+++ b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM67A BeagleY-AI dts file for R5 SPL
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-am67a-beagley-ai.dts"
+#include "k3-am67a-beagley-ai-u-boot.dtsi"
+
+#include "k3-am67a-beagley-ddr-lp4.dtsi"
+#include "k3-am62a-ddr.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-all;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <36>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 22>,
+ <&secure_proxy_main 23>;
+ bootph-all;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&cbass_main {
+ sa3_secproxy: secproxy@44880000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg = <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>,
+ <0x00 0x43600000 0x00 0x10000>;
+ reg-names = "rt", "scfg", "target_data";
+ bootph-all;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>,
+ <&sa3_secproxy 0>;
+ mbox-names = "tx", "rx", "boot_notify";
+ bootph-all;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index ecb1dd4..9ac2911 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -120,3 +120,10 @@
vdd-supply-2 = <&buckb1>;
bootph-pre-ram;
};
+
+&tps659414 {
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/dts/mt7987-pinctrl.dtsi b/arch/arm/dts/mt7987-pinctrl.dtsi
index b5e643f..dfde212 100644
--- a/arch/arm/dts/mt7987-pinctrl.dtsi
+++ b/arch/arm/dts/mt7987-pinctrl.dtsi
@@ -191,6 +191,20 @@
};
};
+ pwm_pins: pwm-pins {
+ mux {
+ /*
+ * - pwm0 : PWM0@PIN13
+ * - pwm1_0 : PWM1@PIN7 (share with JTAG)
+ * pwm1_1 : PWM1@PIN43 (share with i2c0)
+ * - pwm2_0 : PWM2@PIN12 (share with PCM)
+ * pwm2_1 : PWM2@PIN44 (share with i2c0)
+ */
+ function = "pwm";
+ groups = "pwm0";
+ };
+ };
+
uart1_pins: uart1-pins {
mux {
function = "uart";
diff --git a/arch/arm/dts/mt7987.dtsi b/arch/arm/dts/mt7987.dtsi
index fd1585f..4c1d597 100644
--- a/arch/arm/dts/mt7987.dtsi
+++ b/arch/arm/dts/mt7987.dtsi
@@ -389,21 +389,15 @@
};
pwm: pwm@10048000 {
- compatible = "mediatek,mt7988-pwm";
+ compatible = "mediatek,mt7987-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
<&infracfg CLK_INFRA_66M_PWM_HCK>,
- <&clkxtal>,
- <&clkxtal>,
- <&clkxtal>,
- <&clkxtal>,
- <&clkxtal>,
- <&clkxtal>,
- <&clkxtal>,
- <&clkxtal>;
- clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
- "pwm4","pwm5","pwm6","pwm7","pwm8";
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7987a-u-boot.dtsi b/arch/arm/dts/mt7987a-u-boot.dtsi
index ec0a638..a1cb42a 100644
--- a/arch/arm/dts/mt7987a-u-boot.dtsi
+++ b/arch/arm/dts/mt7987a-u-boot.dtsi
@@ -24,6 +24,10 @@
mediatek,hwver = <&hwver>;
};
};
+
+ reserved-memory {
+ /delete-node/ wmcpu-reserved@50000000;
+ };
};
&i2c0 {
diff --git a/arch/arm/dts/mt7987a.dtsi b/arch/arm/dts/mt7987a.dtsi
index 028f563..365fefd 100644
--- a/arch/arm/dts/mt7987a.dtsi
+++ b/arch/arm/dts/mt7987a.dtsi
@@ -29,7 +29,7 @@
&fan {
pwms = <&pwm 0 50000 0>;
- status = "okay";
+ status = "disabled";
};
&i2c0 {
@@ -59,6 +59,8 @@
};
&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/dts/nuvoton-common-npcm7xx.dtsi
index feb8887..093d542 100644
--- a/arch/arm/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm7xx.dtsi
@@ -95,6 +95,11 @@
compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
reg = <0x801000 0x6C>;
};
+
+ timer0: timer@f0801068 {
+ compatible = "nuvoton,npcm750-timer";
+ reg = <0x801068 0x8>;
+ };
};
ahb {
@@ -245,13 +250,6 @@
status = "disabled";
};
- timer0: timer@8000 {
- compatible = "nuvoton,npcm750-timer";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x8000 0x1C>;
- clocks = <&clk NPCM7XX_CLK_TIMER>;
- };
-
watchdog0: watchdog@801C {
compatible = "nuvoton,npcm750-wdt";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index 10051c9..cc9d99b 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -147,6 +147,10 @@
bootph-all;
};
+&otp {
+ bootph-all;
+};
+
&pfc {
bootph-all;
};
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
index 788e44f..86322d7 100644
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -331,6 +331,20 @@
status = "disabled";
};
+ nand: nand@10b80000 {
+ compatible = "cdns,nand";
+ reg = <0x10b80000 0x10000>,
+ <0x10840000 0x1000>;
+ reg-names = "reg", "sdma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 97 4>;
+ clocks = <&clkmgr AGILEX5_NAND_CLK>;
+ resets = <&rst NAND_RESET>, <&rst COMBOPHY_RESET>;
+ cdns,board-delay-ps = <4830>;
+ status = "disabled";
+ };
+
ocram: sram@00000000 {
compatible = "mmio-sram";
reg = <0x00000000 0x200000>;
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index e08dd55..d7ab582 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -69,6 +69,10 @@
/delete-property/ cdns,read-delay;
};
+&flash1 {
+ bootph-all;
+};
+
&i3c0 {
bootph-all;
};
@@ -130,6 +134,10 @@
status = "okay";
};
+&nand {
+ bootph-all;
+};
+
&timer0 {
bootph-all;
};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
index ca87e99..2ab143e 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -165,3 +165,22 @@
};
};
};
+
+&nand {
+ status = "okay";
+
+ flash1: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "root";
+ reg = <0x200000 0x3fe00000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts
index 6cb1781..64386f2 100644
--- a/arch/arm/dts/tegra124-xiaomi-mocha.dts
+++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts
@@ -215,8 +215,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,open-drain = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -225,8 +225,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,open-drain = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -235,8 +235,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,open-drain = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -253,7 +253,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,open-drain = <1>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dsi-b {
diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts
index 243ff2b..58f1499 100644
--- a/arch/arm/dts/tegra30-asus-p1801-t.dts
+++ b/arch/arm/dts/tegra30-asus-p1801-t.dts
@@ -34,20 +34,10 @@
host1x@50000000 {
dc@54200000 {
- clocks = <&tegra_car TEGRA30_CLK_DISP1>,
- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
-
- rgb {
- status = "okay";
-
- nvidia,panel = <&hdmi>;
- };
+ status = "disabled";
};
hdmi: hdmi@54280000 {
- clocks = <&tegra_car TEGRA30_CLK_HDMI>,
- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
-
status = "okay";
hdmi-supply = <&hdmi_5v0_sys>;
@@ -118,8 +108,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -203,7 +193,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -213,7 +203,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -223,7 +213,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -232,7 +222,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -242,7 +232,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
nvidia,pins = "pu4";
@@ -260,7 +250,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hdmi_hpd {
nvidia,pins = "hdmi_int_pn7";
@@ -632,8 +622,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -718,8 +708,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_d10_pt2 {
nvidia,pins = "vi_d10_pt2",
@@ -838,8 +828,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
nvidia,pins = "vi_mclk_pt1";
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts
index 3ddd78b..1b5729c 100644
--- a/arch/arm/dts/tegra30-asus-tf600t.dts
+++ b/arch/arm/dts/tegra30-asus-tf600t.dts
@@ -90,8 +90,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC2 pinmux */
@@ -107,8 +107,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -142,8 +142,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4_cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -159,8 +159,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4_rst_n {
nvidia,pins = "sdmmc4_rst_n_pcc3";
@@ -186,7 +186,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -196,7 +196,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -206,7 +206,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -215,7 +215,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -225,7 +225,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
nvidia,pins = "pu4";
@@ -243,7 +243,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hdmi_hpd {
nvidia,pins = "hdmi_int_pn7";
@@ -613,8 +613,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -701,8 +701,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
pbb0 {
nvidia,pins = "pbb0";
@@ -827,8 +827,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -836,8 +836,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
jtag {
diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts
index 6dc760b..47606ed 100644
--- a/arch/arm/dts/tegra30-asus-tf700t.dts
+++ b/arch/arm/dts/tegra30-asus-tf700t.dts
@@ -15,7 +15,14 @@
rgb {
status = "okay";
- nvidia,panel = <&tc358768>;
+ /delete-property/ nvidia,panel;
+
+ port {
+ dpi_output: endpoint {
+ remote-endpoint = <&bridge_input>;
+ bus-width = <24>;
+ };
+ };
};
};
};
@@ -118,39 +125,70 @@
vddio-supply = <&vdd_1v8_vio>;
vddmipi-supply = <&vdd_1v2_mipi>;
- panel = <&panel>;
- };
- };
- };
+ /*
+ * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
+ * LCD SuperIPS+ Full HD panel.
+ */
+ panel@1 {
+ compatible = "panasonic,vvx10f004b00";
+ reg = <1>;
- panel: panel {
- compatible = "panasonic,vvx10f004b00";
+ power-supply = <&vdd_pnl_reg>;
+ backlight = <&backlight>;
- power-supply = <&vdd_pnl_reg>;
- backlight = <&backlight>;
+ display-timings {
+ timing@0 {
+ /* 1920x1200@60Hz */
+ clock-frequency = <154000000>;
- /delete-property/ enable-gpios;
+ hactive = <1920>;
+ hfront-porch = <48>;
+ hback-porch = <80>;
+ hsync-len = <32>;
+ hsync-active = <1>;
- display-timings {
- timing@0 {
- /* 1920x1200@60Hz */
- clock-frequency = <154000000>;
+ vactive = <1200>;
+ vfront-porch = <3>;
+ vback-porch = <26>;
+ vsync-len = <6>;
+ vsync-active = <1>;
+ };
+ };
- hactive = <1920>;
- hfront-porch = <48>;
- hback-porch = <80>;
- hsync-len = <32>;
- hsync-active = <1>;
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
- vactive = <1200>;
- vfront-porch = <3>;
- vback-porch = <26>;
- vsync-len = <6>;
- vsync-active = <1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ bus-width = <24>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
};
};
};
+ /delete-node/ panel;
+
vdd_1v2_mipi: regulator-mipi {
compatible = "regulator-fixed";
regulator-name = "tc358768_1v2_vdd";
diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi
index 03ba8fb..032fb3d 100644
--- a/arch/arm/dts/tegra30-asus-transformer.dtsi
+++ b/arch/arm/dts/tegra30-asus-transformer.dtsi
@@ -99,8 +99,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -189,7 +189,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
@@ -200,7 +200,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
@@ -211,7 +211,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
@@ -221,7 +221,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
@@ -232,7 +232,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
@@ -647,8 +647,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -741,8 +741,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_d10_pt2 {
@@ -879,8 +879,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts
index 8a0ba3c..db8ac45 100644
--- a/arch/arm/dts/tegra30-htc-endeavoru.dts
+++ b/arch/arm/dts/tegra30-htc-endeavoru.dts
@@ -33,13 +33,11 @@
host1x@50000000 {
dc@54200000 {
- clocks = <&tegra_car TEGRA30_CLK_DISP1>,
- <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+ backlight: backlight {
+ compatible = "nvidia,tegra-pwm-backlight";
- rgb {
- status = "okay";
-
- nvidia,panel = <&dsia>;
+ nvidia,pwm-source = <1>;
+ nvidia,default-brightness = <0x8E>;
};
};
@@ -1265,13 +1263,6 @@
nvidia,xcvr-lsrslew = <2>;
};
- backlight: backlight {
- compatible = "nvidia,tegra-pwm-backlight";
-
- nvidia,pwm-source = <1>;
- nvidia,default-brightness = <0x8E>;
- };
-
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
index 9a1e8c0..876fac7 100644
--- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
+++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
@@ -109,8 +109,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -127,8 +127,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
cam-mclk {
nvidia,pins = "cam_mclk_pcc0";
@@ -147,7 +147,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -157,7 +157,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -167,7 +167,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -176,7 +176,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -186,7 +186,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
@@ -724,8 +724,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-vsync-pd6 {
nvidia,pins = "vi_vsync_pd6",
@@ -736,8 +736,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <2>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_ENABLE>;
};
vi-hsync-pd7 {
nvidia,pins = "vi_hsync_pd7",
@@ -749,8 +749,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d2-pl0 {
nvidia,pins = "vi_d2_pl0",
@@ -760,8 +760,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-mclk-pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -769,8 +769,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <2>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_ENABLE>;
};
vi-d11-pt3 {
nvidia,pins = "vi_d11_pt3";
@@ -778,8 +778,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d5-pl3 {
nvidia,pins = "vi_d5_pl3";
@@ -787,8 +787,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* PORT U */
diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts
index 1d5ca14..ab59931 100644
--- a/arch/arm/dts/tegra30-lg-p880.dts
+++ b/arch/arm/dts/tegra30-lg-p880.dts
@@ -101,6 +101,31 @@
};
};
+ spi@7000dc00 {
+ bridge-spi@2 {
+ /*
+ * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
+ */
+ panel@0 {
+ compatible = "jdi,dx12d100vm0eaa";
+ reg = <0>;
+
+ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+ vdd-supply = <&vcc_3v0_lcd>;
+ vddio-supply = <&iovcc_1v8_lcd>;
+
+ backlight = <&backlight>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+ };
+ };
+
sdmmc3: sdhci@78000400 {
status = "okay";
bus-width = <4>;
@@ -118,13 +143,4 @@
linux,code = <KEY_UP>;
};
};
-
- panel: panel {
- compatible = "jdi,dx12d100vm0eaa";
-
- enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
-
- backlight = <&backlight>;
- };
};
diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts
index 43bb373..988e772 100644
--- a/arch/arm/dts/tegra30-lg-p895.dts
+++ b/arch/arm/dts/tegra30-lg-p895.dts
@@ -108,36 +108,37 @@
};
};
- panel: panel {
- compatible = "hitachi,tx13d100vm0eaa";
+ spi@7000dc00 {
+ bridge-spi@2 {
+ /*
+ * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
+ */
+ panel@0 {
+ compatible = "koe,tx13d100vm0eaa";
+ reg = <0>;
- reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
- renesas,gamma = <3>;
- renesas,inversion;
- renesas,contrast;
+ renesas,gamma = <3>;
+ renesas,inversion;
+ renesas,contrast;
- vcc-supply = <&vcc_3v0_lcd>;
- iovcc-supply = <&iovcc_1v8_lcd>;
+ vcc-supply = <&vcc_3v0_lcd>;
+ iovcc-supply = <&iovcc_1v8_lcd>;
- backlight = <&backlight>;
- };
+ backlight = <&backlight>;
- vcc_3v0_lcd: regulator-lcd {
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v0_lcd";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+ };
};
- iovcc_1v8_lcd: regulator-lcdvio {
- compatible = "regulator-fixed";
- regulator-name = "iovcc_1v8_lcd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ regulator-lcd3v {
+ gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi
index 30d6dcb..40b0ee0 100644
--- a/arch/arm/dts/tegra30-lg-x3.dtsi
+++ b/arch/arm/dts/tegra30-lg-x3.dtsi
@@ -32,7 +32,12 @@
rgb {
status = "okay";
- nvidia,panel = <&bridge>;
+ port {
+ dpi_output: endpoint {
+ remote-endpoint = <&bridge_input>;
+ bus-width = <24>;
+ };
+ };
};
};
};
@@ -890,12 +895,22 @@
status = "okay";
clock-frequency = <400000>;
- backlight: lm3533@36 {
+ backlight: led-controller@36 {
compatible = "ti,lm3533";
reg = <0x36>;
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
- default-brightness-level = <128>;
+
+ ti,boost-ovp-microvolt = <24000000>;
+ ti,boost-freq-hz = <500000>;
+
+ backlight-0 {
+ compatible = "ti,lm3533-backlight";
+
+ ti,max-current-microamp = <23400>;
+ ti,linear-mapping-mode;
+ ti,hardware-controlled;
+ };
};
muic@44 {
@@ -969,18 +984,46 @@
compatible = "solomon,ssd2825";
reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
spi-cpol;
spi-cpha;
spi-max-frequency = <1000000>;
- power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
+
+ dvdd-supply = <&vdd_1v2_rgb>;
+ avdd-supply = <&vdd_1v2_rgb>;
+ vddio-supply = <&vdd_1v8_vio>;
+
+ solomon,hs-zero-delay-ns = <300>;
+ solomon,hs-prep-delay-ns = <65>;
clocks = <&ssd2825_refclk>;
- clock-names = "tx_clk";
- panel = <&panel>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ bus-width = <24>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
};
};
@@ -1036,4 +1079,29 @@
linux,code = <KEY_DOWN>;
};
};
+
+ vdd_1v2_rgb: regulator-rgb1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v2_rgb";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_3v0_lcd: regulator-lcd3v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v0_lcd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ iovcc_1v8_lcd: regulator-lcd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "iovcc_1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
index 6810350..2d22d3e 100644
--- a/arch/arm/dts/tegra30-microsoft-surface-rt.dts
+++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
@@ -103,8 +103,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -121,8 +121,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
cam-mclk {
nvidia,pins = "cam_mclk_pcc0";
@@ -141,7 +141,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -151,7 +151,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -161,7 +161,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -170,7 +170,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -180,7 +180,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
@@ -703,8 +703,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d3-pl1 {
nvidia,pins = "vi_d3_pl1";
@@ -712,8 +712,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-hsync-pd7 {
nvidia,pins = "vi_hsync_pd7",
@@ -724,8 +724,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-mclk-pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -733,8 +733,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d11-pt3 {
nvidia,pins = "vi_d11_pt3";
@@ -742,8 +742,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,lock = <1>;
- nvidia,io-reset = <1>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* PORT U */
diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts
new file mode 100644
index 0000000..04453eb
--- /dev/null
+++ b/arch/arm/dts/tegra30-ouya.dts
@@ -0,0 +1,2063 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+
+/ {
+ model = "Ouya Game Console";
+ compatible = "ouya,ouya", "nvidia,tegra30";
+
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+ i2c1 = &hdmi_ddc;
+
+ mmc0 = &sdmmc4;
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = µ_usb;
+ usb1 = ðernet_usb;
+ usb2 = &fullsize_usb;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ status = "disabled";
+ };
+
+ hdmi: hdmi@54280000 {
+ status = "okay";
+
+ hdmi-supply = <&sys_3v3_reg>;
+ pll-supply = <&ldo7_reg>;
+ vdd-supply = <&vdd_vid_reg>;
+
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ };
+ };
+
+ gpio@6000d000 {
+ fan-en-hog {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uart3_cts_n_pa1 {
+ nvidia,pins = "uart3_cts_n_pa1";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap2_sclk_pa3 {
+ nvidia,pins = "dap2_sclk_pa3";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap2_din_pa4 {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap2_dout_pa5 {
+ nvidia,pins = "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_a18_pb1 {
+ nvidia,pins = "gmi_a18_pb1";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_pclk_pb3 {
+ nvidia,pins = "lcd_pclk_pb3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc3_dat3_pb4 {
+ nvidia,pins = "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_dat2_pb5 {
+ nvidia,pins = "sdmmc3_dat2_pb5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_dat1_pb6 {
+ nvidia,pins = "sdmmc3_dat1_pb6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_dat0_pb7 {
+ nvidia,pins = "sdmmc3_dat0_pb7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ uart3_rts_n_pc0 {
+ nvidia,pins = "uart3_rts_n_pc0";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_pwr1_pc1 {
+ nvidia,pins = "lcd_pwr1_pc1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ gen1_i2c_sda_pc5 {
+ nvidia,pins = "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ sdmmc3_dat5_pd0 {
+ nvidia,pins = "sdmmc3_dat5_pd0";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc3_dat4_pd1 {
+ nvidia,pins = "sdmmc3_dat4_pd1";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc3_dat6_pd3 {
+ nvidia,pins = "sdmmc3_dat6_pd3";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc3_dat7_pd4 {
+ nvidia,pins = "sdmmc3_dat7_pd4";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d1_pd5 {
+ nvidia,pins = "vi_d1_pd5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_vsync_pd6 {
+ nvidia,pins = "vi_vsync_pd6";
+ nvidia,function = "ddr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_hsync_pd7 {
+ nvidia,pins = "vi_hsync_pd7";
+ nvidia,function = "ddr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ lcd_d0_pe0 {
+ nvidia,pins = "lcd_d0_pe0";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d1_pe1 {
+ nvidia,pins = "lcd_d1_pe1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d2_pe2 {
+ nvidia,pins = "lcd_d2_pe2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d3_pe3 {
+ nvidia,pins = "lcd_d3_pe3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d4_pe4 {
+ nvidia,pins = "lcd_d4_pe4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d5_pe5 {
+ nvidia,pins = "lcd_d5_pe5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d6_pe6 {
+ nvidia,pins = "lcd_d6_pe6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d7_pe7 {
+ nvidia,pins = "lcd_d7_pe7";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d8_pf0 {
+ nvidia,pins = "lcd_d8_pf0";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d9_pf1 {
+ nvidia,pins = "lcd_d9_pf1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d10_pf2 {
+ nvidia,pins = "lcd_d10_pf2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d11_pf3 {
+ nvidia,pins = "lcd_d11_pf3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d12_pf4 {
+ nvidia,pins = "lcd_d12_pf4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d13_pf5 {
+ nvidia,pins = "lcd_d13_pf5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d14_pf6 {
+ nvidia,pins = "lcd_d14_pf6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d15_pf7 {
+ nvidia,pins = "lcd_d15_pf7";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad1_pg1 {
+ nvidia,pins = "gmi_ad1_pg1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad2_pg2 {
+ nvidia,pins = "gmi_ad2_pg2";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad3_pg3 {
+ nvidia,pins = "gmi_ad3_pg3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad4_pg4 {
+ nvidia,pins = "gmi_ad4_pg4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad5_pg5 {
+ nvidia,pins = "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad6_pg6 {
+ nvidia,pins = "gmi_ad6_pg6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad7_pg7 {
+ nvidia,pins = "gmi_ad7_pg7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_ad8_ph0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad9_ph1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad11_ph3 {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_ad14_ph6 {
+ nvidia,pins = "gmi_ad14_ph6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_wr_n_pi0 {
+ nvidia,pins = "gmi_wr_n_pi0";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_oe_n_pi1 {
+ nvidia,pins = "gmi_oe_n_pi1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_dqs_pi2 {
+ nvidia,pins = "gmi_dqs_pi2";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_iordy_pi5 {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs7_n_pi6 {
+ nvidia,pins = "gmi_cs7_n_pi6";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_wait_pi7 {
+ nvidia,pins = "gmi_wait_pi7";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_de_pj1 {
+ nvidia,pins = "lcd_de_pj1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs1_n_pj2 {
+ nvidia,pins = "gmi_cs1_n_pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_hsync_pj3 {
+ nvidia,pins = "lcd_hsync_pj3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_vsync_pj4 {
+ nvidia,pins = "lcd_vsync_pj4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uart2_cts_n_pj5 {
+ nvidia,pins = "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uart2_rts_n_pj6 {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_a16_pj7 {
+ nvidia,pins = "gmi_a16_pj7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_adv_n_pk0 {
+ nvidia,pins = "gmi_adv_n_pk0";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_clk_pk1 {
+ nvidia,pins = "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs2_n_pk3 {
+ nvidia,pins = "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ gmi_cs3_n_pk4 {
+ nvidia,pins = "gmi_cs3_n_pk4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gmi_a19_pk7 {
+ nvidia,pins = "gmi_a19_pk7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d2_pl0 {
+ nvidia,pins = "vi_d2_pl0";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d3_pl1 {
+ nvidia,pins = "vi_d3_pl1";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d4_pl2 {
+ nvidia,pins = "vi_d4_pl2";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d5_pl3 {
+ nvidia,pins = "vi_d5_pl3";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d6_pl4 {
+ nvidia,pins = "vi_d6_pl4";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d7_pl5 {
+ nvidia,pins = "vi_d7_pl5";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d8_pl6 {
+ nvidia,pins = "vi_d8_pl6";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d9_pl7 {
+ nvidia,pins = "vi_d9_pl7";
+ nvidia,function = "sdmmc2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d16_pm0 {
+ nvidia,pins = "lcd_d16_pm0";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d17_pm1 {
+ nvidia,pins = "lcd_d17_pm1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d18_pm2 {
+ nvidia,pins = "lcd_d18_pm2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d19_pm3 {
+ nvidia,pins = "lcd_d19_pm3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d20_pm4 {
+ nvidia,pins = "lcd_d20_pm4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d21_pm5 {
+ nvidia,pins = "lcd_d21_pm5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d22_pm6 {
+ nvidia,pins = "lcd_d22_pm6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_d23_pm7 {
+ nvidia,pins = "lcd_d23_pm7";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap1_dout_pn2 {
+ nvidia,pins = "dap1_dout_pn2";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap1_sclk_pn3 {
+ nvidia,pins = "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ lcd_cs0_n_pn4 {
+ nvidia,pins = "lcd_cs0_n_pn4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_sdout_pn5 {
+ nvidia,pins = "lcd_sdout_pn5";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_dc0_pn6 {
+ nvidia,pins = "lcd_dc0_pn6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data0_po1 {
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data1_po2 {
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data2_po3 {
+ nvidia,pins = "ulpi_data2_po3";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data3_po4 {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_data4_po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_data6_po7 {
+ nvidia,pins = "ulpi_data6_po7";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap3_dout_pp2 {
+ nvidia,pins = "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap3_sclk_pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap4_fs_pp4 {
+ nvidia,pins = "dap4_fs_pp4";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap4_din_pp5 {
+ nvidia,pins = "dap4_din_pp5";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap4_dout_pp6 {
+ nvidia,pins = "dap4_dout_pp6";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ dap4_sclk_pp7 {
+ nvidia,pins = "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col1_pq1 {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col3_pq3 {
+ nvidia,pins = "kb_col3_pq3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col5_pq5 {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col6_pq6 {
+ nvidia,pins = "kb_col6_pq6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_col7_pq7 {
+ nvidia,pins = "kb_col7_pq7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row1_pr1 {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row2_pr2 {
+ nvidia,pins = "kb_row2_pr2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row4_pr4 {
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row5_pr5 {
+ nvidia,pins = "kb_row5_pr5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row6_pr6 {
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ kb_row8_ps0 {
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row9_ps1 {
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row10_ps2 {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row12_ps4 {
+ nvidia,pins = "kb_row12_ps4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row14_ps6 {
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_pclk_pt0 {
+ nvidia,pins = "vi_pclk_pt0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_mclk_pt1 {
+ nvidia,pins = "vi_mclk_pt1";
+ nvidia,function = "vi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ vi_d10_pt2 {
+ nvidia,pins = "vi_d10_pt2";
+ nvidia,function = "ddr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_d11_pt3 {
+ nvidia,pins = "vi_d11_pt3";
+ nvidia,function = "ddr";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ vi_d0_pt4 {
+ nvidia,pins = "vi_d0_pt4";
+ nvidia,function = "ddr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ gen2_i2c_sda_pt6 {
+ nvidia,pins = "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu1 {
+ nvidia,pins = "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ jtag_rtck_pu7 {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pv1 {
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pv2 {
+ nvidia,pins = "pv2";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pv3 {
+ nvidia,pins = "pv3";
+ nvidia,function = "clk_12m_out";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ddc_sda_pv5 {
+ nvidia,pins = "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ crt_vsync_pv7 {
+ nvidia,pins = "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_cs1_n_pw0 {
+ nvidia,pins = "lcd_cs1_n_pw0";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_m1_pw1 {
+ nvidia,pins = "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk2_out_pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ uart3_txd_pw6 {
+ nvidia,pins = "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ uart3_rxd_pw7 {
+ nvidia,pins = "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ spi2_sck_px2 {
+ nvidia,pins = "spi2_sck_px2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi1_cs0_n_px6 {
+ nvidia,pins = "spi1_cs0_n_px6";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ ulpi_dir_py1 {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc1_dat2_py5 {
+ nvidia,pins = "sdmmc1_dat2_py5";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc1_dat1_py6 {
+ nvidia,pins = "sdmmc1_dat1_py6";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc1_dat0_py7 {
+ nvidia,pins = "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_sdin_pz2 {
+ nvidia,pins = "lcd_sdin_pz2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_wr_n_pz3 {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ lcd_sck_pz4 {
+ nvidia,pins = "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ sys_clk_req_pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ pwr_i2c_sda_pz7 {
+ nvidia,pins = "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ pbb0 {
+ nvidia,pins = "pbb0";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ cam_i2c_sda_pbb2 {
+ nvidia,pins = "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pbb7 {
+ nvidia,pins = "pbb7";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pcc1 {
+ nvidia,pins = "pcc1";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pcc2 {
+ nvidia,pins = "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l2_rst_n_pcc6 {
+ nvidia,pins = "pex_l2_rst_n_pcc6";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l2_clkreq_n_pcc7 {
+ nvidia,pins = "pex_l2_clkreq_n_pcc7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l0_prsnt_n_pdd0 {
+ nvidia,pins = "pex_l0_prsnt_n_pdd0";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l0_rst_n_pdd1 {
+ nvidia,pins = "pex_l0_rst_n_pdd1";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l0_clkreq_n_pdd2 {
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l1_prsnt_n_pdd4 {
+ nvidia,pins = "pex_l1_prsnt_n_pdd4";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l1_rst_n_pdd5 {
+ nvidia,pins = "pex_l1_rst_n_pdd5";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l1_clkreq_n_pdd6 {
+ nvidia,pins = "pex_l1_clkreq_n_pdd6";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ pex_l2_prsnt_n_pdd7 {
+ nvidia,pins = "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ clk1_req_pee2 {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SDMMC4 pinmux */
+ sdmmc4_clk {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc4_cmd {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
+ nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc4_rst_n {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ drive_groups {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ };
+
+ hdmi_ddc: i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: pmic@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ wakeup-source;
+
+ ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
+ ti,system-power-controller;
+ ti,sleep-keep-ck32k;
+ ti,sleep-enable;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ vdd_1v8: vddio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ sdmmc4: sdhci@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&sys_3v3_reg>;
+ vqmmc-supply = <&vdd_1v8>;
+ };
+
+ micro_usb: usb@7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ };
+
+ ethernet_usb: usb@7d004000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* SMSC 10/100T Ethernet Controller */
+ ethernet@2 {
+ compatible = "usb424,9e00";
+ reg = <2>;
+ local-mac-address = [00 11 22 33 44 55];
+ };
+ };
+
+ usb-phy@7d004000 {
+ status = "okay";
+ };
+
+ fullsize_usb: usb@7d008000 {
+ status = "okay";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-power {
+ label = "power-led";
+ gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ retain-state-suspended;
+ };
+ };
+
+ sys_3v3_reg: regulator-sys-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_vid_reg: regulator-vdd-vid {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio_vid";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts
index 87c2a40..b376b91 100644
--- a/arch/arm/dts/tegra30-wexler-qc750.dts
+++ b/arch/arm/dts/tegra30-wexler-qc750.dts
@@ -157,7 +157,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -167,7 +167,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -177,7 +177,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -186,7 +186,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -196,7 +196,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,lock = <0>;
+ nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
index c67d12d..a11dfde 100644
--- a/arch/arm/include/asm/arch-meson/boot.h
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -21,4 +21,18 @@
int meson_get_soc_rev(char *buff, size_t buff_len);
+/**
+ * meson_get_socinfo - retrieve cpu_id of the Amlogic SoC
+ *
+ * The value in the following format is read from register:
+ * +-----------+------------+------------+------------+
+ * | family_id | package_id | chip_rev | layout_rev |
+ * +-----------+------------+------------+------------+
+ * | 31 24 | 23 16 | 15 8 | 7 0 |
+ * +-----------+------------+------------+------------+
+ *
+ * Return: 4 bytes value of cpu_id on success or 0 on failure.
+ */
+u32 meson_get_socinfo(void);
+
#endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 4b1d564..4d61495 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -6,6 +6,8 @@
#ifndef __MESON_SM_H__
#define __MESON_SM_H__
+#include <asm/types.h>
+
/**
* meson_sm_read_efuse - read efuse memory into buffer
*
@@ -27,16 +29,60 @@
ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
#define SM_SERIAL_SIZE 12
+#define MESON_CPU_ID_SZ 4
+#define MESON_CHIP_ID_SZ 16
+
+/**
+ * union meson_cpu_id - Amlogic cpu_id.
+ * @raw: buffer to hold the cpu_id value as sequential bytes.
+ * @val: cpu_id represented as 32 bit value.
+ */
+union meson_cpu_id {
+ u8 raw[MESON_CPU_ID_SZ];
+ u32 val;
+};
/**
- * meson_sm_get_serial - read chip unique id into buffer
+ * struct meson_sm_chip_id - Amlogic chip_id.
+ * @cpu_id: cpu_id value, which is distinct from socinfo in that the order of
+ * PACK & MINOR bytes are swapped according to Amlogic chip_id format.
+ * @serial: 12 byte unique SoC number, identifying particular die, read
+ * usually from efuse OTP storage. Serial comes in little-endian
+ * order.
+ */
+struct meson_sm_chip_id {
+ union meson_cpu_id cpu_id;
+ u8 serial[SM_SERIAL_SIZE];
+};
+
+/**
+ * meson_sm_get_serial - read chip unique serial (OTP data) into buffer
*
* @buffer: pointer to buffer
* @size: buffer size.
+ *
+ * Serial is returned in big-endian order.
+ *
* @return: zero on success or -errno on failure
*/
int meson_sm_get_serial(void *buffer, size_t size);
+/**
+ * meson_sm_get_chip_id - read Amlogic chip_id
+ *
+ * @chip_id: pointer to buffer capable to hold the struct meson_sm_chip_id
+ *
+ * Amlogic SoCs support 2 versions of chip_id. Function requests the newest
+ * one (v2), but if chip_id v2 is not supported, then secure monitor returns
+ * v1. All differences between v1 and v2 versions are handled by this function
+ * and chip_id is returned in unified format.
+ *
+ * chip_id contains serial, which is returned here in little-endian order.
+ *
+ * @return: 0 on success or -errno on failure
+ */
+int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id);
+
enum {
REBOOT_REASON_COLD = 0,
REBOOT_REASON_NORMAL = 1,
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6b2bb5a..24c8139 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,10 +16,11 @@
*/
tst x0, x0 // this is "b #0x84" in ARM
b reset
- .space 0x7c
+ .space 0x78
+ .word fel_stash - .
- .word 0xe28f0070 // add r0, pc, #112 // @(fel_stash - .)
- .word 0xe59f106c // ldr r1, [pc, #108] // fel_stash - .
+ .word 0xe24f000c // sub r0, pc, #12 // @(fel_stash - .)
+ .word 0xe51f1010 // ldr r1, [pc, #-16] // fel_stash - .
.word 0xe0800001 // add r0, r0, r1
.word 0xe580d000 // str sp, [r0]
.word 0xe580e004 // str lr, [r0, #4]
@@ -54,7 +55,6 @@
#else
.word CONFIG_TEXT_BASE
#endif
- .word fel_stash - .
#else
/* normal execution */
b reset
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index ca37184..2fd0740 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -448,6 +448,11 @@
#define LVS_OUTPUT_POLARITY_LOW BIT(28)
#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
+/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */
+#define H_PULSE0_ENABLE BIT(8)
+#define H_PULSE1_ENABLE BIT(10)
+#define H_PULSE2_ENABLE BIT(12)
+
/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
#define CURSOR_ENABLE BIT(16)
#define SOR_ENABLE BIT(25)
@@ -504,6 +509,22 @@
DATA_ORDER_BLUE_RED,
};
+/* DC_DISP_DISP_COLOR_CONTROL 0x430 */
+#define DITHER_CONTROL_DISABLE (0 << 8)
+#define DITHER_CONTROL_ORDERED (2 << 8)
+#define DITHER_CONTROL_ERRDIFF (3 << 8)
+enum {
+ BASE_COLOR_SIZE_666,
+ BASE_COLOR_SIZE_111,
+ BASE_COLOR_SIZE_222,
+ BASE_COLOR_SIZE_333,
+ BASE_COLOR_SIZE_444,
+ BASE_COLOR_SIZE_555,
+ BASE_COLOR_SIZE_565,
+ BASE_COLOR_SIZE_332,
+ BASE_COLOR_SIZE_888,
+};
+
/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
#define DE_SELECT_SHIFT 0
#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
@@ -570,8 +591,27 @@
#define V_DDA_INC_SHIFT 16
#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
+#define DC_POLL_TIMEOUT_MS 50
+#define DC_N_WINDOWS 5
+#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
+
+#define PULSE_MODE_NORMAL (0 << 3)
+#define PULSE_MODE_ONE_CLOCK (1 << 3)
+#define PULSE_POLARITY_HIGH (0 << 4)
+#define PULSE_POLARITY_LOW (1 << 4)
+#define PULSE_QUAL_ALWAYS (0 << 6)
+#define PULSE_QUAL_VACTIVE (2 << 6)
+#define PULSE_QUAL_VACTIVE1 (3 << 6)
+#define PULSE_LAST_START_A (0 << 8)
+#define PULSE_LAST_END_A (1 << 8)
+#define PULSE_LAST_START_B (2 << 8)
+#define PULSE_LAST_END_B (3 << 8)
+#define PULSE_LAST_START_C (4 << 8)
+#define PULSE_LAST_END_C (5 << 8)
+#define PULSE_LAST_START_D (6 << 8)
+#define PULSE_LAST_END_D (7 << 8)
+
-#define DC_POLL_TIMEOUT_MS 50
-#define DC_N_WINDOWS 5
-#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
+#define PULSE_START(x) (((x) & 0xfff) << 0)
+#define PULSE_END(x) (((x) & 0xfff) << 16)
#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 4b6e841..9a5cc93 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -34,41 +34,41 @@
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_DISABLE = 0,
PMUX_PIN_LOCK_ENABLE,
+ PMUX_PIN_LOCK_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_DISABLE = 0,
PMUX_PIN_OD_ENABLE,
+ PMUX_PIN_OD_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_DISABLE = 0,
PMUX_PIN_IO_RESET_ENABLE,
+ PMUX_PIN_IO_RESET_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_NORMAL = 0,
PMUX_PIN_RCV_SEL_HIGH,
+ PMUX_PIN_RCV_SEL_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
enum pmux_pin_e_io_hv {
- PMUX_PIN_E_IO_HV_DEFAULT = 0,
- PMUX_PIN_E_IO_HV_NORMAL,
+ PMUX_PIN_E_IO_HV_NORMAL = 0,
PMUX_PIN_E_IO_HV_HIGH,
+ PMUX_PIN_E_IO_HV_DEFAULT,
};
#endif
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 8c8579e..9598851 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -467,14 +467,14 @@
[PMUX_FUNC_DAP3] = "dap3",
[PMUX_FUNC_DAP4] = "dap4",
[PMUX_FUNC_DAP5] = "dap5",
- [PMUX_FUNC_DISPA] = "dispa",
- [PMUX_FUNC_DISPB] = "dispb",
+ [PMUX_FUNC_DISPA] = "displaya",
+ [PMUX_FUNC_DISPB] = "displayb",
[PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
[PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
[PMUX_FUNC_GMI] = "gmi",
[PMUX_FUNC_GMI_INT] = "gmi_int",
[PMUX_FUNC_HDMI] = "hdmi",
- [PMUX_FUNC_I2C] = "i2c",
+ [PMUX_FUNC_I2C] = "i2c1",
[PMUX_FUNC_I2C2] = "i2c2",
[PMUX_FUNC_I2C3] = "i2c3",
[PMUX_FUNC_IDE] = "ide",
diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S
index e21b54f..003d5f8 100644
--- a/arch/arm/lib/crt0_aarch64_efi.S
+++ b/arch/arm/lib/crt0_aarch64_efi.S
@@ -144,6 +144,7 @@
IMAGE_SCN_CNT_INITIALIZED_DATA)
.align 12
+ .globl _start
_start:
stp x29, x30, [sp, #-32]!
mov x29, sp
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 91b0fe1..1e7de5c 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -143,6 +143,7 @@
IMAGE_SCN_CNT_INITIALIZED_DATA)
.align 12
+ .globl _start
_start:
stmfd sp!, {r0-r2, lr}
diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c
index 1f672ee..d78d704 100644
--- a/arch/arm/lib/image.c
+++ b/arch/arm/lib/image.c
@@ -28,6 +28,13 @@
uint32_t res5;
};
+bool booti_is_valid(const void *img)
+{
+ const struct Image_header *ih = img;
+
+ return ih->magic == le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC);
+}
+
int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
bool force_reloc)
{
@@ -39,7 +46,7 @@
ih = (struct Image_header *)map_sysmem(image, 0);
- if (ih->magic != le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC)) {
+ if (!booti_is_valid(ih)) {
puts("Bad Linux ARM64 Image magic!\n");
return 1;
}
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 9a43bed..257c14e 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -9,6 +9,8 @@
config IMX8
bool
select HAS_CAAM
+ imply CPU
+ imply CPU_IMX
config MU_BASE_SPL
hex "MU base address used in SPL"
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 89f2b50..31f2f00 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,6 +8,9 @@
select LTO
select ROM_UNIFIED_SECTIONS
select ARMV8_CRYPTO
+ imply CPU
+ imply CPU_IMX
+ imply IMX_TMU
config IMX8MQ
bool
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 85dc8b5..567e8e9 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1270,8 +1270,9 @@
}
}
+ /* Locate the optee node if it exists or create it. */
subpath = "optee";
- offs = fdt_add_subnode(fdt, offs, subpath);
+ offs = fdt_find_or_add_subnode(fdt, offs, subpath);
if (offs < 0) {
printf("Could not create %s node.\n", subpath);
return offs;
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 49220c0..1ccdb1c 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -8,8 +8,11 @@
config IMX9
bool
select BINMAN
+ select CPU
+ select CPU_IMX
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
+ imply IMX_TMU
config IMX93
bool
diff --git a/arch/arm/mach-imx/imx9/container.cfg b/arch/arm/mach-imx/imx9/container.cfg
index 91a9731..a018c36 100644
--- a/arch/arm/mach-imx/imx9/container.cfg
+++ b/arch/arm/mach-imx/imx9/container.cfg
@@ -12,4 +12,6 @@
IMAGE A55 bl31.bin 0x204E0000
#endif
IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
+#ifdef CONFIG_OPTEE
IMAGE A55 tee.bin 0x96000000
+#endif
diff --git a/arch/arm/mach-k3/j722s/Kconfig b/arch/arm/mach-k3/j722s/Kconfig
index 39d38ea..fe76d77 100644
--- a/arch/arm/mach-k3/j722s/Kconfig
+++ b/arch/arm/mach-k3/j722s/Kconfig
@@ -26,8 +26,26 @@
select BINMAN
imply SYS_K3_SPL_ATF
+config TARGET_J722S_A53_BEAGLEY_AI
+ bool "BeagleBoard.org BeagleY-AI running on A53"
+ select ARM64
+ select BINMAN
+ select OF_SYSTEM_SETUP
+
+config TARGET_J722S_R5_BEAGLEY_AI
+ bool "BeagleBoard.org BeagleY-AI running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
endchoice
source "board/ti/j722s/Kconfig"
+source "board/beagle/beagley-ai/Kconfig"
endif
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
index b4058f5..d3807dc 100644
--- a/arch/arm/mach-meson/board-info.c
+++ b/arch/arm/mach-meson/board-info.c
@@ -7,6 +7,7 @@
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <asm/types.h>
#include <dm.h>
#include <linux/bitfield.h>
#include <regmap.h>
@@ -125,12 +126,12 @@
return "Unknown";
}
-static unsigned int get_socinfo(void)
+u32 meson_get_socinfo(void)
{
struct regmap *regmap;
int nodeoffset, ret;
ofnode node;
- unsigned int socinfo;
+ u32 socinfo;
/* find the offset of compatible node */
nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
@@ -162,9 +163,9 @@
int checkboard(void)
{
- unsigned int socinfo;
+ u32 socinfo;
- socinfo = get_socinfo();
+ socinfo = meson_get_socinfo();
if (!socinfo)
return 0;
@@ -181,9 +182,9 @@
int meson_get_soc_rev(char *buff, size_t buff_len)
{
- unsigned int socinfo;
+ u32 socinfo;
- socinfo = get_socinfo();
+ socinfo = meson_get_socinfo();
if (!socinfo)
return -1;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 4d9f83d..b1f91ca 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -10,11 +10,13 @@
#include <regmap.h>
#include <sm.h>
#include <syscon.h>
+#include <asm/arch/boot.h>
#include <asm/arch/sm.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/ptrace.h>
#include <linux/bitops.h>
+#include <linux/compiler_attributes.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/bitfield.h>
@@ -76,31 +78,131 @@
return err;
}
-#define SM_CHIP_ID_LENGTH 119
-#define SM_CHIP_ID_OFFSET 4
-#define SM_CHIP_ID_SIZE 12
+/*
+ * Helps to handle two flavors of cpu_id layouts:
+ *
+ * - in-register view (value read from cpu_id reg, a.k.a. socinfo):
+ * +-----------+------------+------------+------------+
+ * | family_id | package_id | chip_rev | layout_rev |
+ * +-----------+------------+------------+------------+
+ * | 31 24 | 23 16 | 15 8 | 7 0 |
+ * +-----------+------------+------------+------------+
+ *
+ * - in-efuse view (value, residing inside efuse/shmem data usually for
+ * chip_id v2. Chip_id v1 does not contain cpu_id value inside efuse
+ * data (i.e. in chip_id_efuse)):
+ * +-----------+------------+------------+------------+
+ * | family_id | chip_rev | package_id | layout_rev |
+ * +-----------+------------+------------+------------+
+ * | 31 24 | 23 16 | 15 8 | 7 0 |
+ * +-----------+------------+------------+------------+
+ */
+enum {
+ /* In-register view of cpu_id */
+ CPU_ID_REG_MAJOR, /* 31-24 bits */
+ CPU_ID_REG_PACK, /* 23-16 bits */
+ CPU_ID_REG_MINOR, /* 15-8 bits */
+ CPU_ID_REG_MISC, /* 7-0 bits */
-int meson_sm_get_serial(void *buffer, size_t size)
+ /* In-efuse view of cpu_id */
+ CPU_ID_MAJOR = CPU_ID_REG_MAJOR,
+ CPU_ID_PACK = CPU_ID_REG_MINOR,
+ CPU_ID_MINOR = CPU_ID_REG_PACK,
+ CPU_ID_MISC = CPU_ID_REG_MISC,
+};
+
+/*
+ * This is a beginning chunk of the whole efuse storage area, containing
+ * data related to chip_id only
+ */
+struct chip_id_efuse {
+ u32 version;
+ u8 raw[MESON_CHIP_ID_SZ]; /* payload */
+} __packed;
+
+static void meson_sm_serial_reverse(u8 serial[SM_SERIAL_SIZE])
+{
+ for (int i = 0; i < SM_SERIAL_SIZE / 2; i++) {
+ int k = SM_SERIAL_SIZE - 1 - i;
+
+ swap(serial[i], serial[k]);
+ }
+}
+
+int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id)
{
struct udevice *dev;
+ union meson_cpu_id socinfo;
struct pt_regs regs = { 0 };
- u8 id_buffer[SM_CHIP_ID_LENGTH];
+ struct chip_id_efuse chip_id_efuse;
int err;
dev = meson_get_sm_device();
if (IS_ERR(dev))
return PTR_ERR(dev);
- err = sm_call_read(dev, id_buffer, SM_CHIP_ID_LENGTH,
+ /*
+ * Request v2. If not supported by secure monitor, then v1 should be
+ * returned.
+ */
+ regs.regs[1] = 2;
+
+ err = sm_call_read(dev, &chip_id_efuse, sizeof(chip_id_efuse),
MESON_SMC_CMD_CHIP_ID_GET, ®s);
- if (err < 0)
- pr_err("Failed to read serial number (%d)\n", err);
+ if (err < 0) {
+ pr_err("Failed to read chip_id (%d)\n", err);
+ return err;
+ }
- memcpy(buffer, id_buffer + SM_CHIP_ID_OFFSET, size);
+ if (chip_id_efuse.version == 2) {
+ memcpy((u8 *)chip_id, chip_id_efuse.raw,
+ sizeof(struct meson_sm_chip_id));
+ return 0;
+ }
+
+ /*
+ * Legacy chip_id (v1) read out, transform data
+ * to expected order format (little-endian)
+ */
+ memcpy(chip_id->serial, chip_id_efuse.raw, sizeof(chip_id->serial));
+ meson_sm_serial_reverse(chip_id->serial);
+
+ socinfo.val = meson_get_socinfo();
+ if (!socinfo.val)
+ return -ENODEV;
+
+ chip_id->cpu_id = (union meson_cpu_id){
+ .raw[CPU_ID_MAJOR] = socinfo.raw[CPU_ID_REG_MAJOR],
+ .raw[CPU_ID_PACK] = socinfo.raw[CPU_ID_REG_PACK],
+ .raw[CPU_ID_MINOR] = socinfo.raw[CPU_ID_REG_MINOR],
+ .raw[CPU_ID_MISC] = socinfo.raw[CPU_ID_REG_MISC],
+ };
return 0;
}
+int meson_sm_get_serial(void *buffer, size_t size)
+{
+ struct meson_sm_chip_id chip_id;
+ int ret;
+
+ if (size < SM_SERIAL_SIZE)
+ return -EINVAL;
+
+ ret = meson_sm_get_chip_id(&chip_id);
+ if (ret)
+ return ret;
+
+ /*
+ * The order of serial inside chip_id and serial which function must
+ * return does not match: stick here to big-endian for backward
+ * compatibility.
+ */
+ meson_sm_serial_reverse(chip_id.serial);
+ memcpy(buffer, chip_id.serial, sizeof(chip_id.serial));
+ return ret;
+}
+
#define AO_SEC_SD_CFG15 0xfc
#define REBOOT_REASON_MASK GENMASK(15, 12)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 2ef936a..deae4d3 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -88,7 +88,29 @@
return 0;
}
-static void qcom_parse_memory(const void *fdt)
+/**
+ * The generic memory parsing code in U-Boot lacks a few things that we
+ * need on Qualcomm:
+ *
+ * 1. It sets gd->ram_size and gd->ram_base to represent a single memory block
+ * 2. setup_dest_addr() later relocates U-Boot to ram_base + ram_size, the end
+ * of that first memory block.
+ *
+ * This results in all memory beyond U-Boot being unusable in Linux when booting
+ * with EFI.
+ *
+ * Since the ranges in the memory node may be out of order, the only way for us
+ * to correctly determine the relocation address for U-Boot is to parse all
+ * memory regions and find the highest valid address.
+ *
+ * We can't use fdtdec_setup_memory_banksize() since it stores the result in
+ * gd->bd, which is not yet allocated.
+ *
+ * @fdt: FDT blob to parse /memory node from
+ *
+ * Return: 0 on success or -ENODATA if /memory node is missing or incomplete
+ */
+static int qcom_parse_memory(const void *fdt)
{
int offset;
const fdt64_t *memory;
@@ -97,16 +119,12 @@
int i, j, banks;
offset = fdt_path_offset(fdt, "/memory");
- if (offset < 0) {
- log_err("No memory node found in device tree!\n");
- return;
- }
+ if (offset < 0)
+ return -ENODATA;
memory = fdt_getprop(fdt, offset, "reg", &memsize);
- if (!memory) {
- log_err("No memory configuration was provided by the previous bootloader!\n");
- return;
- }
+ if (!memory)
+ return -ENODATA;
banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS);
@@ -119,7 +137,6 @@
for (i = 0, j = 0; i < banks * 2; i += 2, j++) {
prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]);
prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]);
- /* SM8650 boards sometimes have empty regions! */
if (!prevbl_ddr_banks[j].size) {
j--;
continue;
@@ -127,13 +144,16 @@
ram_end = max(ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size);
}
+ if (!banks || !prevbl_ddr_banks[0].size)
+ return -ENODATA;
+
/* Sort our RAM banks -_- */
qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp);
gd->ram_base = prevbl_ddr_banks[0].start;
gd->ram_size = ram_end - gd->ram_base;
- debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n",
- gd->ram_base, gd->ram_size, ram_end);
+
+ return 0;
}
static void show_psci_version(void)
@@ -142,24 +162,56 @@
arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+ /* Some older SoCs like MSM8916 don't always support PSCI */
+ if ((int)res.a0 == PSCI_RET_NOT_SUPPORTED)
+ return;
+
debug("PSCI: v%ld.%ld\n",
PSCI_VERSION_MAJOR(res.a0),
PSCI_VERSION_MINOR(res.a0));
}
+/**
+ * Most MSM8916 devices in the wild shipped without PSCI support, but the
+ * upstream DTs pretend that PSCI exists. If that situation is detected here,
+ * the /psci node is deleted. This is done very early to ensure the PSCI
+ * firmware driver doesn't bind (which then binds a sysreset driver that won't
+ * work).
+ */
+static void qcom_psci_fixup(void *fdt)
+{
+ int offset, ret;
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if ((int)res.a0 != PSCI_RET_NOT_SUPPORTED)
+ return;
+
+ offset = fdt_path_offset(fdt, "/psci");
+ if (offset < 0)
+ return;
+
+ debug("Found /psci DT node on device with no PSCI. Deleting.\n");
+ ret = fdt_del_node(fdt, offset);
+ if (ret)
+ log_err("Failed to delete /psci node: %d\n", ret);
+}
+
/* We support booting U-Boot with an internal DT when running as a first-stage bootloader
* or for supporting quirky devices where it's easier to leave the downstream DT in place
* to improve ABL compatibility. Otherwise, we use the DT provided by ABL.
*/
int board_fdt_blob_setup(void **fdtp)
{
- struct fdt_header *fdt;
+ struct fdt_header *external_fdt, *internal_fdt;
bool internal_valid, external_valid;
- int ret = 0;
+ int ret = -ENODATA;
- fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
- external_valid = fdt && !fdt_check_header(fdt);
- internal_valid = !fdt_check_header(*fdtp);
+ internal_fdt = (struct fdt_header *)*fdtp;
+ external_fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
+ external_valid = external_fdt && !fdt_check_header(external_fdt);
+ internal_valid = !fdt_check_header(internal_fdt);
/*
* There is no point returning an error here, U-Boot can't do anything useful in this situation.
@@ -167,31 +219,42 @@
*/
if (!internal_valid && !external_valid)
panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
- (phys_addr_t)fdt);
+ (phys_addr_t)external_fdt);
+
+ /* Prefer memory information from internal DT if it's present */
+ if (internal_valid)
+ ret = qcom_parse_memory(internal_fdt);
+
+ if (ret < 0 && external_valid) {
+ /* No internal FDT or it lacks a proper /memory node.
+ * The previous bootloader handed us something, let's try that.
+ */
+ if (internal_valid)
+ debug("No memory info in internal FDT, falling back to external\n");
+
+ ret = qcom_parse_memory(external_fdt);
+ }
+
+ if (ret < 0)
+ panic("No valid memory ranges found!\n");
+
+ debug("ram_base = %#011lx, ram_size = %#011llx\n",
+ gd->ram_base, gd->ram_size);
if (internal_valid) {
debug("Using built in FDT\n");
ret = -EEXIST;
} else {
debug("Using external FDT\n");
- /* So we can use it before returning */
- *fdtp = fdt;
+ *fdtp = external_fdt;
+ ret = 0;
}
- /*
- * Parse the /memory node while we're here,
- * this makes it easy to do other things early.
- */
- qcom_parse_memory(*fdtp);
+ qcom_psci_fixup(*fdtp);
return ret;
}
-void reset_cpu(void)
-{
- psci_system_reset();
-}
-
/*
* Some Qualcomm boards require GPIO configuration when switching USB modes.
* Support setting this configuration via pinctrl state.
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ba1b154..ab43239 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -457,6 +457,9 @@
select SUN50I_GEN_H6
imply OF_UPSTREAM
+config MACH_SUN50I_A133
+ bool "sun50i (Allwinner A133)"
+
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -713,16 +716,10 @@
config SYS_CLK_FREQ
default 408000000 if MACH_SUNIV
- default 1008000000 if MACH_SUN4I
- default 1008000000 if MACH_SUN5I
- default 1008000000 if MACH_SUN6I
- default 912000000 if MACH_SUN7I
default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
- default 1008000000 if MACH_SUN8I
- default 1008000000 if MACH_SUN9I
default 888000000 if MACH_SUN50I_H6
- default 1008000000 if MACH_SUN50I_H616
- default 1008000000 if MACH_SUN8I_R528
+ default 912000000 if MACH_SUN7I
+ default 1008000000
config SYS_CONFIG_NAME
default "suniv" if MACH_SUNIV
@@ -1131,10 +1128,6 @@
The used address is "bdaddr" if set, and "ethaddr" with the LSB
flipped elsewise.
-source "board/sunxi/Kconfig"
-
-endif
-
config CHIP_DIP_SCAN
bool "Enable DIPs detection for CHIP board"
select SUPPORT_EXTENSION_SCAN
@@ -1143,3 +1136,7 @@
select W1_EEPROM
select W1_EEPROM_DS24XXX
select CMD_EXTENSION
+
+source "board/sunxi/Kconfig"
+
+endif
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index b424a78..359513d 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -147,15 +147,20 @@
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
CCM_PLL6_CTRL_P0_SHIFT) + 1;
- m = 1;
} else {
div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
- if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
- m = 4;
- else
- m = 2;
}
+ /*
+ * The factors encoded in the register describe the doubled clock
+ * frequency, expect for the H6, where it's the quadrupled frequency.
+ * Compensate for that here.
+ */
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ m = 4;
+ else
+ m = 2;
+
return 24000000U * n / m / div1 / div2;
}
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index b3554cc..cd9d321 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -1360,36 +1360,94 @@
panic("This DRAM setup is currently not supported.\n");
}
+static void mctl_write_pattern(void)
+{
+ unsigned int i;
+ u32 *ptr, val;
+
+ ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i < 16; ptr++, i++) {
+ if (i & 1)
+ val = ~(ulong)ptr;
+ else
+ val = (ulong)ptr;
+ writel(val, ptr);
+ }
+}
+
+static bool mctl_check_pattern(ulong offset)
+{
+ unsigned int i;
+ u32 *ptr, val;
+
+ ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+ for (i = 0; i < 16; ptr++, i++) {
+ if (i & 1)
+ val = ~(ulong)ptr;
+ else
+ val = (ulong)ptr;
+ if (val != *(ptr + offset / 4))
+ return false;
+ }
+
+ return true;
+}
+
static void mctl_auto_detect_dram_size(const struct dram_para *para,
struct dram_config *config)
{
- unsigned int shift;
+ unsigned int shift, cols, rows;
+ u32 buffer[16];
/* max. config for columns, but not rows */
config->cols = 11;
config->rows = 13;
mctl_core_init(para, config);
+ /*
+ * Store content so it can be restored later. This is important
+ * if controller was already initialized and holds any data
+ * which is important for restoring system.
+ */
+ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+ mctl_write_pattern();
+
shift = config->bus_full_width + 1;
/* detect column address bits */
- for (config->cols = 8; config->cols < 11; config->cols++) {
- if (mctl_mem_matches(1ULL << (config->cols + shift)))
+ for (cols = 8; cols < 11; cols++) {
+ if (mctl_check_pattern(1ULL << (cols + shift)))
break;
}
- debug("detected %u columns\n", config->cols);
+ debug("detected %u columns\n", cols);
+
+ /* restore data */
+ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
/* reconfigure to make sure that all active rows are accessible */
- config->rows = 18;
+ config->cols = 8;
+ config->rows = 17;
mctl_core_init(para, config);
+ /* store data again as it might be moved */
+ memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+ mctl_write_pattern();
+
/* detect row address bits */
shift = config->bus_full_width + 4 + config->cols;
- for (config->rows = 13; config->rows < 18; config->rows++) {
- if (mctl_mem_matches(1ULL << (config->rows + shift)))
+ for (rows = 13; rows < 17; rows++) {
+ if (mctl_check_pattern(1ULL << (rows + shift)))
break;
}
- debug("detected %u rows\n", config->rows);
+ debug("detected %u rows\n", rows);
+
+ /* restore data again */
+ memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+ config->cols = cols;
+ config->rows = rows;
}
static unsigned long mctl_calc_size(const struct dram_config *config)
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 8e19324..c77dc53 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -16,33 +16,10 @@
#include <power/pmic.h>
#include <asm/arch/pmic_bus.h>
-#define AXP152_I2C_ADDR 0x30
-
-#define AXP209_I2C_ADDR 0x34
-#define AXP717_I2C_ADDR 0x34
-
-#define AXP305_I2C_ADDR 0x36
-#define AXP313_I2C_ADDR 0x36
-
#define AXP221_CHIP_ADDR 0x68
#if CONFIG_IS_ENABLED(PMIC_AXP)
static struct udevice *pmic;
-#else
-static int pmic_i2c_address(void)
-{
- if (IS_ENABLED(CONFIG_AXP152_POWER))
- return AXP152_I2C_ADDR;
- if (IS_ENABLED(CONFIG_AXP305_POWER))
- return AXP305_I2C_ADDR;
- if (IS_ENABLED(CONFIG_AXP313_POWER))
- return AXP313_I2C_ADDR;
- if (IS_ENABLED(CONFIG_AXP717_POWER))
- return AXP717_I2C_ADDR;
-
- /* Other AXP2xx and AXP8xx variants */
- return AXP209_I2C_ADDR;
-}
#endif
int pmic_bus_init(void)
@@ -88,7 +65,7 @@
if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
- return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
+ return i2c_read(CONFIG_AXP_I2C_ADDRESS, reg, 1, data, 1);
#endif
}
@@ -102,7 +79,7 @@
if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
- return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
+ return i2c_write(CONFIG_AXP_I2C_ADDRESS, reg, 1, &data, 1);
#endif
}
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
index 33e55d4..422007c 100644
--- a/arch/arm/mach-sunxi/rmr_switch.S
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -16,7 +16,9 @@
@ the machine code must be inserted as verbatim .word statements into the
@ beginning of the AArch64 U-Boot code.
@ To get the encoded bytes, use:
-@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}gcc -c -Iinclude -Iarch/arm/include \
+@ -D__ASSEMBLY__ -DCONFIG_ARM64 \
+@ -o rmr_switch.o arch/arm/mach-sunxi/rmr_switch.S
@ ${CROSS_COMPILE}objdump -d rmr_switch.o
@
@ The resulting words should be inserted into the U-Boot file at
@@ -29,14 +31,40 @@
#include <config.h>
.text
+ b start32 // this is "tst x0, x0" in AArch64
+ .word 0x14000047 // this is "b reset" in AArch64
-#ifndef CONFIG_SUN50I_GEN_H6
- ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register
+ .space 0x78 // gap distance set by the common
+ // encoding of the first instruction
+fel_stash_addr:
+ .word fel_stash - . // distance to fel_stash buffer
+
+start32:
+ adr r0, fel_stash_addr // absolute location of fel_stash_addr
+ ldr r1, fel_stash_addr // distance to actual fel_stash
+ add r0, r0, r1 // real address of fel_stash
+
+ /* save the current state as needed by the BROM for a later return */
+ str sp, [r0]
+ str lr, [r0, #4]
+ mrs lr, CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, cr1, cr0, 0 // SCTLR
+ str lr, [r0, #12]
+ mrc p15, 0, lr, cr12, cr0, 0 // VBAR
+ str lr, [r0, #16]
+
+ ldr r1, =CONFIG_SUNXI_RVBAR_ADDRESS
+ ldr r0, =SUNXI_SRAMC_BASE
+ ldr r0, [r0, #36] // SRAM_VER_REG
+ ands r0, r0, #0xff
+ ldrne r1, =CONFIG_SUNXI_RVBAR_ALTERNATIVE
+#ifdef CONFIG_XPL_BUILD
+ ldr r0, =CONFIG_SPL_TEXT_BASE
#else
- ldr r1, =0x09010040 @ MMIO mapped RVBAR[0] register
+ ldr r0, =CONFIG_TEXT_BASE
#endif
- ldr r0, =0x57aA7add @ start address, to be replaced
- str r0, [r1]
+ str r0, [r1] // store start address in RVBAR
dsb sy
isb sy
mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index e0f054a..b5099ce 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -32,6 +32,10 @@
bool "Lenovo Ideapad Yoga 11 board"
select BOARD_LATE_INIT
+config TARGET_OUYA
+ bool "Ouya Game Console board"
+ select BOARD_LATE_INIT
+
config TARGET_QC750
bool "Wexler QC750 board"
select BOARD_LATE_INIT
@@ -64,6 +68,7 @@
source "board/htc/endeavoru/Kconfig"
source "board/asus/grouper/Kconfig"
source "board/lenovo/ideapad-yoga-11/Kconfig"
+source "board/ouya/ouya/Kconfig"
source "board/wexler/qc750/Kconfig"
source "board/microsoft/surface-rt/Kconfig"
source "board/avionic-design/tec-ng/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 819250f..abdaffb 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -133,7 +133,6 @@
#define CFG_FM_PLAT_CLK_DIV 1
#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV
#define CFG_SYS_FM_MURAM_SIZE 0x30000
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@@ -146,7 +145,6 @@
#define CFG_SYS_FM1_CLK 0
#define CFG_QBMAN_CLK_DIV 1
#define CFG_SYS_FM_MURAM_SIZE 0x30000
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@@ -165,7 +163,6 @@
#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
#define CFG_SYS_FM1_CLK 0
#define CFG_SYS_FM_MURAM_SIZE 0x28000
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#elif defined(CONFIG_ARCH_C29X)
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig
index d9cd8dc..14201df 100644
--- a/arch/riscv/cpu/k1/Kconfig
+++ b/arch/riscv/cpu/k1/Kconfig
@@ -13,6 +13,7 @@
imply RISCV_ACLINT if RISCV_MMODE
imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
+ imply DM_RESET
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 0405fac..ceb916b 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -82,8 +82,9 @@
};
};
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
description = "NAME";
type = "flat_dt";
compression = "none";
@@ -92,9 +93,12 @@
};
configurations {
+
+#ifndef CONFIG_MULTI_DTB_FIT
default = "conf-1";
+#endif
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@conf-SEQ {
#else
conf-1 {
@@ -115,7 +119,7 @@
#endif
#endif /* CONFIG_OPTEE */
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
fdt = "fdt-SEQ";
#endif
};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 8a7386b..6fac247 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -46,20 +46,6 @@
#clock-cells = <0>;
};
- eth_csrclk: eth-csrclk {
- compatible = "fixed-clock";
- clock-frequency = <250000000>;
- clock-output-names = "eth_csrclk";
- #clock-cells = <0x0>;
- };
-
- eth_ptpclk: eth-ptpclk {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "eth_ptpclk";
- #clock-cells = <0x0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 514be45..7c0f1b9 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -327,7 +327,7 @@
ranges;
uart0: serial@d4017000 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
interrupts = <42>;
clock-frequency = <14857000>;
@@ -337,7 +337,7 @@
};
uart2: serial@d4017100 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017100 0x0 0x100>;
interrupts = <44>;
clock-frequency = <14857000>;
@@ -347,7 +347,7 @@
};
uart3: serial@d4017200 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017200 0x0 0x100>;
interrupts = <45>;
clock-frequency = <14857000>;
@@ -357,7 +357,7 @@
};
uart4: serial@d4017300 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017300 0x0 0x100>;
interrupts = <46>;
clock-frequency = <14857000>;
@@ -367,7 +367,7 @@
};
uart5: serial@d4017400 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017400 0x0 0x100>;
interrupts = <47>;
clock-frequency = <14857000>;
@@ -377,7 +377,7 @@
};
uart6: serial@d4017500 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017500 0x0 0x100>;
interrupts = <48>;
clock-frequency = <14857000>;
@@ -387,7 +387,7 @@
};
uart7: serial@d4017600 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017600 0x0 0x100>;
interrupts = <49>;
clock-frequency = <14857000>;
@@ -397,7 +397,7 @@
};
uart8: serial@d4017700 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017700 0x0 0x100>;
interrupts = <50>;
clock-frequency = <14857000>;
@@ -407,7 +407,7 @@
};
uart9: serial@d4017800 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017800 0x0 0x100>;
interrupts = <51>;
clock-frequency = <14857000>;
@@ -447,7 +447,7 @@
};
sec_uart1: serial@f0612000 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xf0612000 0x0 0x100>;
interrupts = <43>;
clock-frequency = <14857000>;
@@ -455,5 +455,20 @@
reg-io-width = <4>;
status = "reserved"; /* for TEE usage */
};
+
+ reset: reset-controller@d4050000 {
+ compatible = "spacemit,k1-reset";
+ reg = <0x0 0xd4050000 0x0 0x209c>,
+ <0x0 0xd4282800 0x0 0x400>,
+ <0x0 0xd4015000 0x0 0x1000>,
+ <0x0 0xd4090000 0x0 0x1000>,
+ <0x0 0xd4282c00 0x0 0x400>,
+ <0x0 0xd8440000 0x0 0x98>,
+ <0x0 0xc0000000 0x0 0x4280>,
+ <0x0 0xf0610000 0x0 0x20>;
+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
+ #reset-cells = <1>;
+ status = "disabled";
+ };
};
};
\ No newline at end of file
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 4cce001..05787bd 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -13,82 +13,6 @@
};
&binman {
- itb {
- fit {
- images {
- fdt-jh7110-milkv-mars {
- description = "jh7110-milkv-mars";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb";
- };
- };
-
- fdt-jh7110-pine64-star64 {
- description = "jh7110-pine64-star64";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb";
- };
- };
-
- fdt-jh7110-starfive-visionfive-2-v1.2a {
- description = "jh7110-starfive-visionfive-2-v1.2a";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
- };
- };
-
- fdt-jh7110-starfive-visionfive-2-v1.3b {
- description = "jh7110-starfive-visionfive-2-v1.3b";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
- };
- };
- };
-
- configurations {
- conf-jh7110-milkv-mars {
- description = "jh7110-milkv-mars";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-milkv-mars";
- };
-
- conf-jh7110-pine64-star64 {
- description = "jh7110-pine64-star64";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-pine64-star64";
- };
-
- conf-jh7110-starfive-visionfive-2-v1.2a {
- description = "jh7110-starfive-visionfive-2-v1.2a";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a";
- };
-
- conf-jh7110-starfive-visionfive-2-v1.3b {
- description = "jh7110-starfive-visionfive-2-v1.3b";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b";
- };
- };
- };
- };
-
spl-img {
filename = "spl/u-boot-spl.bin.normal.out";
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
index 90aa2f8..be2a1e0 100644
--- a/arch/riscv/include/asm/arch-jh7110/gpio.h
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -63,6 +63,11 @@
GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+#define SYS_IOMUX_DIN_DISABLED(gpi)\
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+ ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
#define SYS_IOMUX_SET_DS(gpio, ds) \
clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
index 9eacbe4..f170e4b 100644
--- a/arch/riscv/lib/crt0_riscv_efi.S
+++ b/arch/riscv/lib/crt0_riscv_efi.S
@@ -179,6 +179,7 @@
IMAGE_SCN_CNT_INITIALIZED_DATA)
.align 12
+ .globl _start
_start:
addi sp, sp, -(SIZE_LONG * 3)
SAVE_LONG(a0, 0)
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
index a82f48e..859326c 100644
--- a/arch/riscv/lib/image.c
+++ b/arch/riscv/lib/image.c
@@ -32,6 +32,13 @@
uint32_t res4; /* reserved */
};
+bool booti_is_valid(const void *img)
+{
+ const struct linux_image_h *lhdr = img;
+
+ return lhdr->magic == LINUX_RISCV_IMAGE_MAGIC;
+}
+
int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
bool force_reloc)
{
@@ -39,7 +46,7 @@
lhdr = (struct linux_image_h *)map_sysmem(image, 0);
- if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
+ if (!booti_is_valid(lhdr)) {
puts("Bad Linux RISCV Image magic!\n");
return -EINVAL;
}
diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
index 44ba8b5..8ed9237 100644
--- a/arch/sandbox/lib/bootm.c
+++ b/arch/sandbox/lib/bootm.c
@@ -89,3 +89,8 @@
return 1;
}
+
+bool booti_is_valid(const void *img)
+{
+ return false;
+}
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 8b54260..4ed6d8d 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -10,6 +10,8 @@
#include <asm/bootparam.h>
#include <asm/e820.h>
+struct bootm_info;
+
/* linux i386 zImage/bzImage header. Offsets relative to
* the start of the image */
@@ -42,65 +44,28 @@
ZBOOT_STATE_COUNT = 5,
};
-/**
- * struct zboot_state - Current state of the boot
- *
- * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already
- * been loaded and does not exist (as a cohesive whole) in memory
- * @bzimage_size: Size of the bzImage, or 0 to detect this
- * @initrd_addr: Address of the initial ramdisk, or 0 if none
- * @initrd_size: Size of the initial ramdisk, or 0 if none
- * @load_address: Address where the bzImage is moved before booting, either
- * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
- * This is set up when loading the zimage
- * @base_ptr: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
- * This is set up when loading the zimage
- * @cmdline: Environment variable containing the 'override' command line, or
- * NULL to use the one in the setup block
- */
-struct zboot_state {
- ulong bzimage_addr;
- ulong bzimage_size;
- ulong initrd_addr;
- ulong initrd_size;
- ulong load_address;
- struct boot_params *base_ptr;
- const char *cmdline;
-};
-
-extern struct zboot_state state;
-
/**
- * zimage_dump() - Dump information about a zimage
- *
- * @base_ptr: Pointer to the boot parameters
- * @show_cmdline: true to show the kernel command line
- */
-void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
-
-/**
* zboot_load() - Load a zimage
*
* Load the zimage into the correct place
*
* Return: 0 if OK, -ve on error
*/
-int zboot_load(void);
+int zboot_load(struct bootm_info *bmi);
/**
* zboot_setup() - Set up the zboot image reeady for booting
*
* Return: 0 if OK, -ve on error
*/
-int zboot_setup(void);
+int zboot_setup(struct bootm_info *bmi);
/**
* zboot_go() - Start the image
*
* Return: 0 if OK, -ve on error
*/
-int zboot_go(void);
+int zboot_go(struct bootm_info *bmi);
/**
* load_zimage() - Load a zImage or bzImage
@@ -139,6 +104,7 @@
*
* Record information about a zimage so it can be booted
*
+ * @bmi: Bootm information
* @bzimage_addr: Address of the bzImage to boot
* @bzimage_size: Size of the bzImage, or 0 to detect this
* @initrd_addr: Address of the initial ramdisk, or 0 if none
@@ -149,14 +115,17 @@
* @cmdline: Environment variable containing the 'override' command line, or
* NULL to use the one in the setup block
*/
-void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr,
- ulong initrd_size, ulong base_addr, const char *cmdline);
+void zboot_start(struct bootm_info *bmi, ulong bzimage_addr, ulong bzimage_size,
+ ulong initrd_addr, ulong initrd_size, ulong base_addr,
+ const char *cmdline);
/**
* zboot_info() - Show simple info about a zimage
*
- * Shows wherer the kernel was loaded and also the setup base
+ * Shows where the kernel was loaded and also the setup base
+ *
+ * @bmi: Bootm information
*/
-void zboot_info(void);
+void zboot_info(struct bootm_info *bmi);
#endif
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 2eece34..ba7a008 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -55,9 +55,6 @@
#define COMMAND_LINE_SIZE 2048
-/* Current state of the boot */
-struct zboot_state state;
-
static void build_command_line(char *command_line, int auto_boot)
{
char *env_command_line;
@@ -366,13 +363,13 @@
return 0;
}
-int zboot_load(void)
+int zboot_load(struct bootm_info *bmi)
{
struct boot_params *base_ptr;
int ret;
- if (state.base_ptr) {
- struct boot_params *from = (struct boot_params *)state.base_ptr;
+ if (bmi->base_ptr) {
+ struct boot_params *from = (struct boot_params *)bmi->base_ptr;
base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE;
log_debug("Building boot_params at 0x%8.8lx\n",
@@ -380,41 +377,41 @@
memset(base_ptr, '\0', sizeof(*base_ptr));
base_ptr->hdr = from->hdr;
} else {
- base_ptr = load_zimage((void *)state.bzimage_addr, state.bzimage_size,
- &state.load_address);
+ base_ptr = load_zimage((void *)bmi->bzimage_addr,
+ bmi->bzimage_size, &bmi->load_address);
if (!base_ptr) {
puts("## Kernel loading failed ...\n");
return -EINVAL;
}
}
- state.base_ptr = base_ptr;
+ bmi->base_ptr = base_ptr;
- ret = env_set_hex("zbootbase", map_to_sysmem(state.base_ptr));
+ ret = env_set_hex("zbootbase", map_to_sysmem(bmi->base_ptr));
if (!ret)
- ret = env_set_hex("zbootaddr", state.load_address);
+ ret = env_set_hex("zbootaddr", bmi->load_address);
if (ret)
return ret;
return 0;
}
-int zboot_setup(void)
+int zboot_setup(struct bootm_info *bmi)
{
- struct boot_params *base_ptr = state.base_ptr;
+ struct boot_params *base_ptr = bmi->base_ptr;
int ret;
ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
- 0, state.initrd_addr, state.initrd_size,
- (ulong)state.cmdline);
+ 0, bmi->initrd_addr, bmi->initrd_size,
+ (ulong)bmi->cmdline);
if (ret)
return -EINVAL;
return 0;
}
-int zboot_go(void)
+int zboot_go(struct bootm_info *bmi)
{
- struct boot_params *params = state.base_ptr;
+ struct boot_params *params = bmi->base_ptr;
struct setup_header *hdr = ¶ms->hdr;
bool image_64bit;
ulong entry;
@@ -422,7 +419,7 @@
disable_interrupts();
- entry = state.load_address;
+ entry = bmi->load_address;
image_64bit = false;
if (IS_ENABLED(CONFIG_X86_RUN_64BIT) &&
(hdr->xloadflags & XLF_KERNEL_64)) {
@@ -430,30 +427,43 @@
}
/* we assume that the kernel is in place */
- ret = boot_linux_kernel((ulong)state.base_ptr, entry, image_64bit);
+ ret = boot_linux_kernel((ulong)bmi->base_ptr, entry, image_64bit);
return ret;
}
-int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size,
- ulong base, char *cmdline)
+int zboot_run(struct bootm_info *bmi)
{
int ret;
- zboot_start(addr, size, initrd, initrd_size, base, cmdline);
- ret = zboot_load();
+ ret = zboot_load(bmi);
if (ret)
return log_msg_ret("ld", ret);
- ret = zboot_setup();
+ ret = zboot_setup(bmi);
if (ret)
return log_msg_ret("set", ret);
- ret = zboot_go();
+ ret = zboot_go(bmi);
if (ret)
return log_msg_ret("go", ret);
return -EFAULT;
}
+int zboot_run_args(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+ ulong base, char *cmdline)
+{
+ struct bootm_info bmi;
+ int ret;
+
+ bootm_init(&bmi);
+ zboot_start(&bmi, addr, size, initrd, initrd_size, base, cmdline);
+ ret = zboot_run(&bmi);
+ if (ret)
+ return log_msg_ret("zra", ret);
+
+ return 0;
+}
+
static void print_num(const char *name, ulong value)
{
printf("%-20s: %lx\n", name, value);
@@ -555,12 +565,13 @@
printf("\n");
}
-void zimage_dump(struct boot_params *base_ptr, bool show_cmdline)
+void zimage_dump(struct bootm_info *bmi, bool show_cmdline)
{
+ struct boot_params *base_ptr;
struct setup_header *hdr;
- const char *version;
int i;
+ base_ptr = bmi->base_ptr;
printf("Setup located at %p:\n\n", base_ptr);
print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr);
@@ -595,10 +606,14 @@
print_num("Real mode switch", hdr->realmode_swtch);
print_num("Start sys seg", hdr->start_sys_seg);
print_num("Kernel version", hdr->kernel_version);
- version = zimage_get_kernel_version(base_ptr,
- (void *)state.bzimage_addr);
- if (version)
- printf(" @%p: %s\n", version, version);
+ if (bmi->bzimage_addr) {
+ const char *version;
+
+ version = zimage_get_kernel_version(base_ptr,
+ (void *)bmi->bzimage_addr);
+ if (version)
+ printf(" @%p: %s\n", version, version);
+ }
print_num("Type of loader", hdr->type_of_loader);
show_loader(hdr);
print_num("Load flags", hdr->loadflags);
@@ -639,25 +654,24 @@
print_num("Kernel info offset", hdr->kernel_info_offset);
}
-void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr,
- ulong initrd_size, ulong base_addr, const char *cmdline)
+void zboot_start(struct bootm_info *bmi, ulong bzimage_addr, ulong bzimage_size,
+ ulong initrd_addr, ulong initrd_size, ulong base_addr,
+ const char *cmdline)
{
- memset(&state, '\0', sizeof(state));
-
- state.bzimage_size = bzimage_size;
- state.initrd_addr = initrd_addr;
- state.initrd_size = initrd_size;
+ bmi->bzimage_size = bzimage_size;
+ bmi->initrd_addr = initrd_addr;
+ bmi->initrd_size = initrd_size;
if (base_addr) {
- state.base_ptr = map_sysmem(base_addr, 0);
- state.load_address = bzimage_addr;
+ bmi->base_ptr = map_sysmem(base_addr, 0);
+ bmi->load_address = bzimage_addr;
} else {
- state.bzimage_addr = bzimage_addr;
+ bmi->bzimage_addr = bzimage_addr;
}
- state.cmdline = cmdline;
+ bmi->cmdline = cmdline;
}
-void zboot_info(void)
+void zboot_info(struct bootm_info *bmi)
{
printf("Kernel loaded at %08lx, setup_base=%p\n",
- state.load_address, state.base_ptr);
+ bmi->load_address, bmi->base_ptr);
}
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12013aa..93ee5b7 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -100,9 +100,6 @@
int ret;
arch_cpu_init();
-
- init_uart_clk(1);
-
timer_init();
/* Clear the BSS. */
@@ -114,8 +111,6 @@
hang();
}
- preloader_console_init();
-
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
@@ -124,6 +119,7 @@
hang();
}
+ preloader_console_init();
enable_tzc380();
power_init_board();
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index f03841e..e91d3fd 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -111,8 +111,6 @@
/* Claiming pwm pins prevents LCD flicker during startup*/
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
- init_uart_clk(1);
-
return 0;
}
diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
index 30d577f..027fae3 100644
--- a/board/beacon/imx8mp/spl.c
+++ b/board/beacon/imx8mp/spl.c
@@ -50,7 +50,7 @@
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
* set by ROM for ND VDD_SOC
*/
- if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
+ if (!IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
@@ -112,8 +112,6 @@
arch_cpu_init();
- init_uart_clk(1);
-
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
diff --git a/board/beagle/beagley-ai/Kconfig b/board/beagle/beagley-ai/Kconfig
new file mode 100644
index 0000000..bf95398
--- /dev/null
+++ b/board/beagle/beagley-ai/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_J722S_R5_BEAGLEY_AI || TARGET_J722S_A53_BEAGLEY_AI
+
+config SYS_BOARD
+ default "beagley-ai"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "beagley_ai"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J722S_R5_BEAGLEY_AI
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/beagle/beagley-ai/MAINTAINERS b/board/beagle/beagley-ai/MAINTAINERS
new file mode 100644
index 0000000..1623329
--- /dev/null
+++ b/board/beagle/beagley-ai/MAINTAINERS
@@ -0,0 +1,8 @@
+BEAGLEY-AI BOARD
+M: Robert Nelson <robertcnelson@gmail.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+F: board/beagle/beagley-ai/
+F: include/configs/beagley_ai.h
+F: configs/am67a_beagley_ai_r5_defconfig
+F: configs/am67a_beagley_ai_a53_defconfig
diff --git a/board/beagle/beagley-ai/Makefile b/board/beagle/beagley-ai/Makefile
new file mode 100644
index 0000000..0859354
--- /dev/null
+++ b/board/beagle/beagley-ai/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += beagley-ai.o
diff --git a/board/beagle/beagley-ai/beagley-ai.c b/board/beagle/beagley-ai/beagley-ai.c
new file mode 100644
index 0000000..9786f62
--- /dev/null
+++ b/board/beagle/beagley-ai/beagley-ai.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * https://www.beagleboard.org/boards/beagley-ai
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+#include <asm/arch/k3-ddr.h>
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+ env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_XPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ if (IS_ENABLED(CONFIG_K3_DDRSS)) {
+ if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
+ fixup_ddr_driver_for_ecc(spl_image);
+ } else {
+ fixup_memory_node(spl_image);
+ }
+}
+#endif
+
+#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+ char fdtfile[50];
+
+ snprintf(fdtfile, sizeof(fdtfile), "%s.dtb", CONFIG_DEFAULT_DEVICE_TREE);
+
+ env_set("fdtfile", fdtfile);
+
+ return 0;
+}
+#endif
diff --git a/board/beagle/beagley-ai/beagley-ai.env b/board/beagle/beagley-ai/beagley-ai.env
new file mode 100644
index 0000000..10d6203
--- /dev/null
+++ b/board/beagle/beagley-ai/beagley-ai.env
@@ -0,0 +1,21 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/mmc.env>
+
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+
+rproc_fw_binaries= 0 /lib/firmware/j722s-mcu-r5f0_0-fw 2 /lib/firmware/j722s-main-r5f0_0-fw 3 /lib/firmware/j722s-c71_0-fw 4 /lib/firmware/j722s-c71_1-fw
diff --git a/board/beagle/beagley-ai/board-cfg.yaml b/board/beagle/beagley-ai/board-cfg.yaml
new file mode 100644
index 0000000..f9a4c43
--- /dev/null
+++ b/board/beagle/beagley-ai/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J722S
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
diff --git a/board/beagle/beagley-ai/pm-cfg.yaml b/board/beagle/beagley-ai/pm-cfg.yaml
new file mode 100644
index 0000000..46b3ad2
--- /dev/null
+++ b/board/beagle/beagley-ai/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J722S
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
diff --git a/board/beagle/beagley-ai/rm-cfg.yaml b/board/beagle/beagley-ai/rm-cfg.yaml
new file mode 100644
index 0000000..e32beb8
--- /dev/null
+++ b/board/beagle/beagley-ai/rm-cfg.yaml
@@ -0,0 +1,1137 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J722S
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ -
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 20
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 22
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 38
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ -
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 1184
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 192
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+ reserved: 0
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 320
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+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
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+ reserved: 0
+ -
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+ type: 320
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+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 26
+ type: 384
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
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+ start_resource: 0
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+ reserved: 0
+ -
+ start_resource: 154
+ num_resource: 14
+ type: 1802
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 168
+ num_resource: 16
+ type: 1802
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 512
+ type: 1805
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 529
+ num_resource: 256
+ type: 1805
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 529
+ num_resource: 256
+ type: 1805
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 785
+ num_resource: 128
+ type: 1805
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 913
+ num_resource: 128
+ type: 1805
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 1041
+ num_resource: 128
+ type: 1805
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 1169
+ num_resource: 128
+ type: 1805
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 1297
+ num_resource: 239
+ type: 1805
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1807
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1808
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1809
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1810
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1812
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1813
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 9728
+ num_resource: 25
+ type: 1815
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10240
+ num_resource: 25
+ type: 1816
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 10752
+ num_resource: 25
+ type: 1817
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11264
+ num_resource: 25
+ type: 1818
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 11776
+ num_resource: 25
+ type: 1819
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 25
+ type: 1820
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1923
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 51200
+ num_resource: 80
+ type: 12738
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 12739
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 32
+ type: 12750
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 32
+ type: 12750
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12751
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 12769
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 12769
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 12770
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 12810
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 12810
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 2
+ type: 12810
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 18
+ type: 12810
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 12288
+ num_resource: 56
+ type: 12813
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 12344
+ num_resource: 48
+ type: 12813
+ host_id: 20
+ reserved: 0
+ -
+ start_resource: 12392
+ num_resource: 48
+ type: 12813
+ host_id: 22
+ reserved: 0
+ -
+ start_resource: 12440
+ num_resource: 64
+ type: 12813
+ host_id: 38
+ reserved: 0
+ -
+ start_resource: 1536
+ num_resource: 8
+ type: 12823
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2048
+ num_resource: 8
+ type: 12824
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2560
+ num_resource: 8
+ type: 12825
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 32
+ type: 12826
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 32
+ type: 12827
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 32
+ type: 12828
+ host_id: 128
+ reserved: 0
diff --git a/board/beagle/beagley-ai/sec-cfg.yaml b/board/beagle/beagley-ai/sec-cfg.yaml
new file mode 100644
index 0000000..a41374b3
--- /dev/null
+++ b/board/beagle/beagley-ai/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for J722S
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ -
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ -
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id: 0
+ otp_entry:
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ -
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/beagle/beagley-ai/tifs-rm-cfg.yaml b/board/beagle/beagley-ai/tifs-rm-cfg.yaml
new file mode 100644
index 0000000..4a2af0e
--- /dev/null
+++ b/board/beagle/beagley-ai/tifs-rm-cfg.yaml
@@ -0,0 +1,993 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J722S
+#
+
+---
+
+tifs-rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - #1
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #2
+ host_id: 20
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #3
+ host_id: 22
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #4
+ host_id: 30
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #5
+ host_id: 36
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #6
+ host_id: 38
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #7
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #8
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #9
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
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diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 4af3cbe..4275436 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -186,5 +186,7 @@
enum env_location env_get_location(enum env_operation op, int prio)
{
- return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
+ return prio ? ENVL_UNKNOWN : CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH,
+ (ENVL_SPI_FLASH),
+ (ENVL_NOWHERE));
}
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 012ac14..134dbfd 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -62,6 +62,7 @@
imply VIDEO_SIMPLE
imply PCIE_ECAM_GENERIC
imply DM_RNG
+ imply RNG_RISCV_ZKR
imply DM_RTC
imply RTC_GOLDFISH
imply SCSI
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index a214c04..67a10bb 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -110,11 +110,6 @@
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
}
- if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
- /* Set VDDQ to 1.1V from buck2 */
- pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
- }
-
/* set standby voltage to 0.65v */
if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
diff --git a/board/intel/agilex5-socdk/MAINTAINERS b/board/intel/agilex5-socdk/MAINTAINERS
index b696f78..30d8815 100644
--- a/board/intel/agilex5-socdk/MAINTAINERS
+++ b/board/intel/agilex5-socdk/MAINTAINERS
@@ -2,7 +2,9 @@
M: Tien Fong Chee <tien.fong.chee@intel.com>
M: Teik Heng Chong <teik.heng.chong@intel.com>
M: Jit Loon Lim <jit.loon.lim@intel.com>
+M: Dinesh Maniyam <dinesh.maniyam@intel.com>
S: Maintained
F: board/intel/agilex5-socdk/
F: include/configs/socfpga_agilex5_socdk.h
F: configs/socfpga_agilex5_defconfig
+F: configs/socfpga_agilex5_nand2_defconfig
diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig
new file mode 100644
index 0000000..6bab40c
--- /dev/null
+++ b/board/ouya/ouya/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OUYA
+
+config SYS_BOARD
+ default "ouya"
+
+config SYS_VENDOR
+ default "ouya"
+
+config SYS_CONFIG_NAME
+ default "ouya"
+
+endif
diff --git a/board/ouya/ouya/MAINTAINERS b/board/ouya/ouya/MAINTAINERS
new file mode 100644
index 0000000..7f664b2
--- /dev/null
+++ b/board/ouya/ouya/MAINTAINERS
@@ -0,0 +1,8 @@
+OUYA BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+M: Peter Geis <pgwipeout@gmail.com>
+S: Maintained
+F: board/ouya/ouya/
+F: configs/ouya_defconfig
+F: doc/board/ouya/ouya.rst
+F: include/configs/ouya.h
diff --git a/board/ouya/ouya/Makefile b/board/ouya/ouya/Makefile
new file mode 100644
index 0000000..d479ec8
--- /dev/null
+++ b/board/ouya/ouya/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2021
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_XPL_BUILD) += ouya-spl.o
+
+obj-y += ouya.o
diff --git a/board/ouya/ouya/ouya-spl.c b/board/ouya/ouya/ouya-spl.c
new file mode 100644
index 0000000..1f45853
--- /dev/null
+++ b/board/ouya/ouya/ouya-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * T30 Ouya SPL stage configuration
+ *
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2025
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR (0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR (0x60 << 1)
+#define TPS62361B_SET3_REG 0x03
+#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+ /* Set VDD_CORE to 1.200V. */
+ tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+ udelay(1000);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.0125V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+ udelay(1000);
+ tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+ udelay(10 * 1000);
+}
diff --git a/board/ouya/ouya/ouya.c b/board/ouya/ouya/ouya.c
new file mode 100644
index 0000000..6d6eb54
--- /dev/null
+++ b/board/ouya/ouya/ouya.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2025
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <fdt_support.h>
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove TrustZone nodes */
+ fdt_del_node_and_alias(blob, "/firmware");
+ fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+ return 0;
+}
+#endif
diff --git a/board/ouya/ouya/ouya.env b/board/ouya/ouya/ouya.env
new file mode 100644
index 0000000..6ec881b
--- /dev/null
+++ b/board/ouya/ouya/ouya.env
@@ -0,0 +1,12 @@
+#include <env/nvidia/prod_upd.env>
+
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_interface=usb
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_2=update bootloader=run flash_uboot
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index bc55117..65451a3 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -38,6 +38,17 @@
Support of I2C EEPROM based SoM detection. Supported
for PHYTEC AM62x boards.
+config PHYTEC_AM62A_SOM_DETECTION
+ bool "Support SoM detection for AM62Ax PHYTEC platforms"
+ depends on (TARGET_PHYCORE_AM62AX_A53 || TARGET_PHYCORE_AM62AX_R5) && \
+ PHYTEC_SOM_DETECTION
+ select SUPPORT_EXTENSION_SCAN
+ depends on SPL_I2C && DM_I2C
+ default y
+ help
+ Support of I2C EEPROM based SoM detection. Supported
+ for PHYTEC AM62Ax boards.
+
config PHYTEC_AM64_SOM_DETECTION
bool "Support SoM detection for AM64x PHYTEC platforms"
depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \
diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c
index 7930ab4..f5de5de 100644
--- a/board/phytec/common/am6_som_detection.c
+++ b/board/phytec/common/am6_som_detection.c
@@ -11,10 +11,12 @@
extern struct phytec_eeprom_data eeprom_data;
#if IS_ENABLED(CONFIG_PHYTEC_AM62_SOM_DETECTION) || \
+ IS_ENABLED(CONFIG_PHYTEC_AM62A_SOM_DETECTION) || \
IS_ENABLED(CONFIG_PHYTEC_AM64_SOM_DETECTION)
/* Check if the SoM is actually one of the following products:
* - phyCORE-AM62x
+ * - phyCORE-AM62Ax
* - phyCORE-AM64x
*
* Returns 0 in case it's a known SoM. Otherwise, returns -1.
@@ -41,6 +43,9 @@
if (som == PHYTEC_AM62X_SOM && soc_is_am62x())
return 0;
+ if (som == PHYTEC_AM62AX_SOM && soc_is_am62ax())
+ return 0;
+
if (som == PHYTEC_AM64X_SOM && soc_is_am64x())
return 0;
diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h
index c5c6e17..0b3c9c8 100644
--- a/board/phytec/common/am6_som_detection.h
+++ b/board/phytec/common/am6_som_detection.h
@@ -11,6 +11,7 @@
#define EEPROM_ADDR 0x50
#define PHYTEC_AM62X_SOM 71
+#define PHYTEC_AM62AX_SOM 75
#define PHYTEC_AM64X_SOM 72
#define PHYTEC_EEPROM_VALUE_X 0x21
#define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 9d83345..7d2146d 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -48,7 +48,7 @@
* Note: Currently, eMMC hardware partitions are not differentiated; Updates
* are always applied to the first boot partition.
*/
-void configure_capsule_updates(void)
+static void configure_capsule_updates(void)
{
static char dfu_string[128] = { 0 };
const char *dfu_raw = "tiboot3.bin raw 0x0 0x400 mmcpart 1;"
diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS
index 3e4e2fe..7c8a29b 100644
--- a/board/phytec/phycore_am62ax/MAINTAINERS
+++ b/board/phytec/phycore_am62ax/MAINTAINERS
@@ -10,5 +10,6 @@
F: board/phytec/phycore_am62ax/
F: configs/phycore_am62ax_a53_defconfig
F: configs/phycore_am62ax_r5_defconfig
+F: configs/phycore_am62ax_r5_usbdfu_defconfig
F: include/configs/phycore_am62ax.h
F: doc/board/phytec/phycore-am62ax.rst
diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env
index 77c5ea8..a0eacd1 100644
--- a/board/phytec/phycore_am62ax/phycore_am62ax.env
+++ b/board/phytec/phycore_am62ax/phycore_am62ax.env
@@ -1,3 +1,8 @@
+#include <env/phytec/k3_dfu.env>
+#include <env/phytec/k3_mmc.env>
+#include <env/phytec/k3_net.env>
+#include <env/phytec/k3_spi.env>
+
fdtaddr=0x88000000
loadaddr=0x82000000
scriptaddr=0x80000000
@@ -12,3 +17,9 @@
mmcpart=1
console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x02800000
+
+get_cmd=tftp
+
+spi_fdt_addr=0x700000
+spi_image_addr=0x800000
+spi_ramdisk_addr=0x1e00000
diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS
index 670c747..8f2b806 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -12,4 +12,5 @@
F: configs/phycore_am62x_r5_usbdfu_defconfig
F: include/configs/phycore_am62x.h
F: doc/board/phytec/phycore-am62x.rst
+F: doc/board/phytec/k3-common.rst
F: board/phytec/common/k3
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index 024f38e..5c48e85 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -1,4 +1,4 @@
-#include <env/ti/k3_dfu.env>
+#include <env/phytec/k3_dfu.env>
#include <env/phytec/k3_mmc.env>
#include <env/phytec/k3_net.env>
#include <env/phytec/k3_spi.env>
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index bdf9e97..caf9cb0 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -45,7 +45,6 @@
config PHYCORE_IMX8MP_RAM_SIZE_8GB
bool "8GB RAM"
- select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
help
Set RAM size fix to 8GB for phyCORE-i.MX8MP.
Only 2GHz RAMs are supported.
@@ -54,7 +53,6 @@
config PHYCORE_IMX8MP_RAM_FREQ_FIX
bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
- default false
help
RAM frequency is automatic being detected with the help of
the EEPROM introspection data. Set RAM frequency to a fix value
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index aa39afa..70d3c35 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -193,6 +193,21 @@
DTB_DIR "bcm2712-rpi-5-b.dtb",
true,
},
+ [0x18] = {
+ "Compute Module 5",
+ DTB_DIR "bcm2712-rpi-cm5-cm5io.dtb",
+ true,
+ },
+ [0x19] = {
+ "500",
+ DTB_DIR "bcm2712-rpi-500.dtb",
+ true,
+ },
+ [0x1A] = {
+ "Compute Module 5 Lite",
+ DTB_DIR "bcm2712-rpi-cm5l-cm5io.dtb",
+ true,
+ },
};
static const struct rpi_model rpi_models_old_scheme[] = {
@@ -579,8 +594,14 @@
/* kernel address randomisation seed as provided by the firmware */
copy_property(fdt, fw_fdt, "/chosen", "kaslr-seed");
+ /* warnings from the firmware (if any) */
+ copy_property(fdt, fw_fdt, "/chosen", "user-warnings");
+
/* address of the PHY device as provided by the firmware */
copy_property(fdt, fw_fdt, "ethernet0/mdio@e14/ethernet-phy@1", "reg");
+
+ /* Bluetooth device address as provided by the firmware */
+ copy_property(fdt, fw_fdt, "/soc/serial@7e201000/bluetooth", "local-bd-address");
}
int ft_board_setup(void *blob, struct bd_info *bd)
@@ -589,11 +610,13 @@
update_fdt_from_fw(blob, (void *)fw_dtb_pointer);
- node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
- if (node < 0)
- fdt_simplefb_add_node(blob);
- else
- fdt_simplefb_enable_and_mem_rsv(blob);
+ if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) {
+ node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
+ if (node < 0)
+ fdt_simplefb_add_node(blob);
+ else
+ fdt_simplefb_enable_and_mem_rsv(blob);
+ }
#ifdef CONFIG_EFI_LOADER
/* Reserve the spin table */
diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile
index 347be5c..5e51b69 100644
--- a/board/renesas/common/Makefile
+++ b/board/renesas/common/Makefile
@@ -1,6 +1,4 @@
#
-# board/renesas/whitehawk/Makefile
-#
# Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c
index 52a0639..f7d129b 100644
--- a/board/renesas/common/gen4-common.c
+++ b/board/renesas/common/gen4-common.c
@@ -7,11 +7,13 @@
#include <asm/arch/renesas.h>
#include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/processor.h>
#include <asm/system.h>
+#include <image.h>
#include <linux/errno.h>
#define RST_BASE 0xE6160000 /* Domain0 */
@@ -88,3 +90,127 @@
{
return 0;
}
+
+/* R-Car Gen4 TFA BL31 handoff structure and handling. */
+struct param_header {
+ u8 type;
+ u8 version;
+ u16 size;
+ u32 attr;
+};
+
+struct tfa_image_info {
+ struct param_header h;
+ uintptr_t image_base;
+ u32 image_size;
+ u32 image_max_size;
+};
+
+struct aapcs64_params {
+ u64 arg0;
+ u64 arg1;
+ u64 arg2;
+ u64 arg3;
+ u64 arg4;
+ u64 arg5;
+ u64 arg6;
+ u64 arg7;
+};
+
+struct entry_point_info {
+ struct param_header h;
+ uintptr_t pc;
+ u32 spsr;
+ struct aapcs64_params args;
+};
+
+struct bl2_to_bl31_params_mem {
+ struct tfa_image_info bl32_image_info;
+ struct tfa_image_info bl33_image_info;
+ struct entry_point_info bl33_ep_info;
+ struct entry_point_info bl32_ep_info;
+};
+
+/* Default jump address, return to U-Boot */
+#define BL33_BASE 0x44100000
+/* Custom parameters address passed to TFA by ICUMXA loader */
+#define PARAMS_BASE 0x46422200
+
+/* Usually such a structure is produced by ICUMXA and passed in at 0x46422200 */
+static const struct bl2_to_bl31_params_mem blinfo_template = {
+ .bl33_ep_info.h.type = 1, /* PARAM_EP */
+ .bl33_ep_info.h.version = 2, /* Version 2 */
+ .bl33_ep_info.h.size = sizeof(struct entry_point_info),
+ .bl33_ep_info.h.attr = 0x81, /* Executable | Non-Secure */
+ .bl33_ep_info.spsr = 0x2c9, /* Mode=EL2, SP=ELX, Exceptions=OFF */
+ .bl33_ep_info.pc = BL33_BASE,
+
+ .bl33_image_info.h.type = 1, /* PARAM_EP */
+ .bl33_image_info.h.version = 2, /* Version 2 */
+ .bl33_image_info.h.size = sizeof(struct image_info),
+ .bl33_image_info.h.attr = 0,
+ .bl33_image_info.image_base = BL33_BASE,
+};
+
+static bool tfa_bl31_image_loaded;
+static ulong tfa_bl31_image_addr;
+
+static void tfa_bl31_image_process(ulong image, size_t size)
+{
+ /* Custom parameters address passed to TFA by ICUMXA loader */
+ struct bl2_to_bl31_params_mem *blinfo = (struct bl2_to_bl31_params_mem *)PARAMS_BASE;
+
+ /* Not in EL3, do nothing. */
+ if (current_el() != 3)
+ return;
+
+ /* Clear a page and copy template */
+ memset((void *)PARAMS_BASE, 0, PAGE_SIZE);
+ memcpy(blinfo, &blinfo_template, sizeof(*blinfo));
+ tfa_bl31_image_addr = image;
+ tfa_bl31_image_loaded = true;
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TFA_BL31, tfa_bl31_image_process);
+
+void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr,
+ u64 arg4, u64 entry_point, u64 es_flag)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(void);
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t)(void *)tfa_bl31_image_addr;
+ struct bl2_to_bl31_params_mem *blinfo =
+ (struct bl2_to_bl31_params_mem *)PARAMS_BASE;
+
+ /* Not in EL3, do nothing. */
+ if (current_el() != 3)
+ return;
+
+ /*
+ * Destination address in arch/arm/cpu/armv8/transition.S
+ * right past the first bl in armv8_switch_to_el2() to let
+ * the rest of U-Boot pre-Linux code run. The code does run
+ * without stack pointer!
+ */
+ const u64 ep = ((u64)(uintptr_t)&armv8_switch_to_el2) + 4;
+
+ /* If TFA BL31 was not part of the fitImage, do regular boot. */
+ if (!tfa_bl31_image_loaded)
+ return;
+
+ /*
+ * Set up kernel entry point and parameters:
+ * x0 is FDT address, x1..x3 must be 0
+ */
+ blinfo->bl33_ep_info.pc = ep;
+ blinfo->bl33_ep_info.args.arg0 = args;
+ blinfo->bl33_ep_info.args.arg1 = mach_nr;
+ blinfo->bl33_ep_info.args.arg2 = fdt_addr;
+ blinfo->bl33_ep_info.args.arg3 = arg4;
+ blinfo->bl33_ep_info.args.arg4 = entry_point;
+ blinfo->bl33_ep_info.args.arg5 = es_flag;
+ blinfo->bl33_image_info.image_base = ep;
+
+ /* Jump to TFA BL31 */
+ image_entry();
+}
diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c
index e46ef0a..ebfefab 100644
--- a/board/renesas/common/gen4-spl.c
+++ b/board/renesas/common/gen4-spl.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * R-Car Gen4 Cortex-R52 SPL
+ * R-Car Gen4 SPL
*
* Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 22afd76..13a4893 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -103,6 +103,9 @@
JH7110_CLK_CPU_ROOT_MASK,
BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+ /* Set USB overcurrent overflow pin disable */
+ SYS_IOMUX_DIN_DISABLED(2);
+
ret = spl_board_init_f();
if (ret) {
debug("spl_board_init_f init failed: %d\n", ret);
@@ -118,6 +121,10 @@
product_id = get_product_id_from_eeprom();
+ /* Strip off prefix */
+ if (strncmp(name, "starfive/", 9))
+ return -EINVAL;
+ name += 9;
if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
if ((version == 'b' || version == 'B') &&
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index c7a2205..ac9cefc 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -563,7 +563,8 @@
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \
- defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER
+ defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER || \
+ defined CONFIG_AXP803_POWER
power_failed = axp_init();
if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
@@ -581,6 +582,8 @@
#endif
#ifdef CONFIG_AXP_DCDC2_VOLT
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
+#endif
+#ifdef CONFIG_AXP_DCDC3_VOLT
power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
#endif
#ifdef CONFIG_AXP_DCDC4_VOLT
diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml
index dc445a4..73da85e 100644
--- a/board/ti/am62px/rm-cfg.yaml
+++ b/board/ti/am62px/rm-cfg.yaml
@@ -244,7 +244,7 @@
subhdr:
magic: 0x7B25
size: 8
- resasg_entries_size: 1048
+ resasg_entries_size: 1112
reserved: 0
resasg_entries:
-
@@ -303,31 +303,55 @@
reserved: 0
-
start_resource: 0
+ num_resource: 2
+ type: 1676
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 1676
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 1676
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 1676
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 4
num_resource: 18
type: 1677
host_id: 12
reserved: 0
-
- start_resource: 18
+ start_resource: 22
num_resource: 6
type: 1677
host_id: 35
reserved: 0
-
- start_resource: 18
+ start_resource: 22
num_resource: 6
type: 1677
host_id: 36
reserved: 0
-
- start_resource: 24
+ start_resource: 28
num_resource: 2
type: 1677
host_id: 30
reserved: 0
-
- start_resource: 26
- num_resource: 6
+ start_resource: 30
+ num_resource: 2
type: 1677
host_id: 128
reserved: 0
@@ -387,31 +411,55 @@
reserved: 0
-
start_resource: 0
+ num_resource: 2
+ type: 1695
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 1695
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 1695
+ host_id: 36
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 1695
+ host_id: 30
+ reserved: 0
+ -
+ start_resource: 4
num_resource: 18
type: 1696
host_id: 12
reserved: 0
-
- start_resource: 18
+ start_resource: 22
num_resource: 6
type: 1696
host_id: 35
reserved: 0
-
- start_resource: 18
+ start_resource: 22
num_resource: 6
type: 1696
host_id: 36
reserved: 0
-
- start_resource: 24
+ start_resource: 28
num_resource: 2
type: 1696
host_id: 30
reserved: 0
-
- start_resource: 26
- num_resource: 6
+ start_resource: 30
+ num_resource: 2
type: 1696
host_id: 128
reserved: 0
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index ec0f223..e0a7c66 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -36,6 +36,7 @@
#include <dwc_ahsata.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
+#include <i2c.h>
#include <imx_thermal.h>
#include <micrel.h>
#include <miiphy.h>
@@ -77,6 +78,8 @@
#define APALIS_IMX6_SATA_INIT_RETRIES 10
+#define I2C_PWR 1
+
int dram_init(void)
{
/* use the DDR controllers configured size */
@@ -689,6 +692,32 @@
return 0;
}
+static bool is_som_variant_1_2(void)
+{
+ struct udevice *bus;
+ struct udevice *i2c_dev;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PWR, &bus);
+ if (ret) {
+ printf("Failed to get I2C_PWR\n");
+ return false;
+ }
+
+ /* V1.2 uses the TLA2024 at 0x49 instead of the STMPE811 at 0x41 */
+ ret = dm_i2c_probe(bus, 0x49, 0, &i2c_dev);
+
+ return (bool)!ret;
+}
+
+static void select_dt_from_module_version(void)
+{
+ if (is_som_variant_1_2())
+ env_set("variant", "-v1.2");
+ else
+ env_set("variant", "");
+}
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@@ -696,6 +725,8 @@
char env_str[256];
u32 rev;
+ select_dt_from_module_version();
+
rev = get_board_revision();
snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
env_set("board_rev", env_str);
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 64cf99e..69a3c5f 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -33,6 +33,7 @@
#include <cpu.h>
#include <dm/platform_data/serial_mxc.h>
#include <fsl_esdhc_imx.h>
+#include <i2c.h>
#include <imx_thermal.h>
#include <miiphy.h>
#include <netdev.h>
@@ -71,6 +72,8 @@
#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+#define I2C_PWR 1
+
int dram_init(void)
{
/* use the DDR controllers configured size */
@@ -609,6 +612,32 @@
return 0;
}
+static bool is_som_variant_1_2(void)
+{
+ struct udevice *bus;
+ struct udevice *i2c_dev;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PWR, &bus);
+ if (ret) {
+ printf("Failed to get I2C_PWR\n");
+ return false;
+ }
+
+ /* V1.2 uses the TLA2024 at 0x49 instead of the STMPE811 at 0x41 */
+ ret = dm_i2c_probe(bus, 0x49, 0, &i2c_dev);
+
+ return (bool)!ret;
+}
+
+static void select_dt_from_module_version(void)
+{
+ if (is_som_variant_1_2())
+ env_set("variant", "-v1.2");
+ else
+ env_set("variant", "");
+}
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@@ -616,6 +645,8 @@
char env_str[256];
u32 rev;
+ select_dt_from_module_version();
+
rev = get_board_revision();
snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
env_set("board_rev", env_str);
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index a1c4711..7b2eecb 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -112,13 +112,6 @@
#define CORE_VOLTAGE 0x80000000
#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4)
-#if IS_ENABLED(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
- fixup_memory_node(spl_image);
-}
-#endif
-
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
diff --git a/boot/Makefile b/boot/Makefile
index 34bac26..f1e4444 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -10,7 +10,7 @@
obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o
-obj-$(CONFIG_PXE_UTILS) += pxe_utils.o
+obj-$(CONFIG_PXE_UTILS) += bootm.o pxe_utils.o
endif
diff --git a/boot/bootm.c b/boot/bootm.c
index 854ac7e..8a1aac7 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -146,7 +146,7 @@
/* check image type, for FIT images get FIT kernel node */
*os_data = *os_len = 0;
buf = map_sysmem(img_addr, 0);
- switch (genimg_get_format(buf)) {
+ switch (genimg_get_format_comp(buf)) {
#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
printf("## Booting kernel from Legacy Image at %08lx ...\n",
@@ -227,6 +227,9 @@
break;
}
#endif
+ case IMAGE_FORMAT_BOOTI:
+ *os_data = img_addr;
+ break;
default:
bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
return -EPROTOTYPE;
@@ -286,6 +289,35 @@
return ret;
}
+static int found_booti_os(enum image_comp_t comp)
+{
+ images.os.load = images.os.image_start;
+ images.os.type = IH_TYPE_KERNEL;
+ images.os.os = IH_OS_LINUX;
+ images.os.comp = comp;
+ if (IS_ENABLED(CONFIG_RISCV_SMODE))
+ images.os.arch = IH_ARCH_RISCV;
+ else if (IS_ENABLED(CONFIG_ARM64))
+ images.os.arch = IH_ARCH_ARM64;
+
+ log_debug("load %lx start %lx len %lx ep %lx os %x comp %x\n",
+ images.os.load, images.os.image_start, images.os.image_len,
+ images.ep, images.os.os, images.os.comp);
+ if (comp != IH_COMP_NONE) {
+ images.os.load = env_get_hex("kernel_comp_addr_r", 0);
+ images.os.image_len = env_get_ulong("kernel_comp_size", 16, 0);
+ if (!images.os.load || !images.os.image_len) {
+ puts("kernel_comp_addr_r or kernel_comp_size is not provided!\n");
+ return -ENOTSUPP;
+ }
+ if (lmb_reserve(images.os.load, images.os.image_len, LMB_NONE)
+ < 0)
+ return -EXDEV;
+ }
+
+ return 0;
+}
+
/**
* bootm_find_os(): Find the OS to boot
*
@@ -390,7 +422,28 @@
}
break;
#endif
+ case IMAGE_FORMAT_BOOTI:
+ if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
+ if (found_booti_os(IH_COMP_NONE))
+ return 1;
+ ep_found = true;
+ break;
+ }
+ fallthrough;
default:
+ /* any compressed image is probably a booti image */
+ if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
+ int comp;
+
+ comp = image_decomp_type(os_hdr, 2);
+ if (comp != IH_COMP_NONE) {
+ if (found_booti_os(comp))
+ return 1;
+ ep_found = true;
+ }
+ break;
+ }
+
puts("ERROR: unknown image format type!\n");
return 1;
}
@@ -541,6 +594,7 @@
static int bootm_find_other(ulong img_addr, const char *conf_ramdisk,
const char *conf_fdt)
{
+ log_debug("find_other type %x os %x\n", images.os.type, images.os.os);
if ((images.os.type == IH_TYPE_KERNEL ||
images.os.type == IH_TYPE_KERNEL_NOLOAD ||
images.os.type == IH_TYPE_MULTI) &&
@@ -629,15 +683,17 @@
debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n",
req_size, load, image_len);
}
+ log_debug("load_os load %lx image_start %lx image_len %lx\n", load,
+ image_start, image_len);
load_buf = map_sysmem(load, 0);
image_buf = map_sysmem(os.image_start, image_len);
err = image_decomp(os.comp, load, os.image_start, os.type,
- load_buf, image_buf, image_len,
- CONFIG_SYS_BOOTM_LEN, &load_end);
+ load_buf, image_buf, image_len, bootm_len(),
+ &load_end);
if (err) {
- err = handle_decomp_error(os.comp, load_end - load,
- CONFIG_SYS_BOOTM_LEN, err);
+ err = handle_decomp_error(os.comp, load_end - load, bootm_len(),
+ err);
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
@@ -1110,6 +1166,10 @@
states |= BOOTM_STATE_RAMDISK;
states |= extra_states;
+ log_debug("cmd '%s' states %x addr_img '%s' conf_ramdisk '%s' conf_fdt '%s' images %p\n",
+ cmd, states, bmi->addr_img, bmi->conf_ramdisk, bmi->conf_fdt,
+ bmi->images);
+
return bootm_run_states(bmi, states);
}
@@ -1127,7 +1187,9 @@
int booti_run(struct bootm_info *bmi)
{
- return boot_run(bmi, "booti", 0);
+ return boot_run(bmi, "booti", BOOTM_STATE_START | BOOTM_STATE_FINDOS |
+ BOOTM_STATE_PRE_LOAD | BOOTM_STATE_FINDOTHER |
+ BOOTM_STATE_LOADOS);
}
int bootm_boot_start(ulong addr, const char *cmdline)
@@ -1166,7 +1228,8 @@
{
memset(bmi, '\0', sizeof(struct bootm_info));
bmi->boot_progress = true;
- if (IS_ENABLED(CONFIG_CMD_BOOTM))
+ if (IS_ENABLED(CONFIG_CMD_BOOTM) || IS_ENABLED(CONFIG_CMD_BOOTZ) ||
+ IS_ENABLED(CONFIG_CMD_BOOTI) || IS_ENABLED(CONFIG_PXE_UTILS))
bmi->images = &images;
}
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index c7b862e..ea4c9ed 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -446,9 +446,9 @@
}
if (IS_ENABLED(CONFIG_X86)) {
- ret = zboot_run(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
- map_to_sysmem(bflow->x86_setup),
- bflow->cmdline);
+ ret = zboot_run_args(map_to_sysmem(bflow->buf), bflow->size, 0,
+ 0, map_to_sysmem(bflow->x86_setup),
+ bflow->cmdline);
} else {
ret = bootm_boot_start(map_to_sysmem(bflow->buf),
bflow->cmdline);
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 49efeec..92f2f53 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -18,6 +18,7 @@
#include <dm/ofnode.h>
#include <linux/ctype.h>
#include <linux/types.h>
+#include <linux/sizes.h>
#include <asm/global_data.h>
#include <asm/unaligned.h>
#include <linux/libfdt.h>
@@ -464,7 +465,6 @@
do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
}
-#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
/*
* fdt_pack_reg - pack address and size array into the "reg"-suitable stream
*/
@@ -493,6 +493,7 @@
return p - (char *)buf;
}
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
#if CONFIG_NR_DRAM_BANKS > 4
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
@@ -2222,3 +2223,39 @@
}
return 1;
}
+
+int fdt_fixup_pmem_region(void *fdt, u64 pmem_start, u64 pmem_size)
+{
+ char node_name[32];
+ int nodeoffset, len;
+ int err;
+ u8 tmp[4 * 16]; /* Up to 64-bit address + 64-bit size */
+
+ if (!IS_ALIGNED(pmem_start, SZ_2M) ||
+ !IS_ALIGNED(pmem_start + pmem_size, SZ_2M)) {
+ printf("Start and end address must be 2MiB aligned\n");
+ return -1;
+ }
+
+ snprintf(node_name, sizeof(node_name), "pmem@%llx", pmem_start);
+ nodeoffset = fdt_find_or_add_subnode(fdt, 0, node_name);
+ if (nodeoffset < 0)
+ return nodeoffset;
+
+ err = fdt_setprop_string(fdt, nodeoffset, "compatible", "pmem-region");
+ if (err)
+ return err;
+ err = fdt_setprop_empty(fdt, nodeoffset, "volatile");
+ if (err)
+ return err;
+
+ len = fdt_pack_reg(fdt, tmp, &pmem_start, &pmem_size, 1);
+ err = fdt_setprop(fdt, nodeoffset, "reg", tmp, len);
+ if (err < 0) {
+ printf("WARNING: could not set pmem %s %s.\n", "reg",
+ fdt_strerror(err));
+ return err;
+ }
+
+ return 0;
+}
diff --git a/boot/image-board.c b/boot/image-board.c
index 514f8e6..a2bafba 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -234,21 +234,7 @@
&fit_uname_kernel);
}
-/**
- * genimg_get_format - get image format type
- * @img_addr: image start address
- *
- * genimg_get_format() checks whether provided address points to a valid
- * legacy or FIT image.
- *
- * New uImage format and FDT blob are based on a libfdt. FDT blob
- * may be passed directly or embedded in a FIT image. In both situations
- * genimg_get_format() must be able to dectect libfdt header.
- *
- * returns:
- * image format type or IMAGE_FORMAT_INVALID if no image is present
- */
-int genimg_get_format(const void *img_addr)
+enum image_fmt_t genimg_get_format(const void *img_addr)
{
if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
const struct legacy_img_hdr *hdr;
@@ -264,10 +250,24 @@
if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) &&
is_android_boot_image_header(img_addr))
return IMAGE_FORMAT_ANDROID;
+ if (IS_ENABLED(CONFIG_CMD_BOOTI) &&
+ booti_is_valid(img_addr))
+ return IMAGE_FORMAT_BOOTI;
return IMAGE_FORMAT_INVALID;
}
+enum image_fmt_t genimg_get_format_comp(const void *img_addr)
+{
+ enum image_fmt_t fmt = genimg_get_format(img_addr);
+
+ if (IS_ENABLED(CONFIG_CMD_BOOTI) && fmt == IMAGE_FORMAT_INVALID &&
+ image_decomp_type(img_addr, 2) != IH_COMP_NONE)
+ fmt = IMAGE_FORMAT_BOOTI;
+
+ return fmt;
+}
+
/**
* fit_has_config - check if there is a valid FIT configuration
* @images: pointer to the bootm command headers structure
@@ -364,7 +364,7 @@
* check image type, for FIT images get FIT node.
*/
buf = map_sysmem(rd_addr, 0);
- switch (genimg_get_format(buf)) {
+ switch (genimg_get_format_comp(buf)) {
case IMAGE_FORMAT_LEGACY:
if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
const struct legacy_img_hdr *rd_hdr;
@@ -434,6 +434,10 @@
done = true;
}
break;
+ case IMAGE_FORMAT_BOOTI:
+ break;
+ case IMAGE_FORMAT_INVALID:
+ break;
}
if (!done) {
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 9d1598b..8f718ad 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -11,6 +11,7 @@
#include <command.h>
#include <fdt_support.h>
#include <fdtdec.h>
+#include <efi.h>
#include <env.h>
#include <errno.h>
#include <image.h>
@@ -649,6 +650,12 @@
if (!ft_verify_fdt(blob))
goto err;
+ if (CONFIG_IS_ENABLED(BLKMAP) && CONFIG_IS_ENABLED(EFI_LOADER)) {
+ fdt_ret = fdt_efi_pmem_setup(blob);
+ if (fdt_ret)
+ goto err;
+ }
+
/* after here we are using a livetree */
if (!of_live_active() && CONFIG_IS_ENABLED(EVENT)) {
struct event_ft_fixup fixup;
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index 82f217a..c606da9 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -7,6 +7,7 @@
#define LOG_CATEGORY LOGC_BOOT
#include <bootflow.h>
+#include <bootm.h>
#include <command.h>
#include <dm.h>
#include <env.h>
@@ -432,169 +433,42 @@
}
#endif
-/**
- * label_boot() - Boot according to the contents of a pxe_label
+/*
+ * label_process_fdt() - Process FDT for the label
*
- * If we can't boot for any reason, we return. A successful boot never
- * returns.
+ * @ctx: PXE context
+ * @label: Label to process
+ * @kernel_addr: String containing kernel address
+ * @fdt_argp: bootm argument to fill in, for FDT
+ * Return: 0 if OK, -ENOMEM if out of memory, -ENOENT if FDT file could not be
+ * loaded
*
- * The kernel will be stored in the location given by the 'kernel_addr_r'
- * environment variable.
+ * fdt usage is optional:
+ * It handles the following scenarios.
*
- * If the label specifies an initrd file, it will be stored in the location
- * given by the 'ramdisk_addr_r' environment variable.
+ * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is
+ * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to
+ * bootm, and adjust argc appropriately.
*
- * If the label specifies an 'append' line, its contents will overwrite that
- * of the 'bootargs' environment variable.
+ * If retrieve fails and no exact fdt blob is specified in pxe file with
+ * "fdt" label, try Scenario 2.
*
- * @ctx: PXE context
- * @label: Label to process
- * Returns does not return on success, otherwise returns 0 if a localboot
- * label was processed, or 1 on error
+ * Scenario 2: If there is an fdt_addr specified, pass it along to
+ * bootm, and adjust argc appropriately.
+ *
+ * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
+ * bootm, and adjust argc appropriately, unless the image type is fitImage.
+ *
+ * Scenario 4: fdt blob is not available.
*/
-static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
+static int label_process_fdt(struct pxe_context *ctx, struct pxe_label *label,
+ char *kernel_addr, const char **fdt_argp)
{
- char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL };
- char *zboot_argv[] = { "zboot", NULL, "0", NULL, NULL };
- char *kernel_addr = NULL;
- char *initrd_addr_str = NULL;
- char initrd_filesize[10];
- char initrd_str[28];
- char mac_str[29] = "";
- char ip_str[68] = "";
- char *fit_addr = NULL;
- int bootm_argc = 2;
- int zboot_argc = 3;
- int len = 0;
- ulong kernel_addr_r;
- void *buf;
-
- label_print(label);
-
- label->attempted = 1;
-
- if (label->localboot) {
- if (label->localboot_val >= 0)
- label_localboot(label);
- return 0;
- }
-
- if (!label->kernel) {
- printf("No kernel given, skipping %s\n",
- label->name);
- return 1;
- }
-
- if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r",
- (enum bootflow_img_t)IH_TYPE_KERNEL, NULL)
- < 0) {
- printf("Skipping %s for failure retrieving kernel\n",
- label->name);
- return 1;
- }
-
- kernel_addr = env_get("kernel_addr_r");
- /* for FIT, append the configuration identifier */
- if (label->config) {
- int len = strlen(kernel_addr) + strlen(label->config) + 1;
-
- fit_addr = malloc(len);
- if (!fit_addr) {
- printf("malloc fail (FIT address)\n");
- return 1;
- }
- snprintf(fit_addr, len, "%s%s", kernel_addr, label->config);
- kernel_addr = fit_addr;
- }
-
- /* For FIT, the label can be identical to kernel one */
- if (label->initrd && !strcmp(label->kernel_label, label->initrd)) {
- initrd_addr_str = kernel_addr;
- } else if (label->initrd) {
- ulong size;
- if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r",
- (enum bootflow_img_t)IH_TYPE_RAMDISK,
- &size) < 0) {
- printf("Skipping %s for failure retrieving initrd\n",
- label->name);
- goto cleanup;
- }
- strcpy(initrd_filesize, simple_xtoa(size));
- initrd_addr_str = env_get("ramdisk_addr_r");
- size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
- initrd_addr_str, size);
- if (size >= sizeof(initrd_str))
- goto cleanup;
- }
-
- if (label->ipappend & 0x1) {
- sprintf(ip_str, " ip=%s:%s:%s:%s",
- env_get("ipaddr"), env_get("serverip"),
- env_get("gatewayip"), env_get("netmask"));
- }
-
- if (IS_ENABLED(CONFIG_CMD_NET)) {
- if (label->ipappend & 0x2) {
- int err;
-
- strcpy(mac_str, " BOOTIF=");
- err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8);
- if (err < 0)
- mac_str[0] = '\0';
- }
- }
-
- if ((label->ipappend & 0x3) || label->append) {
- char bootargs[CONFIG_SYS_CBSIZE] = "";
- char finalbootargs[CONFIG_SYS_CBSIZE];
-
- if (strlen(label->append ?: "") +
- strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) {
- printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n",
- strlen(label->append ?: ""),
- strlen(ip_str), strlen(mac_str),
- sizeof(bootargs));
- goto cleanup;
- }
-
- if (label->append)
- strncpy(bootargs, label->append, sizeof(bootargs));
-
- strcat(bootargs, ip_str);
- strcat(bootargs, mac_str);
-
- cli_simple_process_macros(bootargs, finalbootargs,
- sizeof(finalbootargs));
- env_set("bootargs", finalbootargs);
- printf("append: %s\n", finalbootargs);
- }
-
- /*
- * fdt usage is optional:
- * It handles the following scenarios.
- *
- * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is
- * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to
- * bootm, and adjust argc appropriately.
- *
- * If retrieve fails and no exact fdt blob is specified in pxe file with
- * "fdt" label, try Scenario 2.
- *
- * Scenario 2: If there is an fdt_addr specified, pass it along to
- * bootm, and adjust argc appropriately.
- *
- * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
- * bootm, and adjust argc appropriately, unless the image type is fitImage.
- *
- * Scenario 4: fdt blob is not available.
- */
- bootm_argv[3] = env_get("fdt_addr_r");
-
/* For FIT, the label can be identical to kernel one */
if (label->fdt && !strcmp(label->kernel_label, label->fdt)) {
- bootm_argv[3] = kernel_addr;
+ *fdt_argp = kernel_addr;
/* if fdt label is defined then get fdt from server */
- } else if (bootm_argv[3]) {
+ } else if (*fdt_argp) {
char *fdtfile = NULL;
char *fdtfilefree = NULL;
@@ -607,6 +481,7 @@
}
} else if (label->fdtdir) {
char *f1, *f2, *f3, *f4, *slash;
+ int len;
f1 = env_get("fdtfile");
if (f1) {
@@ -649,7 +524,7 @@
fdtfilefree = malloc(len);
if (!fdtfilefree) {
printf("malloc fail (FDT filename)\n");
- goto cleanup;
+ return -ENOMEM;
}
snprintf(fdtfilefree, len, "%s%s%s%s%s%s",
@@ -664,12 +539,12 @@
free(fdtfilefree);
if (err < 0) {
- bootm_argv[3] = NULL;
+ *fdt_argp = NULL;
if (label->fdt) {
printf("Skipping %s for failure retrieving FDT\n",
label->name);
- goto cleanup;
+ return -ENOENT;
}
if (label->fdtdir) {
@@ -686,74 +561,236 @@
label_boot_fdtoverlay(ctx, label);
#endif
} else {
- bootm_argv[3] = NULL;
+ *fdt_argp = NULL;
}
}
- bootm_argv[1] = kernel_addr;
- zboot_argv[1] = kernel_addr;
+ return 0;
+}
- if (initrd_addr_str) {
- bootm_argv[2] = initrd_str;
- bootm_argc = 3;
+/**
+ * label_run_boot() - Set up the FDT and call the appropriate bootm/z/i command
+ *
+ * @ctx: PXE context
+ * @label: Label to process
+ * @kernel_addr: String containing kernel address (cannot be NULL)
+ * @initrd_addr_str: String containing initrd address (NULL if none)
+ * @initrd_filesize: String containing initrd size (only used if
+ * @initrd_addr_str)
+ * @initrd_str: initrd string to process (only used if @initrd_addr_str)
+ * Return: does not return on success, or returns 0 if the boot command
+ * returned, or -ve error value on error
+ */
+static int label_run_boot(struct pxe_context *ctx, struct pxe_label *label,
+ char *kernel_addr, char *initrd_addr_str,
+ char *initrd_filesize, char *initrd_str)
+{
+ struct bootm_info bmi;
+ ulong kernel_addr_r;
+ void *buf;
+ int ret;
+
+ bootm_init(&bmi);
+
+ bmi.conf_fdt = env_get("fdt_addr_r");
- zboot_argv[3] = initrd_addr_str;
- zboot_argv[4] = initrd_filesize;
- zboot_argc = 5;
+ ret = label_process_fdt(ctx, label, kernel_addr, &bmi.conf_fdt);
+ if (ret)
+ return ret;
+
+ bmi.addr_img = kernel_addr;
+ bootm_x86_set(&bmi, bzimage_addr, hextoul(kernel_addr, NULL));
+
+ if (initrd_addr_str) {
+ bmi.conf_ramdisk = initrd_str;
+ bootm_x86_set(&bmi, initrd_addr,
+ hextoul(initrd_addr_str, NULL));
+ bootm_x86_set(&bmi, initrd_size,
+ hextoul(initrd_filesize, NULL));
}
- if (!bootm_argv[3]) {
- if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
- if (strcmp("-", label->fdt))
- bootm_argv[3] = env_get("fdt_addr");
- } else {
- bootm_argv[3] = env_get("fdt_addr");
- }
+ if (!bmi.conf_fdt) {
+ if (!IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS) ||
+ strcmp("-", label->fdt))
+ bmi.conf_fdt = env_get("fdt_addr");
}
kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
buf = map_sysmem(kernel_addr_r, 0);
- if (!bootm_argv[3] && genimg_get_format(buf) != IMAGE_FORMAT_FIT) {
- if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
- if (strcmp("-", label->fdt))
- bootm_argv[3] = env_get("fdtcontroladdr");
- } else {
- bootm_argv[3] = env_get("fdtcontroladdr");
- }
- }
-
- if (bootm_argv[3]) {
- if (!bootm_argv[2])
- bootm_argv[2] = "-";
- bootm_argc = 4;
+ if (!bmi.conf_fdt && genimg_get_format(buf) != IMAGE_FORMAT_FIT) {
+ if (!IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS) ||
+ strcmp("-", label->fdt))
+ bmi.conf_fdt = env_get("fdtcontroladdr");
}
/* Try bootm for legacy and FIT format image */
if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
IS_ENABLED(CONFIG_CMD_BOOTM)) {
log_debug("using bootm\n");
- do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv);
+ ret = bootm_run(&bmi);
/* Try booting an AArch64 Linux kernel image */
} else if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
log_debug("using booti\n");
- do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv);
+ ret = booti_run(&bmi);
/* Try booting a Image */
} else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) {
log_debug("using bootz\n");
- do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv);
+ ret = bootz_run(&bmi);
/* Try booting an x86_64 Linux kernel image */
} else if (IS_ENABLED(CONFIG_CMD_ZBOOT)) {
log_debug("using zboot\n");
- do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL);
+ ret = zboot_run(&bmi);
}
unmap_sysmem(buf);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * label_boot() - Boot according to the contents of a pxe_label
+ *
+ * If we can't boot for any reason, we return. A successful boot never
+ * returns.
+ *
+ * The kernel will be stored in the location given by the 'kernel_addr_r'
+ * environment variable.
+ *
+ * If the label specifies an initrd file, it will be stored in the location
+ * given by the 'ramdisk_addr_r' environment variable.
+ *
+ * If the label specifies an 'append' line, its contents will overwrite that
+ * of the 'bootargs' environment variable.
+ *
+ * @ctx: PXE context
+ * @label: Label to process
+ * Returns does not return on success, otherwise returns 0 if a localboot
+ * label was processed, or 1 on error
+ */
+static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
+{
+ char *kernel_addr = NULL;
+ char *initrd_addr_str = NULL;
+ char initrd_filesize[10];
+ char initrd_str[28];
+ char mac_str[29] = "";
+ char ip_str[68] = "";
+ char *fit_addr = NULL;
+
+ label_print(label);
+
+ label->attempted = 1;
+
+ if (label->localboot) {
+ if (label->localboot_val >= 0)
+ label_localboot(label);
+ return 0;
+ }
+
+ if (!label->kernel) {
+ printf("No kernel given, skipping %s\n",
+ label->name);
+ return 1;
+ }
+
+ if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r",
+ (enum bootflow_img_t)IH_TYPE_KERNEL, NULL)
+ < 0) {
+ printf("Skipping %s for failure retrieving kernel\n",
+ label->name);
+ return 1;
+ }
+
+ kernel_addr = env_get("kernel_addr_r");
+ /* for FIT, append the configuration identifier */
+ if (label->config) {
+ int len = strlen(kernel_addr) + strlen(label->config) + 1;
+
+ fit_addr = malloc(len);
+ if (!fit_addr) {
+ printf("malloc fail (FIT address)\n");
+ return 1;
+ }
+ snprintf(fit_addr, len, "%s%s", kernel_addr, label->config);
+ kernel_addr = fit_addr;
+ }
+
+ /* For FIT, the label can be identical to kernel one */
+ if (label->initrd && !strcmp(label->kernel_label, label->initrd)) {
+ initrd_addr_str = kernel_addr;
+ } else if (label->initrd) {
+ ulong size;
+ int ret;
+
+ ret = get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r",
+ (enum bootflow_img_t)IH_TYPE_RAMDISK,
+ &size);
+ if (ret < 0) {
+ printf("Skipping %s for failure retrieving initrd\n",
+ label->name);
+ goto cleanup;
+ }
+ strcpy(initrd_filesize, simple_xtoa(size));
+ initrd_addr_str = env_get("ramdisk_addr_r");
+ size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
+ initrd_addr_str, size);
+ if (size >= sizeof(initrd_str))
+ goto cleanup;
+ }
+
+ if (label->ipappend & 0x1) {
+ sprintf(ip_str, " ip=%s:%s:%s:%s",
+ env_get("ipaddr"), env_get("serverip"),
+ env_get("gatewayip"), env_get("netmask"));
+ }
+
+ if (IS_ENABLED(CONFIG_CMD_NET)) {
+ if (label->ipappend & 0x2) {
+ int err;
+
+ strcpy(mac_str, " BOOTIF=");
+ err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8);
+ if (err < 0)
+ mac_str[0] = '\0';
+ }
+ }
+
+ if ((label->ipappend & 0x3) || label->append) {
+ char bootargs[CONFIG_SYS_CBSIZE] = "";
+ char finalbootargs[CONFIG_SYS_CBSIZE];
+
+ if (strlen(label->append ?: "") +
+ strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) {
+ printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n",
+ strlen(label->append ?: ""),
+ strlen(ip_str), strlen(mac_str),
+ sizeof(bootargs));
+ goto cleanup;
+ }
+
+ if (label->append)
+ strlcpy(bootargs, label->append, sizeof(bootargs));
+
+ strcat(bootargs, ip_str);
+ strcat(bootargs, mac_str);
+
+ cli_simple_process_macros(bootargs, finalbootargs,
+ sizeof(finalbootargs));
+ env_set("bootargs", finalbootargs);
+ printf("append: %s\n", finalbootargs);
+ }
+
+ label_run_boot(ctx, label, kernel_addr, initrd_addr_str,
+ initrd_filesize, initrd_str);
+ /* ignore the error value since we are going to fail anyway */
cleanup:
free(fit_addr);
- return 1;
+ return 1; /* returning is always failure */
}
/** enum token_type - Tokens for the pxe file parser */
diff --git a/cmd/blkmap.c b/cmd/blkmap.c
index 164f80f..86a123b 100644
--- a/cmd/blkmap.c
+++ b/cmd/blkmap.c
@@ -62,13 +62,18 @@
{
phys_addr_t addr;
int err;
+ bool preserve = false;
if (argc < 2)
return CMD_RET_USAGE;
addr = hextoul(argv[1], NULL);
- err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr);
+ if (argc == 3 && !strcmp(argv[2], "preserve"))
+ preserve = true;
+
+ err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr,
+ preserve);
if (err) {
printf("Unable to map %#llx at block 0x" LBAF ": %d\n",
(unsigned long long)addr, ctx->blknr, err);
@@ -221,7 +226,7 @@
"blkmap create <label> - create device\n"
"blkmap destroy <label> - destroy device\n"
"blkmap map <label> <blk#> <cnt> linear <interface> <dev> <blk#> - device mapping\n"
- "blkmap map <label> <blk#> <cnt> mem <addr> - memory mapping\n",
+ "blkmap map <label> <blk#> <cnt> mem <addr> [preserve] - memory mapping\n",
U_BOOT_SUBCMD_MKENT(info, 2, 1, do_blkmap_common),
U_BOOT_SUBCMD_MKENT(part, 2, 1, do_blkmap_common),
U_BOOT_SUBCMD_MKENT(dev, 4, 1, do_blkmap_common),
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index f88995a..6d0be32 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -380,7 +380,13 @@
bflow = std->cur_bootflow;
if (IS_ENABLED(CONFIG_X86) && x86_setup) {
- zimage_dump(bflow->x86_setup, false);
+ struct bootm_info bmi;
+
+ bootm_init(&bmi);
+ /* we don't know this at present */
+ bootm_x86_set(&bmi, bzimage_addr, 0);
+ bootm_x86_set(&bmi, base_ptr, bflow->x86_setup);
+ zimage_dump(&bmi, false);
return 0;
}
diff --git a/cmd/net.c b/cmd/net.c
index 79525f7..8f33c9f 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -297,13 +297,15 @@
/**
* parse_addr_size() - parse address and size arguments for tftpput
*
- * @argv: command line arguments
+ * @argv: command line arguments (argv[1] and argv[2] must be valid)
+ * @addrp: returns the address, on success
+ * @sizep: returns the size, on success
* Return: 0 on success
*/
-static int parse_addr_size(char * const argv[])
+static int parse_addr_size(char * const argv[], ulong *addrp, ulong *sizep)
{
- if (strict_strtoul(argv[1], 16, &image_save_addr) < 0 ||
- strict_strtoul(argv[2], 16, &image_save_size) < 0) {
+ if (strict_strtoul(argv[1], 16, addrp) < 0 ||
+ strict_strtoul(argv[2], 16, sizep) < 0) {
printf("Invalid address/size\n");
return CMD_RET_USAGE;
}
@@ -313,24 +315,31 @@
/**
* parse_args() - parse command line arguments
*
+ * Sets:
+ * - image_save_addr and image_save_size, if proto == TFTPPUT
+ *
* @proto: command prototype
- * @argc: number of arguments
- * @argv: command line arguments
+ * @argc: number of arguments, include the command, which has already been
+ * parsed
+ * @argv: command line arguments, with argv[0] being the command
+ * @fnamep: set to the filename, if provided, else NULL
+ * @addrp: returns the load/save address, if any is provided, else it is
+ * left unchanged
+ * @sizep: returns the save size, if any is provided, else it is left
+ * unchanged
* Return: 0 on success
*/
-static int parse_args(enum proto_t proto, int argc, char *const argv[])
+static int parse_args(enum proto_t proto, int argc, char *const argv[],
+ const char **fnamep, ulong *addrp, ulong *sizep)
{
ulong addr;
char *end;
+ *fnamep = NULL;
switch (argc) {
case 1:
if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT)
return 1;
-
- /* refresh bootfile name from env */
- copy_filename(net_boot_file_name, env_get("bootfile"),
- sizeof(net_boot_file_name));
break;
case 2:
@@ -343,48 +352,42 @@
* mis-interpreted as a valid number.
*/
addr = hextoul(argv[1], &end);
- if (end == (argv[1] + strlen(argv[1]))) {
- image_load_addr = addr;
- /* refresh bootfile name from env */
- copy_filename(net_boot_file_name, env_get("bootfile"),
- sizeof(net_boot_file_name));
- } else {
- net_boot_file_name_explicit = true;
- copy_filename(net_boot_file_name, argv[1],
- sizeof(net_boot_file_name));
- }
+ if (end == (argv[1] + strlen(argv[1])))
+ *addrp = addr;
+ else
+ *fnamep = argv[1];
break;
case 3:
if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT) {
- if (parse_addr_size(argv))
+ if (parse_addr_size(argv, addrp, sizep))
return 1;
} else {
- image_load_addr = hextoul(argv[1], NULL);
- net_boot_file_name_explicit = true;
- copy_filename(net_boot_file_name, argv[2],
- sizeof(net_boot_file_name));
+ *addrp = hextoul(argv[1], NULL);
+ *fnamep = argv[2];
}
break;
-#ifdef CONFIG_CMD_TFTPPUT
case 4:
- if (parse_addr_size(argv))
- return 1;
- net_boot_file_name_explicit = true;
- copy_filename(net_boot_file_name, argv[3],
- sizeof(net_boot_file_name));
- break;
-#endif
+ if (IS_ENABLED(CONFIG_CMD_TFTPPUT)) {
+ if (parse_addr_size(argv, addrp, sizep))
+ return 1;
+ *fnamep = argv[3];
+ break;
+ }
default:
return 1;
}
+
return 0;
}
static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc,
char *const argv[])
{
+ ulong addr, save_size;
+ bool fname_explicit;
+ const char *fname;
char *s;
int rcode = 0;
int size;
@@ -392,10 +395,10 @@
net_boot_file_name_explicit = false;
*net_boot_file_name = '\0';
- /* pre-set image_load_addr */
+ /* pre-set addr */
s = env_get("loadaddr");
if (s != NULL)
- image_load_addr = hextoul(s, NULL);
+ addr = hextoul(s, NULL);
if (IS_ENABLED(CONFIG_IPV6)) {
use_ip6 = false;
@@ -408,12 +411,17 @@
}
}
- if (parse_args(proto, argc, argv)) {
+ if (parse_args(proto, argc, argv, &fname, &addr, &save_size)) {
bootstage_error(BOOTSTAGE_ID_NET_START);
return CMD_RET_USAGE;
}
- bootstage_mark(BOOTSTAGE_ID_NET_START);
+ if (fname) {
+ fname_explicit = true;
+ } else {
+ fname_explicit = false;
+ fname = env_get("bootfile");
+ }
if (IS_ENABLED(CONFIG_IPV6) && !use_ip6) {
char *s, *e;
@@ -428,12 +436,10 @@
}
}
- size = net_loop(proto);
- if (size < 0) {
- bootstage_error(BOOTSTAGE_ID_NET_NETLOOP_OK);
+ size = netboot_run_(proto, addr, fname, save_size, fname_explicit,
+ IS_ENABLED(CONFIG_IPV6) && use_ip6);
+ if (size < 0)
return CMD_RET_FAILURE;
- }
- bootstage_mark(BOOTSTAGE_ID_NET_NETLOOP_OK);
/* net_loop ok, update environment */
netboot_update_env();
diff --git a/cmd/version.c b/cmd/version.c
index 53db1a0..6240660 100644
--- a/cmd/version.c
+++ b/cmd/version.c
@@ -6,6 +6,7 @@
#include <command.h>
#include <display_options.h>
+#include <version.h>
#include <version_string.h>
#include <linux/compiler.h>
#ifdef CONFIG_SYS_COREBOOT
diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c
index 94e602b8..ee099ca 100644
--- a/cmd/x86/zboot.c
+++ b/cmd/x86/zboot.c
@@ -7,11 +7,15 @@
#define LOG_CATEGORY LOGC_BOOT
+#include <bootm.h>
#include <command.h>
#include <mapmem.h>
#include <vsprintf.h>
#include <asm/zimage.h>
+/* Current state of the boot */
+static struct bootm_info bmi;
+
static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -20,6 +24,8 @@
ulong base_addr;
int i;
+ bootm_init(&bmi);
+
log_debug("argc %d:", argc);
for (i = 0; i < argc; i++)
log_debug(" %s", argv[i]);
@@ -35,7 +41,7 @@
base_addr = argc > 5 ? hextoul(argv[5], NULL) : 0;
cmdline = argc > 6 ? env_get(argv[6]) : NULL;
- zboot_start(bzimage_addr, bzimage_size, initrd_addr, initrd_size,
+ zboot_start(&bmi, bzimage_addr, bzimage_size, initrd_addr, initrd_size,
base_addr, cmdline);
return 0;
@@ -46,7 +52,7 @@
{
int ret;
- ret = zboot_load();
+ ret = zboot_load(&bmi);
if (ret)
return ret;
@@ -56,16 +62,17 @@
static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- if (!state.base_ptr) {
+ if (!bmi.base_ptr) {
printf("base is not set: use 'zboot load' first\n");
return CMD_RET_FAILURE;
}
- if (zboot_setup()) {
+
+ if (zboot_setup(&bmi)) {
puts("Setting up boot parameters failed ...\n");
return CMD_RET_FAILURE;
}
- if (zboot_setup())
+ if (zboot_setup(&bmi))
return CMD_RET_FAILURE;
return 0;
@@ -74,7 +81,7 @@
static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- zboot_info();
+ zboot_info(&bmi);
return 0;
}
@@ -84,7 +91,7 @@
{
int ret;
- ret = zboot_go();
+ ret = zboot_go(&bmi);
if (ret) {
printf("Kernel returned! (err=%d)\n", ret);
return CMD_RET_FAILURE;
@@ -96,15 +103,13 @@
static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- struct boot_params *base_ptr = state.base_ptr;
-
if (argc > 1)
- base_ptr = (void *)hextoul(argv[1], NULL);
- if (!base_ptr) {
+ bmi.base_ptr = (void *)hextoul(argv[1], NULL);
+ if (!bmi.base_ptr) {
printf("No zboot setup_base\n");
return CMD_RET_FAILURE;
}
- zimage_dump(base_ptr, true);
+ zimage_dump(&bmi, true);
return 0;
}
@@ -119,8 +124,8 @@
U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""),
)
-int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], int state_mask)
+static int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[], int state_mask)
{
int ret = 0;
diff --git a/common/console.c b/common/console.c
index 863ac6a..26812b2 100644
--- a/common/console.c
+++ b/common/console.c
@@ -942,11 +942,6 @@
struct stdio_dev *dev;
dev = stdio_get_by_name(name);
-#ifdef CONFIG_VIDCONSOLE_AS_LCD
- if (!dev && !strcmp(name, CONFIG_VIDCONSOLE_AS_NAME))
- dev = stdio_get_by_name("vidconsole");
-#endif
-
if (dev && (dev->flags & flags))
return dev;
@@ -1154,12 +1149,6 @@
if (!IS_ENABLED(CONFIG_SYS_CONSOLE_INFO_QUIET))
stdio_print_current_devices();
-#ifdef CONFIG_VIDCONSOLE_AS_LCD
- if (strstr(stdoutname, CONFIG_VIDCONSOLE_AS_NAME))
- printf("Warning: Please change '%s' to 'vidconsole' in stdout/stderr environment vars\n",
- CONFIG_VIDCONSOLE_AS_NAME);
-#endif
-
if (IS_ENABLED(CONFIG_SYS_CONSOLE_ENV_OVERWRITE)) {
/* set the environment variables (will overwrite previous env settings) */
for (i = 0; i < MAX_FILES; i++)
diff --git a/common/edid.c b/common/edid.c
index e2ac710..e5aa4ca 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -16,6 +16,7 @@
#include <linux/ctype.h>
#include <linux/string.h>
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
#define TIMING(c, ha, hfp, hbp, hsl, va, vfp, vbp, vsl, f) \
.pixelclock = { (c), (c), (c) }, \
.hactive = { (ha), (ha), (ha) }, \
@@ -206,6 +207,7 @@
{ TIMING(556188000, 4096, 8, 32, 40, 2160, 48, 8, 6,
DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
};
+#endif
int edid_check_info(struct edid1_info *edid_info)
{
@@ -417,6 +419,7 @@
return false;
}
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
static bool edid_find_valid_standard_timing(struct edid1_info *buf,
struct display_timing *timing,
bool (*mode_valid)(void *priv,
@@ -446,6 +449,7 @@
return found;
}
+#endif
int edid_get_timing_validate(u8 *buf, int buf_size,
struct display_timing *timing,
@@ -493,10 +497,12 @@
}
}
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
/* Look for timing in Standard Timings */
if (!found)
found = edid_find_valid_standard_timing(edid, timing, mode_valid,
mode_valid_priv);
+#endif
if (!found)
return -EINVAL;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 97f542f..c08045f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -80,11 +80,10 @@
default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
default 0xec00 if OMAP34XX
default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
- default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
- default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
default 0xbfa0 if MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ default 0x7fa0 if ARCH_SUNXI
default 0x10000 if ASPEED_AST2600
default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
default 0x30000 if ARCH_SC5XX && (SC59X_64 || SC59X)
@@ -1450,6 +1449,24 @@
Address within SPI-Flash from where the u-boot payload is fetched
from.
+config SYS_SPI_KERNEL_OFFS
+ hex "Falcon mode: address of kernel payload in SPI flash"
+ depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+ help
+ Address within SPI-Flash from where the kernel payload is fetched
+ in falcon boot.
+
+config SYS_SPI_ARGS_OFFS
+ hex "Falcon mode: address of args payload in SPI flash"
+ depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+ help
+ Address within SPI-Flash from where the args payload (usually the
+ dtb) is fetched in falcon boot.
+
+config SYS_SPI_ARGS_SIZE
+ hex "Falcon mode: size of args payload in SPI flash"
+ depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+
config SPL_THERMAL
bool "Driver support for thermal devices"
help
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index c547882..7e0274a 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -11,12 +11,20 @@
static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
ulong size, void *buf)
{
+ struct legacy_img_hdr *header;
int ret;
loff_t actlen;
ret = ext4fs_read(buf, file_offset, size, &actlen);
if (ret)
return ret;
+
+ if (CONFIG_IS_ENABLED(OS_BOOT)) {
+ header = (struct legacy_img_hdr *)buf;
+ if (image_get_magic(header) != FDT_MAGIC)
+ return size;
+ }
+
return actlen;
}
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index fce451b..f426a06 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -47,6 +47,7 @@
static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
ulong size, void *buf)
{
+ struct legacy_img_hdr *header;
loff_t actread;
int ret;
char *filename = load->priv;
@@ -55,6 +56,12 @@
if (ret)
return ret;
+ if (CONFIG_IS_ENABLED(OS_BOOT)) {
+ header = (struct legacy_img_hdr *)buf;
+ if (image_get_magic(header) != FDT_MAGIC)
+ return size;
+ }
+
return actread;
}
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 691a431..00dbd30 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -82,13 +82,14 @@
#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot()) {
int err = spl_load(spl_image, bootdev, &load, 0,
- CFG_SYS_SPI_KERNEL_OFFS);
+ CONFIG_SYS_SPI_KERNEL_OFFS);
if (!err)
/* Read device tree. */
- return spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
- CFG_SYS_SPI_ARGS_SIZE,
- (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
+ return spi_flash_read(
+ flash, CONFIG_SYS_SPI_ARGS_OFFS,
+ CONFIG_SYS_SPI_ARGS_SIZE,
+ (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
}
#endif
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 13260ed..2421208 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -40,6 +40,9 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index a406e89..2fc5e35 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -38,6 +38,9 @@
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index d865b12..634294e 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -41,6 +41,9 @@
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am62x_a53_usbmsc.config b/configs/am62x_a53_usbmsc.config
new file mode 100644
index 0000000..873a559
--- /dev/null
+++ b/configs/am62x_a53_usbmsc.config
@@ -0,0 +1,20 @@
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_DWC3_AM62=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
+# CONFIG_DM_USB_GADGET is not set
+# CONFIG_SPL_DM_USB_GADGET is not set
+# CONFIG_USB_GADGET_DOWNLOAD is not set
diff --git a/configs/am62x_r5_usbmsc.config b/configs/am62x_r5_usbmsc.config
new file mode 100644
index 0000000..09f9451
--- /dev/null
+++ b/configs/am62x_r5_usbmsc.config
@@ -0,0 +1,24 @@
+CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_MISC=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
+# CONFIG_CMD_DFU is not set
+# CONFIG_CMD_FAT is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_MMC is not set
+# CONFIG_DFU is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
+# CONFIG_SPL_MTD is not set
+# CONFIG_SPL_RAM_DEVICE is not set
+# CONFIG_SPL_SPI is not set
+# CONFIG_SPL_SYS_MALLOC is not set
+# CONFIG_MMC_SDHCI is not set
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 3f002ae..c2ad124 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -71,6 +71,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 227de53..b0d333d 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -1,7 +1,9 @@
+#include<configs/am65x_evm_r5_defconfig>
+
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x55000
+CONFIG_SYS_MALLOC_F_LEN=0x57000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -13,103 +15,17 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_DM_RESET=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41c7effc
-CONFIG_SPL_BSS_MAX_SIZE=0xc00
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SIZE_LIMIT=0x7ec00
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
-CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
-CONFIG_SPL_MAX_SIZE=0x58000
-CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
CONFIG_MISC=y
-CONFIG_K3_AVS0=y
-# CONFIG_MMC is not set
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_OMAP_USB2_PHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_TPS62360=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
@@ -126,4 +42,34 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_FS_FAT=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_CMD_MMC=n
+CONFIG_ENV_OVERWRITE=n
+CONFIG_ENV_IS_IN_FAT=n
+CONFIG_DMA_CHANNELS=n
+CONFIG_TI_K3_NAVSS_UDMA=n
+CONFIG_SUPPORT_EMMC_BOOT=n
+CONFIG_MMC_HS200_SUPPORT=n
+CONFIG_SPL_MMC_HS200_SUPPORT=n
+CONFIG_MMC_SDHCI=n
+CONFIG_SPL_MMC_SDHCI_ADMA=n
+CONFIG_MMC_SDHCI_AM654=n
+CONFIG_MTD=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SOC_DEVICE=n
+CONFIG_SOC_DEVICE_TI_K3=n
+CONFIG_SOC_TI=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
diff --git a/configs/am67a_beagley_ai_a53_defconfig b/configs/am67a_beagley_ai_a53_defconfig
new file mode 100644
index 0000000..b0903b6
--- /dev/null
+++ b/configs/am67a_beagley_ai_a53_defconfig
@@ -0,0 +1,37 @@
+#include <configs/j722s_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_BEAGLEY_AI=y
+
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am67a-beagley-ai"
+CONFIG_SPL_OF_LIST="ti/k3-am67a-beagley-ai"
+CONFIG_OF_LIST="ti/k3-am67a-beagley-ai"
+
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run distro_bootcmd"
+CONFIG_EXT4_WRITE=y
+CONFIG_LZO=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_TI_I2C_BOARD_DETECT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_MTD_SUPPORT=n
+CONFIG_SPL_MTD_SUPPORT=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH=n
+CONFIG_MTD=n
+CONFIG_MTD_PARTITIONS=n
+CONFIG_DM_MTD=n
+CONFIG_MTD_UBI=n
+CONFIG_CMD_UBIFS=n
+CONFIG_CMD_UBI=n
+CONFIG_DFU_SF=n
+CONFIG_DM_SPI=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_SPL_MTD=n
+CONFIG_CMD_SPI=n
diff --git a/configs/am67a_beagley_ai_r5_defconfig b/configs/am67a_beagley_ai_r5_defconfig
new file mode 100644
index 0000000..5380747
--- /dev/null
+++ b/configs/am67a_beagley_ai_r5_defconfig
@@ -0,0 +1,14 @@
+#include <configs/j722s_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_R5_BEAGLEY_AI=y
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-am67a-r5-beagley-ai"
+CONFIG_SPL_OF_LIST="k3-am67a-r5-beagley-ai"
+CONFIG_OF_LIST="k3-am67a-r5-beagley-ai"
+
+CONFIG_TI_I2C_BOARD_DETECT=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_MTD_SUPPORT=n
diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig
index 097bed6..d6ef89c 100644
--- a/configs/am68_sk_r5_defconfig
+++ b/configs/am68_sk_r5_defconfig
@@ -6,7 +6,6 @@
CONFIG_TARGET_J721S2_R5_EVM=y
CONFIG_ESM_K3=n
-CONFIG_K3_AVS0=n
CONFIG_ESM_PMIC=n
CONFIG_DM_REGULATOR_TPS65941=n
CONFIG_PMIC_TPS65941=n
diff --git a/configs/am69_sk_a72_defconfig b/configs/am69_sk_a72_defconfig
index 452de88..bd8aaf7 100644
--- a/configs/am69_sk_a72_defconfig
+++ b/configs/am69_sk_a72_defconfig
@@ -5,5 +5,10 @@
CONFIG_SOC_K3_J784S4=y
CONFIG_TARGET_J784S4_A72_EVM=y
+CONFIG_CMD_UFS=n
+CONFIG_UFS=n
+CONFIG_CADENCE_UFS=n
+CONFIG_TI_J721E_UFS=n
+
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk"
CONFIG_OF_LIST="ti/k3-am69-sk"
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index a3f65c5..f51386d 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -31,7 +31,7 @@
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6q-apalis-${fdt_board}.dtb"
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6q-apalis${variant}-${fdt_board}.dtb"
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1055
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig
index 0f12db3..7483f12 100644
--- a/configs/bananapi-f3_defconfig
+++ b/configs/bananapi-f3_defconfig
@@ -18,3 +18,4 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_RESET_SPACEMIT_K1=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 4c6ba80..9fc844b 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -30,7 +30,7 @@
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6dl-colibri-${fdt_board}.dtb"
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6dl-colibri${variant}-${fdt_board}.dtb"
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1056
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 55f9bba..a00a042 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -53,6 +53,9 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x150000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 > "
CONFIG_SYS_MAXARGS=32
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 4007c89..9965e00 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -48,6 +48,9 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x150000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x10000
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="display5 factory > "
CONFIG_SYS_MAXARGS=32
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 2448bef..f9cb732 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -43,6 +43,9 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_CMD_SPL=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_NAND=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index f6f0045..81da64b 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -40,6 +40,9 @@
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_NAND=y
CONFIG_BOOTP_DNS2=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 850ccd9..1d099a5 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -39,6 +39,9 @@
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index 5e422f6..fb3d7fc 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -80,6 +80,7 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x0c02
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_LCD_ENDEAVORU=y
CONFIG_VIDEO_DSI_TEGRA30=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index d1f6eef..bf80a19 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -63,6 +63,9 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x40
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x100000
+CONFIG_SYS_SPI_ARGS_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_SIZE=0x8000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index a69e2ba..288626c 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -87,6 +87,7 @@
CONFIG_ETHPRIME="eth1"
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index ae5849b..8df921c 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -99,7 +99,9 @@
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
+CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index 1ba2bfe..1280194 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -170,5 +170,9 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
+CONFIG_CMD_UFS=y
+CONFIG_UFS=y
+CONFIG_CADENCE_UFS=y
+CONFIG_TI_J721E_UFS=y
#include <configs/k3_efi_capsule.config>
diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig
index 0cbedb2..dfeb16a 100644
--- a/configs/mocha_defconfig
+++ b/configs/mocha_defconfig
@@ -28,6 +28,7 @@
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 870b7a1..25b0b11 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -13,7 +13,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index f841b21..737a079 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -24,7 +24,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 11a18d1..964d00a 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -24,7 +24,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 316f74c..369bc0f 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -14,7 +14,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 8be5963..97d4f9f 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -15,7 +15,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 2c13dd4..1a49bc2 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -14,7 +14,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/ouya_defconfig b/configs/ouya_defconfig
new file mode 100644
index 0000000..d4ae9db
--- /dev/null
+++ b/configs/ouya_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="ouya"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-ouya"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA30=y
+CONFIG_TARGET_OUYA=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2084
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra30 (Ouya) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_TPS65910=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_I2C_EDID_STANDARD=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 594af51..247df4c 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -81,7 +81,6 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_EXYNOS=y
CONFIG_EXYNOS_DP=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 2b34c25..df72be8 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -80,7 +80,6 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_EXYNOS=y
CONFIG_EXYNOS_DP=y
diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig
index 8c4fcc3..d86e19d 100644
--- a/configs/phycore_am62ax_a53_defconfig
+++ b/configs/phycore_am62ax_a53_defconfig
@@ -35,6 +35,9 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
@@ -62,18 +65,25 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_CMD_BOOTEFI_HELLO is not set
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
+# CONFIG_CMD_POWEROFF is not set
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@@ -95,6 +105,7 @@
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
@@ -118,6 +129,7 @@
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
@@ -175,3 +187,4 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+# CONFIG_HEXDUMP is not set
diff --git a/configs/phycore_am62ax_r5_usbdfu_defconfig b/configs/phycore_am62ax_r5_usbdfu_defconfig
new file mode 100644
index 0000000..34674ce
--- /dev/null
+++ b/configs/phycore_am62ax_r5_usbdfu_defconfig
@@ -0,0 +1,4 @@
+#include <configs/phycore_am62ax_r5_defconfig>
+#include <configs/am62x_r5_usbdfu.config>
+
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 661a484..ba4d38d 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -97,6 +97,7 @@
CONFIG_PINCTRL_QCOM_APQ8096=y
CONFIG_PINCTRL_QCOM_QCM2290=y
CONFIG_PINCTRL_QCOM_QCS404=y
+CONFIG_PINCTRL_QCOM_SC7280=y
CONFIG_PINCTRL_QCOM_SDM845=y
CONFIG_PINCTRL_QCOM_SM6115=y
CONFIG_PINCTRL_QCOM_SM8150=y
@@ -120,6 +121,7 @@
CONFIG_SPMI_MSM=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
+CONFIG_SYSRESET_QCOM_PSHOLD=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/qcom_ipq9574_mmc_defconfig b/configs/qcom_ipq9574_mmc_defconfig
new file mode 100644
index 0000000..9bc1e1c
--- /dev/null
+++ b/configs/qcom_ipq9574_mmc_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_NR_DRAM_BANKS=24
+CONFIG_DEFAULT_DEVICE_TREE="qcom/ipq9574-rdp433"
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_EFI_LOADER is not set
+# CONFIG_EFI_BINARY_EXEC is not set
+# CONFIG_EFI_VARIABLE_FILE_STORE is not set
+# CONFIG_PXE_UTILS is not set
+# CONFIG_BOOTSTD is not set
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_BOOTDELAY=2
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_LOG_MAX_LEVEL=9
+CONFIG_LOG_DEFAULT_LEVEL=4
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PART=y
+CONFIG_OF_LIVE=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env"
+CONFIG_CLK=y
+CONFIG_CLK_QCOM_IPQ9574=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SCSI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000
+CONFIG_MSM_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_QCOM_IPQ9574=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_QCOM=y
+CONFIG_RGMII=y
+CONFIG_PHY=y
+CONFIG_PHY_QCOM_QMP_UFS=y
+CONFIG_PHY_QCOM_QUSB2=y
+CONFIG_SCSI=y
+CONFIG_MSM_SERIAL=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SOC_QCOM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x78b1000
+CONFIG_DEBUG_UART_MSM=y
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_TEXT_BASE=0x4A240000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1024
+CONFIG_OF_LIVE=y
+CONFIG_MSM_SERIAL=y
+CONFIG_DM_EVENT=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0
+CONFIG_PARTITIONS=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_MTD=y
+CONFIG_MTD_PARTS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_PARTITIONS=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_SCSI is not set
+# CONFIG_SPMI is not set
diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig
index b49a81d..8dcf8e3 100644
--- a/configs/r8a779g0_whitehawk_defconfig
+++ b/configs/r8a779g0_whitehawk_defconfig
@@ -3,6 +3,8 @@
CONFIG_ARM=y
CONFIG_ARCH_RENESAS=y
CONFIG_RCAR_GEN4=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARMV8_PSCI=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779g0-white-hawk"
diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig
index 7a1224b..b1d970b 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -26,6 +26,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -54,5 +55,12 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_RAA215300=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index 4632939..e1a0555 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -149,6 +149,7 @@
CONFIG_GPIO_HOG=y
CONFIG_QCOM_PMIC_GPIO=y
CONFIG_SANDBOX_GPIO=y
+CONFIG_TPL_DM_I2C=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 88a75c0..f70e3db 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -27,7 +27,7 @@
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};nvme scan"
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 27698f5..adf6213 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -98,7 +98,6 @@
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_EXYNOS=y
CONFIG_EXYNOS_DP=y
diff --git a/configs/socfpga_agilex5_nand2_defconfig b/configs/socfpga_agilex5_nand2_defconfig
new file mode 100644
index 0000000..c9c7077
--- /dev/null
+++ b/configs/socfpga_agilex5_nand2_defconfig
@@ -0,0 +1,31 @@
+#include <configs/socfpga_agilex5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
+CONFIG_BOOTARGS="earlycon panic=-1 root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1"
+CONFIG_TARGET_SOCFPGA_AGILEX5_NAND2=y
+CONFIG_PHY_CADENCE_COMBOPHY=n
+CONFIG_SPL_PHY_CADENCE_COMBOPHY=n
+# CONFIG_MMC_DW is not set
+CONFIG_SPL_MTD=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_MTDIDS_DEFAULT="nand0=10b80000.nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=10b80000.nand.0:2m(u-boot),-(root)"
+CONFIG_CMD_UBIFS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_CADENCE=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_CADENCE=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 43846e3..d3b6656 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -92,7 +92,6 @@
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_EXYNOS=y
CONFIG_EXYNOS_DP=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 3a90f1f..6a5b247 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -72,6 +72,7 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BIND is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
@@ -118,6 +119,9 @@
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_STARFIVE_JH7110=y
+CONFIG_PHY=y
+CONFIG_PHY_STARFIVE_JH7110_PCIE=y
+CONFIG_PHY_STARFIVE_JH7110_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -133,13 +137,19 @@
CONFIG_SYSRESET=y
CONFIG_TIMER_EARLY=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+# CONFIG_USB_CDNS3_TI is not set
CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
# CONFIG_WATCHDOG is not set
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_WDT=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 99fe65d..c307d8c 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -110,7 +110,6 @@
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_IMX_VIDEO_SKIP=y
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 91074e9..3e2db0c 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -90,6 +90,8 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/vexpress_fvp_defconfig b/configs/vexpress_fvp_defconfig
index 7362c1f..fda0f52 100644
--- a/configs/vexpress_fvp_defconfig
+++ b/configs/vexpress_fvp_defconfig
@@ -2,4 +2,5 @@
CONFIG_ARCH_VEXPRESS64=y
CONFIG_DEFAULT_DEVICE_TREE="arm_fvp"
CONFIG_IDENT_STRING=" arm_fvp"
+# CONFIG_ARM64_CRC32 is not set
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index 12be929..e738bd2 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -83,6 +83,7 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x7100
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
# CONFIG_VIDEO_LOGO is not set
CONFIG_BACKLIGHT_LM3533=y
CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 1578edf..6859e24 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -51,6 +51,9 @@
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x280000
+CONFIG_SYS_SPI_ARGS_OFFS=0x200000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
CONFIG_SYS_MAXARGS=32
# CONFIG_BOOTM_NETBSD is not set
CONFIG_CMD_IMLS=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 6f86873..1f8e8c3 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -58,6 +58,9 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_OFFS=0xa0000
+CONFIG_SYS_SPI_ARGS_SIZE=0xa0000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_SMBIOS=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 9641998..abd1e1b 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -56,6 +56,9 @@
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_OFFS=0xa0000
+CONFIG_SYS_SPI_ARGS_SIZE=0xa0000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_SMBIOS=y
diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII
deleted file mode 100644
index 05ab203..0000000
--- a/doc/README.bitbangMII
+++ /dev/null
@@ -1,39 +0,0 @@
-This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
-support an arbitrary number of mii buses. This feature is useful when your
-board uses different mii buses for different phys and all (or a part) of these
-buses are implemented via bit-banging mode.
-
-The driver requires that the following macros should be defined into the board
-configuration file:
-
-CONFIG_BITBANGMII - Enable the miiphybb driver
-
-The board code needs to fill the bb_miiphy_buses[] array with a record for
-each required bus and declare the bb_miiphy_buses_num variable with the
-number of mii buses. The record (struct bb_miiphy_bus) has the following
-fields/callbacks (see miiphy.h for details):
-
-char name[] - The symbolic name that must be equal to the MII bus
- registered name
-int (*init)() - Initialization function called at startup time (just
- before the Ethernet initialization)
-int (*mdio_active)() - Activate the MDIO pin as output
-int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
-int (*set_mdio)() - Write the MDIO pin
-int (*get_mdio)() - Read the MDIO pin
-int (*set_mdc)() - Write the MDC pin
-int (*delay)() - Delay function
-void *priv - Private data used by board specific code
-
-The board code will look like:
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... },
- { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... },
- ...
-};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
-
-2009 Industrie Dial Face S.p.A.
- Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
diff --git a/doc/board/amlogic/odroid-n2.rst b/doc/board/amlogic/odroid-n2.rst
index 883720f..5222a21 100644
--- a/doc/board/amlogic/odroid-n2.rst
+++ b/doc/board/amlogic/odroid-n2.rst
@@ -54,10 +54,9 @@
$ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- $ DIR=odroid-n2
- $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 $DIR
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 odroidg12
- $ cd odroid-n2
+ $ cd odroidg12
$ make odroidn2_defconfig
$ make
$ export UBOOTDIR=$PWD
@@ -74,12 +73,8 @@
$ cp $UBOOTDIR/fip/g12b/bl2.bin fip/
$ cp $UBOOTDIR/fip/g12b/bl30.bin fip/
$ cp $UBOOTDIR/fip/g12b/bl31.img fip/
- $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
$ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
$ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
- $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
- $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
- $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
$ cp $UBOOTDIR/fip/g12b/piei.fw fip/
$ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
$ cp u-boot.bin fip/bl33.bin
@@ -113,7 +108,7 @@
--level v3 --type bl31
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
--output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --level v3 --type bl33
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
--output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
@@ -124,11 +119,7 @@
--bl33 fip/bl33.bin.enc \
--ddrfw1 fip/ddr4_1d.fw \
--ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
--ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
--ddrfw8 fip/aml_ddr.fw \
--level v3
diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst
index a732fac..109337d 100644
--- a/doc/board/armltd/vexpress64.rst
+++ b/doc/board/armltd/vexpress64.rst
@@ -19,6 +19,11 @@
The supported FVPs are available free of charge and can be downloaded from the
Arm developer site [1]_ (user registration might be required).
+The Architecture Envelope Models (AEM) FVPs offer virtual platforms for Armv8-A,
+Armv9-A, and Armv8-R architectures, including a comprehensive set of System IP.
+For general use though, the Armv8-A Base Rev C FVP, which emulates a generic 64-bit
+Armv8-A hardware platform, is a suitable option.
+
Supported features:
* GICv3
@@ -31,6 +36,50 @@
The FVPs can be debugged using Arm Development Studio [2]_.
+Building U-Boot
+^^^^^^^^^^^^^^^
+
+Set the ``CROSS_COMPILE`` environment variable as usual, and run:
+
+.. code-block:: bash
+
+ make vexpress_fvp_defconfig
+ make
+
+Running U-Boot
+^^^^^^^^^^^^^^
+
+Set ``CROSS_COMPILE`` as usual and build TF-A:
+
+.. code-block:: bash
+
+ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ cd trusted-firmware-a
+ make PLAT=fvp BL33=/path/to/u-boot.bin fiptool all fip
+
+This command generates the ROM image `bl1.bin`, and a boot image `fip.bin` in
+TF-A's FIP format [5]_. It contains all images executed by TF-A, including U-Boot.
+Note that TF-A outputs the built binaries into `build/fvp/release/`.
+
+If you already have a FIP image, and are primarily interested in updating the BL33
+image (i.e., U-Boot), use `fiptool` from TF-A:
+
+.. code-block:: bash
+
+ make fiptool
+ tools/fiptool/fiptool update --nt-fw=/path/to/u-boot.bin /path/to/fip.bin
+
+To run the FVP:
+
+.. code-block:: bash
+
+ FVP_Base_RevC-2xAEMvA -C bp.flashloader0.fname=fip.bin \
+ -C bp.secureflashloader.fname=bl1.bin \
+ -C bp.vis.disable_visualisation=1
+
+This setup relies on semi-hosting, as well as, having a kernel image (``Image``)
+and ramdisk (``ramdisk.img``) in the current working directory.
+
Juno
----
@@ -62,7 +111,8 @@
References
----------
-.. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms
+.. [1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/Arm%20Architecture%20FVPs
.. [2] https://developer.arm.com/tools-and-software/embedded/arm-development-studio
.. [3] https://developer.arm.com/tools-and-software/development-boards/juno-development-board
-.. [4] https://trustedfirmware-a.readthedocs.io/
\ No newline at end of file
+.. [4] https://trustedfirmware-a.readthedocs.io/
+.. [5] https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/image-terminology.html#firmware-image-package-fip
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 84c135e..7ad1137 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -43,6 +43,7 @@
microsoft/index
nxp/index
openpiton/index
+ ouya/index
phytec/index
purism/index
qualcomm/index
diff --git a/doc/board/ouya/index.rst b/doc/board/ouya/index.rst
new file mode 100644
index 0000000..7413240
--- /dev/null
+++ b/doc/board/ouya/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+OUYA
+====
+
+.. toctree::
+ :maxdepth: 2
+
+ ouya
diff --git a/doc/board/ouya/ouya.rst b/doc/board/ouya/ouya.rst
new file mode 100644
index 0000000..641affc
--- /dev/null
+++ b/doc/board/ouya/ouya.rst
@@ -0,0 +1,124 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Ouya Game Console (ouya)
+=======================================
+
+``DISCLAMER!`` Moving your Ouya to use U-Boot assumes replacement of the
+vendor bootloader. Vendor android firmwares will no longer be able to run on the
+device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-none-eabi-
+ $ make ouya_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev ouya
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM. Regardless of the method bct and bootloader
+will end up in boot0 and boot1 partitions of eMMC.
+
+Flashing with the NV3P protocol
+*******************************
+
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ ./run_bootloader.sh -s T30 -t ./bct/ouya.bct -b android_bootloader.bin
+ $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
+
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, interrupt bootflow by pressing ``CTRL + C`` (USB keyboard
+must be plugged in before U-Boot is preloaded, else it will not work), input
+``bootmenu`` from the keyboard and hit enter. The bootmenu will appear. There, select
+``fastboot`` using the up and down arrows and enter key. After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally,
+bootmenu provides entries to mount eMMC as mass storage, fastboot, reboot,
+reboot RCM, poweroff, enter U-Boot console and update bootloader (check
+the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the USB. Enter
+bootmenu, choose update bootloader option with Enter and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/phytec/k3-common.rst b/doc/board/phytec/k3-common.rst
new file mode 100644
index 0000000..ffb50b5
--- /dev/null
+++ b/doc/board/phytec/k3-common.rst
@@ -0,0 +1,67 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov <w.egorov@phytec.de>
+
+Environment
+-----------
+
+
+Variables Set at Runtime
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+At runtime the `boot` environment variable is set to reflect the source from which the board was booted. This ensures that the correct boot path is followed for further system initialization.
+
+
+Environment Storage Selection
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The environment is loaded from a storage location based on the boot device:
+
+* If booted from eMMC or uSD card, the environment is retrieved from FAT or a fixed offset if configured.
+
+* If booted from SPI, the environment is retrieved from SPI flash if enabled.
+
+For all other boot devices, the environment is not stored persistently (ENVL_NOWHERE).
+
+
+Saving the Environment
+~~~~~~~~~~~~~~~~~~~~~~
+
+The `saveenv` command will store the environment on the same device the board was booted from, ensuring consistency between boot sources and stored configurations.
+
+
+Capsule Updates
+---------------
+
+Capsules for each of these binaries are automatically generated as part of the build process and are named `<binary>-capsule.bin`. For example, the capsule for `u-boot.img` is named `uboot-capsule.bin`.
+
+
+
+Performing an Update
+~~~~~~~~~~~~~~~~~~~~
+
+Each board has a dynamically generated GUID. To retrieve it, run:
+
+.. code-block::
+
+ efidebug capsule esrt
+
+To update the firmware, follow these steps on the board. Ensure the capsule binaries are available on a uSD card.
+
+.. code-block:: bash
+
+ load mmc 1:1 $loadaddr tiboot3-capsule.bin
+ efidebug capsule update $loadaddr
+
+ load mmc 1:1 $loadaddr tispl-capsule.bin
+ efidebug capsule update $loadaddr
+
+ load mmc 1:1 $loadaddr uboot-capsule.bin
+ efidebug capsule update $loadaddr
+
+These commands load the capsule binaries into memory and trigger the EFI capsule update process.
+
+
+Important Notes
+~~~~~~~~~~~~~~~
+
+The updates are applied to the boot device from which the board is currently running. For eMMC, updates are always applied to the first boot partition. Capsule updates can be performed on eMMC, OSPI NOR, or a uSD card, depending on the boot device. For any additional configuration or troubleshooting, refer to :ref:`uefi_capsule_update_ref`.
diff --git a/doc/board/phytec/phycore-am62ax.rst b/doc/board/phytec/phycore-am62ax.rst
index 0c5b481..e1f7410 100644
--- a/doc/board/phytec/phycore-am62ax.rst
+++ b/doc/board/phytec/phycore-am62ax.rst
@@ -176,6 +176,8 @@
- 11011100
- 00000000
+.. include:: k3-common.rst
+
Further Information
-------------------
diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst
index 56c1fd8..36315b4 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -176,6 +176,8 @@
- 11001010
- 00100000
+.. include:: k3-common.rst
+
Further Information
-------------------
diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst
index 01c42b9..71f1fd7 100644
--- a/doc/board/phytec/phycore-am64x.rst
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -175,6 +175,8 @@
- 11011100
- 00000000
+.. include:: k3-common.rst
+
Further Information
-------------------
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 8c79699..66bc922 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -10,3 +10,4 @@
rb3gen2
board
debugging
+ rdp
diff --git a/doc/board/qualcomm/rdp.rst b/doc/board/qualcomm/rdp.rst
new file mode 100644
index 0000000..fd14f1d
--- /dev/null
+++ b/doc/board/qualcomm/rdp.rst
@@ -0,0 +1,55 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. sectionauthor:: Varadarajan Narayanan <quic_varada@quicinc.com>
+
+Qualcomm Reference Design Platform (RDP)
+========================================
+
+Qualcomm RDPs are development boards based on the Qualcomm IPQ series of
+SoCs. These SoCs are used as the application processors in WiFi router
+platforms. RDPs come in multiple variants with differences in storage
+medium (NOR, NAND, MMC), no. of USB and PCIe ports, n/w ports etc.
+
+.. _Qualcomm's product page: https://www.qualcomm.com/products/internet-of-things/networking/wi-fi-networks/networking-pro-series/qualcomm-networking-pro-820-platform
+
+Installation
+------------
+First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``IPQ9574``::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make qcom_ipq9574_mmc_defconfig
+ $ make -j8
+
+This will build ``u-boot.elf`` in the configured output directory.
+
+Although the RDPs do not have secure boot set up by default, the firmware still
+expects firmware ELF images to be "signed". The signature does not provide any
+security in this case, but it provides the firmware with some required metadata.
+
+To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_::
+
+ $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf
+
+Then install the resulting ``u-boot.mbn`` to the ``0:APPSBL`` partition
+on your device with::
+
+ IPQ9574# tftpboot path/to/u-boot.mbn
+ IPQ9574# mmc part (note down the start & end block no.s of '0:APPSBL' partition)
+ IPQ9574# mmc erase <start blk no> <count>
+ IPQ9574# mmc write $fileaddr <blk no> <count>
+
+U-Boot should be running after a reboot (``reset``).
+
+.. WARNING
+ Boards with newer software versions would automatically go the emergency
+ download (EDL) mode if U-Boot is not functioning as expected. If its a
+ runtime failure at Uboot, the system will get reset (due to watchdog)
+ and XBL will try to boot from next bank and if Bank B also doesn't have
+ a functional image and is not booting fine, then the system will enter
+ EDL. A tool like bkerler's `edl`_ can be used for flashing with the
+ firehose loader binary appropriate for the board.
+
+ Note that the support added is very basic. Restoring the original U-Boot
+ on boards with older version of the software requires a debugger.
+
+.. _qtestsign: https://github.com/msm8916-mainline/qtestsign
+.. _edl: https://github.com/bkerler/edl
diff --git a/doc/develop/bitbangmii.rst b/doc/develop/bitbangmii.rst
new file mode 100644
index 0000000..35a4a0c
--- /dev/null
+++ b/doc/develop/bitbangmii.rst
@@ -0,0 +1,75 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>, Industrie Dial Face S.p.A., 2009
+
+Bit-banged MII bus support
+==========================
+
+The miiphybb ( Bit-banged MII bus driver ) supports an arbitrary number of
+MII buses. This feature is useful when a driver uses different MII buses for
+different PHYs and all (or a part) of these buses are implemented via
+bit-banging mode.
+
+The driver requires that the following macro is defined in the board
+configuration file:
+
+* CONFIG_BITBANGMII - Enable the miiphybb driver
+
+The driver code needs to allocate a regular MDIO device using mdio_alloc()
+and assign .read and .write accessors which wrap bb_miiphy_read() and
+bb_miiphy_write() functions respectively. The bb_miiphy_read() and
+bb_miiphy_write() functions take a pointer to a callback structure,
+struct bb_miiphy_bus_ops. The struct bb_miiphy_bus_ops has the following
+fields/callbacks (see miiphy.h for details):
+
+.. code-block:: c
+
+ int (*mdio_active)() // Activate the MDIO pin as output
+ int (*mdio_tristate)() // Activate the MDIO pin as input/tristate pin
+ int (*set_mdio)() // Write the MDIO pin
+ int (*get_mdio)() // Read the MDIO pin
+ int (*set_mdc)() // Write the MDC pin
+ int (*delay)() // Delay function
+
+The driver code will look like:
+
+.. code-block:: c
+
+ static const struct bb_miiphy_bus_ops ravb_bb_miiphy_bus_ops = {
+ .mdio_active = ravb_bb_mdio_active,
+ .mdio_tristate = ravb_bb_mdio_tristate,
+ .set_mdio = ravb_bb_set_mdio,
+ .get_mdio = ravb_bb_get_mdio,
+ .set_mdc = ravb_bb_set_mdc,
+ .delay = ravb_bb_delay,
+ };
+
+ static int ravb_bb_miiphy_read(struct mii_dev *miidev, int addr,
+ int devad, int reg)
+ {
+ return bb_miiphy_read(miidev, &ravb_bb_miiphy_bus_ops,
+ addr, devad, reg);
+ }
+
+ static int ravb_bb_miiphy_write(struct mii_dev *miidev, int addr,
+ int devad, int reg, u16 value)
+ {
+ return bb_miiphy_write(miidev, &ravb_bb_miiphy_bus_ops,
+ addr, devad, reg, value);
+ }
+
+ static int ravb_probe(struct udevice *dev)
+ {
+ struct mii_dev *mdiodev;
+ ...
+ mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+
+ mdiodev->read = ravb_bb_miiphy_read;
+ mdiodev->write = ravb_bb_miiphy_write;
+ mdiodev->priv = eth;
+ snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
+
+ ret = mdio_register(mdiodev);
+ ...
+ }
diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst
index 92f638a..3009373 100644
--- a/doc/develop/driver-model/design.rst
+++ b/doc/develop/driver-model/design.rst
@@ -843,8 +843,10 @@
activated and 'known' by the uclass.
For some platforms, certain devices must be probed to get the platform into
-a working state. To help with this, drivers marked with DM_FLAG_PROBE_AFTER_BIND
-will be probed immediately after all devices are bound. For now, this happens in
+a working state. To help with this, devices marked with DM_FLAG_PROBE_AFTER_BIND
+will be probed immediately after all devices are bound. This flag must be set
+on the device in its ``bind()`` function with
+``dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND)``. For now, this happens in
SPL, before relocation and after relocation. See the call to ``dm_autoprobe()``
for where this is done.
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index d9f2a83..c907f8c 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -9,6 +9,7 @@
.. toctree::
:maxdepth: 1
+ bitbangmii
board_best_practices
codingstyle
designprinciples
diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst
index b504730..40a8538 100644
--- a/doc/develop/py_testing.rst
+++ b/doc/develop/py_testing.rst
@@ -125,7 +125,7 @@
If sandbox crashes (e.g. with a segfault) you will see message like this::
- test/py/u_boot_spawn.py:171: in expect
+ test/py/spawn.py:171: in expect
c = os.read(self.fd, 1024).decode(errors='replace')
E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV)
@@ -506,24 +506,24 @@
Please refer to the pytest documentation for details of writing pytest tests.
Details specific to the U-Boot test suite are described below.
-A test fixture named `u_boot_console` should be used by each test function. This
+A test fixture named `ubman` should be used by each test function. This
provides the means to interact with the U-Boot console, and retrieve board and
environment configuration information.
-The function `u_boot_console.run_command()` executes a shell command on the
+The function `ubman.run_command()` executes a shell command on the
U-Boot console, and returns all output from that command. This allows
validation or interpretation of the command output. This function validates
that certain strings are not seen on the U-Boot console. These include shell
error messages and the U-Boot sign-on message (in order to detect unexpected
-board resets). See the source of `u_boot_console_base.py` for a complete list of
+board resets). See the source of `console_base.py` for a complete list of
"bad" strings. Some test scenarios are expected to trigger these strings. Use
-`u_boot_console.disable_check()` to temporarily disable checking for specific
+`ubman.disable_check()` to temporarily disable checking for specific
strings. See `test_unknown_cmd.py` for an example.
Board- and board-environment configuration values may be accessed as sub-fields
-of the `u_boot_console.config` object, for example
-`u_boot_console.config.ram_base`.
+of the `ubman.config` object, for example
+`ubman.config.ram_base`.
Build configuration values (from `.config`) may be accessed via the dictionary
-`u_boot_console.config.buildconfig`, with keys equal to the Kconfig variable
+`ubman.config.buildconfig`, with keys equal to the Kconfig variable
names.
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index dc5bb34..e736dc0 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -76,7 +76,7 @@
* U-Boot v2025.04-rc4 was released on Mon 10 March 2025.
-.. * U-Boot v2025.04-rc5 was released on Mon 24 March 2025.
+* U-Boot v2025.04-rc5 was released on Mon 24 March 2025.
Please note that the following dates are planned only and may be deviated from
as needed.
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index 5f3c43d..7ea1708 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -116,19 +116,19 @@
in Python::
@pytest.mark.buildconfigspec('cmd_memory')
- def test_md(u_boot_console):
+ def test_md(ubman):
"""Test that md reads memory as expected, and that memory can be modified
using the mw command."""
- ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ ram_base = utils.find_ram_base(ubman)
addr = '%08x' % ram_base
val = 'a5f09876'
expected_response = addr + ': ' + val
- u_boot_console.run_command('mw ' + addr + ' 0 10')
- response = u_boot_console.run_command('md ' + addr + ' 10')
+ ubman.run_command('mw ' + addr + ' 0 10')
+ response = ubman.run_command('md ' + addr + ' 10')
assert(not (expected_response in response))
- u_boot_console.run_command('mw ' + addr + ' ' + val)
- response = u_boot_console.run_command('md ' + addr + ' 10')
+ ubman.run_command('mw ' + addr + ' ' + val)
+ response = ubman.run_command('md ' + addr + ' 10')
assert(expected_response in response)
This runs a few commands and checks the output. Note that it runs a command,
diff --git a/doc/device-tree-bindings/mtd/cadence,nand.yaml b/doc/device-tree-bindings/mtd/cadence,nand.yaml
new file mode 100644
index 0000000..11ce023
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/cadence,nand.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence NAND controller
+
+maintainers:
+ - Dinesh Maniyam <dinesh.maniyam@intel.com>
+
+properties:
+ compatible:
+ enum:
+ - cdns,nand
+
+ reg-names:
+ description: |
+ There are two register regions:
+ reg: register interface
+ sdma: host data/command interface
+ items:
+ - const: reg
+ - const: sdma
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: |
+ There is one controller core clock
+ maxItems: 1
+
+ resets:
+ description: |
+ There are two resets:
+ controller core reset
+ combo-phy register reset
+ minItems: 1
+ maxItems: 2
+
+ cdns,board-delay-ps:
+ description: |
+ Estimated Board delay. The value includes the total
+ round trip delay for the signals and is used for deciding on values
+ associated with data read capture. The example formula for SDR mode is
+ the following:
+ board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+ + DQ PAD delay
+ enum:
+ - 4830
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ compatible:
+ const: cdns,nand
+
+ reg:
+ maxItems: 1
+
+ label:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - cdns,board-delay-ps
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ nand-controller@60000000 {
+ compatible = "cdns,nand";
+ reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
+ reg-names = "reg", "sdma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk>;
+ cdns,board-delay-ps = <4830>;
+ interrupts = <2 0>;
+ nand@0 {
+ label = "nand-0";
+ reg = <0>;
+ };
+ nand@1 {
+ label = "nand-1";
+ reg = <1>;
+ };
+ };
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 34eed13..473c65b 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -17,6 +17,30 @@
struct blkmap;
/**
+ * define BLKMAP_SLICE_LINEAR - Linear mapping to another block device
+ *
+ * This blkmap slice type is used for mapping to other existing block
+ * devices.
+ */
+#define BLKMAP_SLICE_LINEAR BIT(0)
+
+/**
+ * define BLKMAP_SLICE_MEM - Linear mapping to memory based block device
+ *
+ * This blkmap slice type is used for mapping to memory based block
+ * devices, like ramdisks.
+ */
+#define BLKMAP_SLICE_MEM BIT(1)
+
+/**
+ * define BLKMAP_SLICE_PRESERVE - Preserved blkmap slice
+ *
+ * This blkmap slice is intended to be preserved, and it's
+ * information passed on to a later stage, like OS.
+ */
+#define BLKMAP_SLICE_PRESERVE BIT(2)
+
+/**
* struct blkmap_slice - Region mapped to a blkmap
*
* Common data for a region mapped to a blkmap, specialized by each
@@ -25,12 +49,14 @@
* @node: List node used to associate this slice with a blkmap
* @blknr: Start block number of the mapping
* @blkcnt: Number of blocks covered by this mapping
+ * @attr: Attributes of blkmap slice
*/
struct blkmap_slice {
struct list_head node;
lbaint_t blknr;
lbaint_t blkcnt;
+ uint attr;
/**
* @read: - Read from slice
@@ -169,6 +195,7 @@
.slice = {
.blknr = blknr,
.blkcnt = blkcnt,
+ .attr = BLKMAP_SLICE_LINEAR,
.read = blkmap_linear_read,
.write = blkmap_linear_write,
@@ -234,7 +261,7 @@
}
int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
- void *addr, bool remapped)
+ void *addr, bool remapped, bool preserve)
{
struct blkmap *bm = dev_get_plat(dev);
struct blkmap_mem *bmm;
@@ -248,6 +275,7 @@
.slice = {
.blknr = blknr,
.blkcnt = blkcnt,
+ .attr = BLKMAP_SLICE_MEM,
.read = blkmap_mem_read,
.write = blkmap_mem_write,
@@ -258,6 +286,9 @@
.remapped = remapped,
};
+ if (preserve)
+ bmm->slice.attr |= BLKMAP_SLICE_PRESERVE;
+
err = blkmap_slice_add(bm, &bmm->slice);
if (err)
free(bmm);
@@ -268,11 +299,11 @@
int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
void *addr)
{
- return __blkmap_map_mem(dev, blknr, blkcnt, addr, false);
+ return __blkmap_map_mem(dev, blknr, blkcnt, addr, false, false);
}
int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
- phys_addr_t paddr)
+ phys_addr_t paddr, bool preserve)
{
struct blkmap *bm = dev_get_plat(dev);
struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
@@ -283,7 +314,7 @@
if (!addr)
return -ENOMEM;
- err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true);
+ err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true, preserve);
if (err)
unmap_sysmem(addr);
@@ -486,6 +517,49 @@
return err;
}
+static bool blkmap_mem_preserve_slice(struct blkmap_slice *bms)
+{
+ return (bms->attr & (BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE)) ==
+ (BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE);
+}
+
+int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr,
+ u64 size), void *ctx)
+{
+ int ret;
+ u64 addr, size;
+ struct udevice *dev;
+ struct uclass *uc;
+ struct blkmap *bm;
+ struct blkmap_mem *bmm;
+ struct blkmap_slice *bms;
+ struct blk_desc *bd;
+
+ if (!cb) {
+ log_debug("%s: No callback passed to the function\n", __func__);
+ return 0;
+ }
+
+ uclass_id_foreach_dev(UCLASS_BLKMAP, dev, uc) {
+ bm = dev_get_plat(dev);
+ bd = dev_get_uclass_plat(bm->blk);
+
+ list_for_each_entry(bms, &bm->slices, node) {
+ if (!blkmap_mem_preserve_slice(bms))
+ continue;
+
+ bmm = container_of(bms, struct blkmap_mem, slice);
+ addr = (u64)(uintptr_t)bmm->addr;
+ size = (u64)bms->blkcnt << bd->log2blksz;
+ ret = cb(ctx, addr, size);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
int blkmap_destroy(struct udevice *dev)
{
int err;
diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c
index bfba141..2f1bc28 100644
--- a/drivers/block/blkmap_helper.c
+++ b/drivers/block/blkmap_helper.c
@@ -28,7 +28,7 @@
bm = dev_get_plat(bm_dev);
desc = dev_get_uclass_plat(bm->blk);
blknum = image_size >> desc->log2blksz;
- ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr);
+ ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr, true);
if (ret) {
log_err("Unable to map %#llx at block %d : %d\n",
(unsigned long long)image_addr, 0, ret);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 199ca6e..9e3b519 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -97,7 +97,7 @@
return 0;
}
-struct clk *clk_register_composite(struct device *dev, const char *name,
+struct clk *clk_register_composite(struct udevice *dev, const char *name,
const char * const *parent_names,
int num_parents, struct clk *mux,
const struct clk_ops *mux_ops,
@@ -149,7 +149,7 @@
clk = &composite->clk;
clk->flags = flags;
ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
- parent_names[clk_composite_get_parent(clk)]);
+ clk_resolve_parent_clk(dev, parent_names[clk_composite_get_parent(clk)]));
if (ret) {
clk = ERR_PTR(ret);
goto err;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index aa210e3..e692b9c 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -183,7 +183,7 @@
.set_rate = clk_divider_set_rate,
};
-static struct clk *_register_divider(struct device *dev, const char *name,
+static struct clk *_register_divider(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags, const struct clk_div_table *table)
@@ -218,7 +218,8 @@
clk = &div->clk;
clk->flags = flags;
- ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
+ ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name,
+ clk_resolve_parent_clk(dev, parent_name));
if (ret) {
kfree(div);
return ERR_PTR(ret);
@@ -227,7 +228,7 @@
return clk;
}
-struct clk *clk_register_divider(struct device *dev, const char *name,
+struct clk *clk_register_divider(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 068798c..4eb8be7 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -37,7 +37,7 @@
.get_rate = clk_factor_recalc_rate,
};
-struct clk *clk_hw_register_fixed_factor(struct device *dev,
+struct clk *clk_hw_register_fixed_factor(struct udevice *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
@@ -56,7 +56,7 @@
clk->flags = flags;
ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name,
- parent_name);
+ clk_resolve_parent_clk(dev, parent_name));
if (ret) {
kfree(fix);
return ERR_PTR(ret);
@@ -65,7 +65,7 @@
return clk;
}
-struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
{
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index bf1c6a9..256ff10 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -117,7 +117,7 @@
.get_rate = clk_generic_get_rate,
};
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock)
@@ -149,7 +149,8 @@
clk = &gate->clk;
clk->flags = flags;
- ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
+ ret = clk_register(clk, UBOOT_DM_CLK_GATE, name,
+ clk_resolve_parent_clk(dev, parent_name));
if (ret) {
kfree(gate);
return ERR_PTR(ret);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 62477e1..d7411f8 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -113,6 +113,11 @@
for (i = 0; i < mux->num_parents; i++) {
if (!strcmp(parent->dev->name, mux->parent_names[i]))
return i;
+ if (!strcmp(parent->dev->name,
+ clk_resolve_parent_clk(clk->dev,
+ mux->parent_names[i])))
+ return i;
+
}
return -EINVAL;
@@ -159,15 +164,15 @@
.set_parent = clk_mux_set_parent,
};
-struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
+struct clk *clk_register_mux(struct udevice *dev, const char *name,
const char * const *parent_names, u8 num_parents,
unsigned long flags,
- void __iomem *reg, u8 shift, u32 mask,
- u8 clk_mux_flags, u32 *table)
+ void __iomem *reg, u8 shift, u8 width,
+ u8 clk_mux_flags)
{
+ u32 mask = BIT(width) - 1;
struct clk_mux *mux;
struct clk *clk;
- u8 width = 0;
int ret;
if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
@@ -192,7 +197,7 @@
mux->shift = shift;
mux->mask = mask;
mux->flags = clk_mux_flags;
- mux->table = table;
+ mux->table = NULL;
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
mux->io_mux_val = *(u32 *)reg;
#endif
@@ -207,7 +212,8 @@
* for the corresponding clock (to do that define .set_parent() method).
*/
ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
- parent_names[clk_mux_get_parent(clk)]);
+ clk_resolve_parent_clk(dev,
+ parent_names[clk_mux_get_parent(clk)]));
if (ret) {
kfree(mux);
return ERR_PTR(ret);
@@ -216,35 +222,6 @@
return clk;
}
-struct clk *clk_register_mux_table(struct device *dev, const char *name,
- const char * const *parent_names, u8 num_parents,
- unsigned long flags,
- void __iomem *reg, u8 shift, u32 mask,
- u8 clk_mux_flags, u32 *table)
-{
- struct clk *clk;
-
- clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
- flags, reg, shift, mask, clk_mux_flags,
- table);
- if (IS_ERR(clk))
- return ERR_CAST(clk);
- return clk;
-}
-
-struct clk *clk_register_mux(struct device *dev, const char *name,
- const char * const *parent_names, u8 num_parents,
- unsigned long flags,
- void __iomem *reg, u8 shift, u8 width,
- u8 clk_mux_flags)
-{
- u32 mask = BIT(width) - 1;
-
- return clk_register_mux_table(dev, name, parent_names, num_parents,
- flags, reg, shift, mask, clk_mux_flags,
- NULL);
-}
-
U_BOOT_DRIVER(ccf_clk_mux) = {
.name = UBOOT_DM_CLK_CCF_MUX,
.id = UCLASS_CLK,
diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 5fbbb07..343fa5c 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -50,6 +50,7 @@
static const struct udevice_id stub_clk_ids[] = {
{ .compatible = "qcom,rpmcc" },
+ { .compatible = "qcom,sc7280-rpmh-clk" },
{ .compatible = "qcom,sm8150-rpmh-clk" },
{ .compatible = "qcom,sm8250-rpmh-clk" },
{ .compatible = "qcom,sm8550-rpmh-clk" },
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 353ae47..90b7052 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -420,6 +420,24 @@
return clk_get_by_index_nodev(node, index, clk);
}
+const char *
+clk_resolve_parent_clk(struct udevice *dev, const char *name)
+{
+ struct udevice *parent;
+ struct clk clk;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, name, &parent);
+ if (!ret)
+ return name;
+
+ ret = clk_get_by_name(dev, name, &clk);
+ if (!clk.dev)
+ return name;
+
+ return clk.dev->name;
+}
+
int clk_release_all(struct clk *clk, unsigned int count)
{
unsigned int i;
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 56d893e..d17a54f 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -60,6 +60,7 @@
depends on ARCH_IMX8M && SPL
select SPL_CLK
select SPL_CLK_CCF
+ select SPL_CLK_COMPOSITE_CCF
help
This enables SPL DM/DTS support for clock driver in i.MX8MP
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 64bffa3..14c5b92 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -151,7 +151,7 @@
.set_parent = imx8m_clk_mux_set_parent,
};
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg,
unsigned long flags)
@@ -187,7 +187,7 @@
gate->reg = reg;
gate->bit_idx = PCG_CGC_SHIFT;
- clk = clk_register_composite(NULL, name,
+ clk = clk_register_composite(dev, name,
parent_names, num_parents,
&mux->clk, &imx8m_clk_mux_ops, &div->clk,
&imx8m_clk_composite_divider_ops,
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 65fa6b5..fa07b13 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -90,7 +90,7 @@
.get_rate = clk_generic_get_rate,
};
-struct clk *clk_register_gate2(struct device *dev, const char *name,
+struct clk *clk_register_gate2(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx, u8 cgr_val,
u8 clk_gate2_flags, unsigned int *share_count)
@@ -111,7 +111,8 @@
clk = &gate->clk;
- ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name);
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name,
+ clk_resolve_parent_clk(dev, parent_name));
if (ret) {
kfree(gate);
return ERR_PTR(ret);
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index df9f028..13239f2 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,8 @@
static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
"pll2_pfd0_352m", "pll2_198m", };
+static const char *const uart_sels[] = { "pll3_80m", "osc", };
+static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
static int imx6q_clk_probe(struct udevice *dev)
{
@@ -44,21 +46,21 @@
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX6QDL_CLK_PLL2,
- imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc",
base + 0x30, 0x1));
clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
- imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
base + 0x10, 0x3));
clk_dm(IMX6QDL_CLK_PLL3_60M,
- imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
+ imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8));
clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
clk_dm(IMX6QDL_CLK_PLL6,
- imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
+ imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
clk_dm(IMX6QDL_CLK_PLL6_ENET,
- imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
+ imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
/* CCM clocks */
base = dev_read_addr_ptr(dev);
@@ -66,76 +68,98 @@
return -EINVAL;
clk_dm(IMX6QDL_CLK_USDHC1_SEL,
- imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMX6QDL_CLK_USDHC2_SEL,
- imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMX6QDL_CLK_USDHC3_SEL,
- imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
+ imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMX6QDL_CLK_USDHC4_SEL,
- imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
+ imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ if (of_machine_is_compatible("fsl,imx6qp")) {
+ clk_dm(IMX6QDL_CLK_UART_SEL,
+ imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels,
+ ARRAY_SIZE(uart_sels)));
+ clk_dm(IMX6QDL_CLK_ECSPI_SEL,
+ imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
+ ARRAY_SIZE(ecspi_sels)));
+ }
+
clk_dm(IMX6QDL_CLK_USDHC1_PODF,
- imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
clk_dm(IMX6QDL_CLK_USDHC2_PODF,
- imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
base + 0x24, 16, 3));
clk_dm(IMX6QDL_CLK_USDHC3_PODF,
- imx_clk_divider("usdhc3_podf", "usdhc3_sel",
+ imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel",
base + 0x24, 19, 3));
clk_dm(IMX6QDL_CLK_USDHC4_PODF,
- imx_clk_divider("usdhc4_podf", "usdhc4_sel",
+ imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel",
base + 0x24, 22, 3));
- clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
- imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+ if (of_machine_is_compatible("fsl,imx6qp")) {
+ clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+ imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6));
+ clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+ imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
+ } else {
+ clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+ imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6));
+ clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+ imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+ }
clk_dm(IMX6QDL_CLK_ECSPI1,
- imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+ imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0));
clk_dm(IMX6QDL_CLK_ECSPI2,
- imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
+ imx_clk_gate2(dev, "ecspi2", "ecspi_root", base + 0x6c, 2));
clk_dm(IMX6QDL_CLK_ECSPI3,
- imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
+ imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4));
clk_dm(IMX6QDL_CLK_ECSPI4,
- imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+ imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6));
+ clk_dm(IMX6QDL_CLK_UART_IPG,
+ imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24));
+ clk_dm(IMX6QDL_CLK_UART_SERIAL,
+ imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", base + 0x7c, 26));
clk_dm(IMX6QDL_CLK_USDHC1,
- imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
clk_dm(IMX6QDL_CLK_USDHC2,
- imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
clk_dm(IMX6QDL_CLK_USDHC3,
- imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
+ imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6));
clk_dm(IMX6QDL_CLK_USDHC4,
- imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
+ imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8));
clk_dm(IMX6QDL_CLK_PERIPH_PRE,
- imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
+ imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels,
ARRAY_SIZE(periph_pre_sels)));
clk_dm(IMX6QDL_CLK_PERIPH,
- imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48,
+ imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48,
5, periph_sels, ARRAY_SIZE(periph_sels)));
clk_dm(IMX6QDL_CLK_AHB,
- imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
+ imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3,
base + 0x48, 1));
clk_dm(IMX6QDL_CLK_IPG,
- imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
+ imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2));
clk_dm(IMX6QDL_CLK_IPG_PER,
- imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
+ imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6));
clk_dm(IMX6QDL_CLK_I2C1,
- imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
+ imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6));
clk_dm(IMX6QDL_CLK_I2C2,
- imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
+ imx_clk_gate2(dev, "i2c2", "ipg_per", base + 0x70, 8));
clk_dm(IMX6QDL_CLK_I2C3,
- imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10));
+ imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10));
clk_dm(IMX6QDL_CLK_PWM1,
- imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16));
+ imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16));
- clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
+ clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
clk_dm(IMX6QDL_CLK_ENET_REF,
- imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
+ imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1));
return 0;
}
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index bb6958f..b81db51 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -14,7 +14,7 @@
#include "clk.h"
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -23,128 +23,144 @@
static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
-static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
-static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll1_out", };
#ifndef CONFIG_XPL_BUILD
-static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll1_out", "sys_pll3_out", };
-static const char * const imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll1_out", "clk_ext4", };
-static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
"clk_ext4", "video_pll1_out", };
-static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
"sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
"audio_pll2_out", };
#endif
-static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
-static const char * const imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
-static const char * const imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
-static const char * const imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
+static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+ "audio_pll2_out", };
+
+static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+ "audio_pll2_out", };
+
+static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+ "audio_pll2_out", };
+
+static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+ "audio_pll2_out", };
+
#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
-static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m",
+static const char * const imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m",
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll2_333m", "sys_pll3_out", };
-static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m",
+static const char * const imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
"clk_ext1", "clk_ext2", "clk_ext3",
"clk_ext4", "sys_pll1_400m", };
-static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+static const char * const imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", "sys_pll1_200m", };
#endif
#ifndef CONFIG_XPL_BUILD
-static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
#endif
-static const char * const imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
-static const char * const imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_clk", "sys_pll1_100m", };
#if CONFIG_IS_ENABLED(NXP_FSPI)
-static const char * const imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
"sys_pll3_out", "sys_pll1_100m", };
#endif
-static const char * const imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
#if CONFIG_IS_ENABLED(DM_SPI)
-static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
#endif
@@ -156,19 +172,19 @@
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
- imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_ARM_PLL_REF_SEL,
- imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
- imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+ imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
- imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+ imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
- imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MM_DRAM_PLL,
@@ -189,238 +205,254 @@
/* PLL bypass out */
clk_dm(IMX8MM_DRAM_PLL_BYPASS,
- imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+ imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
dram_pll_bypass_sels,
ARRAY_SIZE(dram_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_ARM_PLL_BYPASS,
- imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+ imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
arm_pll_bypass_sels,
ARRAY_SIZE(arm_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_SYS_PLL1_BYPASS,
- imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
sys_pll1_bypass_sels,
ARRAY_SIZE(sys_pll1_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_SYS_PLL2_BYPASS,
- imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
sys_pll2_bypass_sels,
ARRAY_SIZE(sys_pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MM_SYS_PLL3_BYPASS,
- imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
sys_pll3_bypass_sels,
ARRAY_SIZE(sys_pll3_bypass_sels),
CLK_SET_RATE_PARENT));
/* PLL out gate */
clk_dm(IMX8MM_DRAM_PLL_OUT,
- imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+ imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass",
base + 0x50, 13));
clk_dm(IMX8MM_ARM_PLL_OUT,
- imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+ imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
base + 0x84, 11));
clk_dm(IMX8MM_SYS_PLL1_OUT,
- imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+ imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass",
base + 0x94, 11));
clk_dm(IMX8MM_SYS_PLL2_OUT,
- imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+ imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass",
base + 0x104, 11));
clk_dm(IMX8MM_SYS_PLL3_OUT,
- imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+ imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass",
base + 0x114, 11));
/* SYS PLL fixed output */
clk_dm(IMX8MM_SYS_PLL1_40M,
- imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+ imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
clk_dm(IMX8MM_SYS_PLL1_80M,
- imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+ imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
clk_dm(IMX8MM_SYS_PLL1_100M,
- imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+ imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
clk_dm(IMX8MM_SYS_PLL1_133M,
- imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+ imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
clk_dm(IMX8MM_SYS_PLL1_160M,
- imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+ imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
clk_dm(IMX8MM_SYS_PLL1_200M,
- imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+ imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
clk_dm(IMX8MM_SYS_PLL1_266M,
- imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+ imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
clk_dm(IMX8MM_SYS_PLL1_400M,
- imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
clk_dm(IMX8MM_SYS_PLL1_800M,
- imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+ imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
clk_dm(IMX8MM_SYS_PLL2_50M,
- imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+ imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
clk_dm(IMX8MM_SYS_PLL2_100M,
- imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+ imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
clk_dm(IMX8MM_SYS_PLL2_125M,
- imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+ imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
clk_dm(IMX8MM_SYS_PLL2_166M,
- imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+ imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
clk_dm(IMX8MM_SYS_PLL2_200M,
- imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+ imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
clk_dm(IMX8MM_SYS_PLL2_250M,
- imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+ imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
clk_dm(IMX8MM_SYS_PLL2_333M,
- imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+ imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
clk_dm(IMX8MM_SYS_PLL2_500M,
- imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
clk_dm(IMX8MM_SYS_PLL2_1000M,
- imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+ imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
base = dev_read_addr_ptr(dev);
if (!base)
return -EINVAL;
clk_dm(IMX8MM_CLK_A53_SRC,
- imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
clk_dm(IMX8MM_CLK_A53_CG,
- imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
clk_dm(IMX8MM_CLK_A53_DIV,
- imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+ imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
base + 0x8000, 0, 3));
clk_dm(IMX8MM_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels,
base + 0x9000));
clk_dm(IMX8MM_CLK_IPG_ROOT,
- imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+ imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mm_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MM_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
/* IP */
#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
clk_dm(IMX8MM_CLK_PCIE1_CTRL,
- imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+ imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
base + 0xa300));
clk_dm(IMX8MM_CLK_PCIE1_PHY,
- imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+ imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels,
base + 0xa380));
clk_dm(IMX8MM_CLK_PCIE1_AUX,
- imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+ imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels,
base + 0xa400));
#endif
clk_dm(IMX8MM_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MM_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MM_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base + 0xad00));
clk_dm(IMX8MM_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base + 0xad80));
clk_dm(IMX8MM_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base + 0xae00));
clk_dm(IMX8MM_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ imx8m_clk_composite(dev, "i2c4", imx8mm_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MM_CLK_UART1,
+ imx8m_clk_composite(dev, "uart1", imx8mm_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MM_CLK_UART2,
+ imx8m_clk_composite(dev, "uart2", imx8mm_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MM_CLK_UART3,
+ imx8m_clk_composite(dev, "uart3", imx8mm_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MM_CLK_UART4,
+ imx8m_clk_composite(dev, "uart4", imx8mm_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MM_CLK_UART1_ROOT,
+ imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+ clk_dm(IMX8MM_CLK_UART2_ROOT,
+ imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+ clk_dm(IMX8MM_CLK_UART3_ROOT,
+ imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+ clk_dm(IMX8MM_CLK_UART4_ROOT,
+ imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MM_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mm_wdog_sels, base + 0xb900));
clk_dm(IMX8MM_CLK_USDHC3,
- imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
+ imx8m_clk_composite(dev, "usdhc3", imx8mm_usdhc3_sels,
base + 0xbc80));
clk_dm(IMX8MM_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
clk_dm(IMX8MM_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
- imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,
- imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MM_CLK_I2C3_ROOT,
- imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MM_CLK_I2C4_ROOT,
- imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MM_CLK_OCOTP_ROOT,
- imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
clk_dm(IMX8MM_CLK_USDHC1_ROOT,
- imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MM_CLK_USDHC2_ROOT,
- imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
clk_dm(IMX8MM_CLK_WDOG1_ROOT,
- imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+ imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
clk_dm(IMX8MM_CLK_WDOG2_ROOT,
- imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+ imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
clk_dm(IMX8MM_CLK_WDOG3_ROOT,
- imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MM_CLK_USDHC3_ROOT,
- imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+ imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
- imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+ imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MM_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mm_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MM_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mm_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MM_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mm_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MM_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mm_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MM_CLK_ENET1_ROOT,
- imx_clk_gate4("enet1_root_clk", "enet_axi",
+ imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
clk_dm(IMX8MM_CLK_PWM1,
- imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ imx8m_clk_composite(dev, "pwm1", imx8mm_pwm1_sels, base + 0xb380));
clk_dm(IMX8MM_CLK_PWM2,
- imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ imx8m_clk_composite(dev, "pwm2", imx8mm_pwm2_sels, base + 0xb400));
clk_dm(IMX8MM_CLK_PWM3,
- imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ imx8m_clk_composite(dev, "pwm3", imx8mm_pwm3_sels, base + 0xb480));
clk_dm(IMX8MM_CLK_PWM4,
- imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
+ imx8m_clk_composite(dev, "pwm4", imx8mm_pwm4_sels, base + 0xb500));
clk_dm(IMX8MM_CLK_PWM1_ROOT,
- imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MM_CLK_PWM2_ROOT,
- imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
clk_dm(IMX8MM_CLK_PWM3_ROOT,
- imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
clk_dm(IMX8MM_CLK_PWM4_ROOT,
- imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+ imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
#endif
#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
clk_dm(IMX8MM_CLK_PCIE1_ROOT,
- imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
+ imx_clk_gate4(dev, "pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
#endif
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MM_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MM_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MM_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
- imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
- imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
- imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+ imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
#endif
#if CONFIG_IS_ENABLED(NXP_FSPI)
clk_dm(IMX8MM_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mm_qspi_sels, base + 0xab80));
clk_dm(IMX8MM_CLK_QSPI_ROOT,
- imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+ imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
#endif
clk_dm(IMX8MM_CLK_ARM,
- imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+ imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
imx8mm_arm_core_sels,
ARRAY_SIZE(imx8mm_arm_core_sels),
CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index be15ebd..be5b793 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -16,7 +16,7 @@
static u32 share_count_nand;
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -25,117 +25,133 @@
static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
-static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
-static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll_out", };
-static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll_out", "sys_pll3_out", };
#ifndef CONFIG_XPL_BUILD
-static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll_out", "clk_ext4", };
-static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
"clk_ext4", "video_pll_out", };
-static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
"video_pll_out", "audio_pll2_out", };
#endif
-static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
-static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
-static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
#if CONFIG_IS_ENABLED(DM_SPI)
-static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
#endif
-static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
+static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+ "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+ "clk_ext3", "audio_pll2_out", };
+
#ifndef CONFIG_XPL_BUILD
-static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll_out", };
-static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll_out", };
-static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll_out", };
-static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll_out", };
#endif
-static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
"m7_alt_pll", "sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m", };
-static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_clk", "sys_pll1_100m", };
-static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
"sys_pll3_out", "sys_pll1_100m", };
-static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out",
+static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
"sys_pll2_250m", "video_pll_out", };
-static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
@@ -148,19 +164,19 @@
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
- imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MN_ARM_PLL_REF_SEL,
- imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
- imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+ imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
- imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+ imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
- imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MN_DRAM_PLL,
@@ -181,86 +197,86 @@
/* PLL bypass out */
clk_dm(IMX8MN_DRAM_PLL_BYPASS,
- imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+ imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
dram_pll_bypass_sels,
ARRAY_SIZE(dram_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MN_ARM_PLL_BYPASS,
- imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+ imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
arm_pll_bypass_sels,
ARRAY_SIZE(arm_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MN_SYS_PLL1_BYPASS,
- imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
sys_pll1_bypass_sels,
ARRAY_SIZE(sys_pll1_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MN_SYS_PLL2_BYPASS,
- imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
sys_pll2_bypass_sels,
ARRAY_SIZE(sys_pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MN_SYS_PLL3_BYPASS,
- imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+ imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
sys_pll3_bypass_sels,
ARRAY_SIZE(sys_pll3_bypass_sels),
CLK_SET_RATE_PARENT));
/* PLL out gate */
clk_dm(IMX8MN_DRAM_PLL_OUT,
- imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+ imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass",
base + 0x50, 13));
clk_dm(IMX8MN_ARM_PLL_OUT,
- imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+ imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
base + 0x84, 11));
clk_dm(IMX8MN_SYS_PLL1_OUT,
- imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+ imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass",
base + 0x94, 11));
clk_dm(IMX8MN_SYS_PLL2_OUT,
- imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+ imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass",
base + 0x104, 11));
clk_dm(IMX8MN_SYS_PLL3_OUT,
- imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+ imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass",
base + 0x114, 11));
/* SYS PLL fixed output */
clk_dm(IMX8MN_SYS_PLL1_40M,
- imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+ imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
clk_dm(IMX8MN_SYS_PLL1_80M,
- imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+ imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
clk_dm(IMX8MN_SYS_PLL1_100M,
- imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+ imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
clk_dm(IMX8MN_SYS_PLL1_133M,
- imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+ imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
clk_dm(IMX8MN_SYS_PLL1_160M,
- imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+ imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
clk_dm(IMX8MN_SYS_PLL1_200M,
- imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+ imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
clk_dm(IMX8MN_SYS_PLL1_266M,
- imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+ imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
clk_dm(IMX8MN_SYS_PLL1_400M,
- imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
clk_dm(IMX8MN_SYS_PLL1_800M,
- imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+ imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
clk_dm(IMX8MN_SYS_PLL2_50M,
- imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+ imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
clk_dm(IMX8MN_SYS_PLL2_100M,
- imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+ imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
clk_dm(IMX8MN_SYS_PLL2_125M,
- imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+ imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
clk_dm(IMX8MN_SYS_PLL2_166M,
- imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+ imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
clk_dm(IMX8MN_SYS_PLL2_200M,
- imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+ imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
clk_dm(IMX8MN_SYS_PLL2_250M,
- imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+ imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
clk_dm(IMX8MN_SYS_PLL2_333M,
- imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+ imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
clk_dm(IMX8MN_SYS_PLL2_500M,
- imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
clk_dm(IMX8MN_SYS_PLL2_1000M,
- imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+ imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
if (ret)
@@ -272,141 +288,157 @@
return -EINVAL;
clk_dm(IMX8MN_CLK_A53_SRC,
- imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
clk_dm(IMX8MN_CLK_A53_CG,
- imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
clk_dm(IMX8MN_CLK_A53_DIV,
- imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+ imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
base + 0x8000, 0, 3));
clk_dm(IMX8MN_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels,
base + 0x9000));
clk_dm(IMX8MN_CLK_IPG_ROOT,
- imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+ imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MN_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mn_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MN_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
/* IP */
clk_dm(IMX8MN_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MN_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MN_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00));
clk_dm(IMX8MN_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80));
clk_dm(IMX8MN_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00));
clk_dm(IMX8MN_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+ imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MN_CLK_UART1,
+ imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MN_CLK_UART2,
+ imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MN_CLK_UART3,
+ imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MN_CLK_UART4,
+ imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080));
clk_dm(IMX8MN_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900));
clk_dm(IMX8MN_CLK_USDHC3,
- imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
+ imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels,
base + 0xbc80));
clk_dm(IMX8MN_CLK_NAND,
- imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
+ imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00));
clk_dm(IMX8MN_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80));
clk_dm(IMX8MN_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
clk_dm(IMX8MN_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MN_CLK_I2C1_ROOT,
- imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MN_CLK_I2C2_ROOT,
- imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MN_CLK_I2C3_ROOT,
- imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MN_CLK_I2C4_ROOT,
- imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MN_CLK_OCOTP_ROOT,
- imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
clk_dm(IMX8MN_CLK_USDHC1_ROOT,
- imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MN_CLK_USDHC2_ROOT,
- imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
clk_dm(IMX8MN_CLK_WDOG1_ROOT,
- imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+ imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
clk_dm(IMX8MN_CLK_WDOG2_ROOT,
- imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+ imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
clk_dm(IMX8MN_CLK_WDOG3_ROOT,
- imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MN_CLK_USDHC3_ROOT,
- imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+ imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MN_CLK_QSPI_ROOT,
- imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+ imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
clk_dm(IMX8MN_CLK_NAND_ROOT,
- imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
+ imx_clk_gate2_shared2(dev, "nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
- imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
+ imx_clk_gate2_shared2(dev, "nand_usdhc_rawnand_clk",
"nand_usdhc_bus", base + 0x4300, 0,
&share_count_nand));
+ clk_dm(IMX8MN_CLK_UART1_ROOT,
+ imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+ clk_dm(IMX8MN_CLK_UART2_ROOT,
+ imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+ clk_dm(IMX8MN_CLK_UART3_ROOT,
+ imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+ clk_dm(IMX8MN_CLK_UART4_ROOT,
+ imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
- imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+ imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MN_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MN_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MN_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MN_CLK_ENET1_ROOT,
- imx_clk_gate4("enet1_root_clk", "enet_axi",
+ imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
clk_dm(IMX8MN_CLK_PWM1,
- imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
+ imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380));
clk_dm(IMX8MN_CLK_PWM2,
- imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
+ imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400));
clk_dm(IMX8MN_CLK_PWM3,
- imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
+ imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480));
clk_dm(IMX8MN_CLK_PWM4,
- imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
+ imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500));
clk_dm(IMX8MN_CLK_PWM1_ROOT,
- imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MN_CLK_PWM2_ROOT,
- imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
clk_dm(IMX8MN_CLK_PWM3_ROOT,
- imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
clk_dm(IMX8MN_CLK_PWM4_ROOT,
- imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+ imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
#endif
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MN_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MN_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MN_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
- imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
- imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
- imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+ imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
#endif
clk_dm(IMX8MN_CLK_ARM,
- imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+ imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
imx8mn_arm_core_sels,
ARRAY_SIZE(imx8mn_arm_core_sels),
CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 1d04090..bad579f 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -14,7 +14,7 @@
#include "clk.h"
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -23,167 +23,167 @@
static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
-static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
-static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
+static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
"video_pll1_out", "sys_pll1_100m",};
-static const char * const imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll1_out", "sys_pll3_out", };
-static const char * const imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll1_out", };
-static const char * const imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
+static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", };
-static const char * const imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
+static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", };
-static const char * const imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll1_out", };
-static const char * const imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
+static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
"audio_pll1_out", "sys_pll1_266m", };
-static const char * const imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", "sys_pll1_200m", };
-static const char * const imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll1_out", "clk_ext4", };
-static const char * const imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
"clk_ext4", "video_pll1_out", };
-static const char * const imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
-static const char * const imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
-static const char * const imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
-static const char * const imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext4", "audio_pll2_out", };
-static const char * const imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
"clk_ext3", "audio_pll2_out", };
-static const char * const imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
-static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
-static const char * const imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
-static const char * const imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
"sys_pll1_80m", "sys_pll2_166m" };
-static const char * const imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
"sys_pll3_out", "sys_pll1_100m", };
-static const char * const imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
-static const char * const imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll1_out", "clk_ext4", };
-static const char * const imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
"clk_ext4", "video_pll1_out", };
-static const char * const imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", };
@@ -199,11 +199,11 @@
clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
- clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
- clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
- clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
- clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
- clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
&imx_1443x_dram_pll));
@@ -216,37 +216,37 @@
clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
&imx_1416x_pll));
- clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
- clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
- clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
- clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
- clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
+ clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
- clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
- clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
- clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
- clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
- clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
+ clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
+ clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
+ clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
+ clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
+ clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
- clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
- clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
- clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
- clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
- clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
- clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
- clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
- clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
- clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+ clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
+ clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
+ clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
+ clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
+ clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
+ clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
+ clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
+ clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
+ clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
- clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
- clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
- clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
- clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
- clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
- clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
- clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
- clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
- clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+ clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
+ clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
+ clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
+ clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
+ clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
+ clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
+ clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
+ clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
+ clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
if (ret)
@@ -262,104 +262,104 @@
if (!base)
return -EINVAL;
- clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
- clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
- clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
+ clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
+ clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
- clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
- clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
- clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
- clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
- clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
- clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
+ clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
+ clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800));
+ clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
+ clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
+ clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00));
+ clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80));
- clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
+ clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000));
- clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
+ clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root", "ahb_root", base + 0x9080, 0, 1));
- clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
- clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
- clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
- clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
- clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
- clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
- clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
- clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
- clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
- clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
- clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
- clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
- clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
- clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
- clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
- clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
- clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
+ clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
+ clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
+ clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite(dev, "pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
+ clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite(dev, "i2c5", imx8mp_i2c5_sels, base + 0xa480));
+ clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite(dev, "i2c6", imx8mp_i2c6_sels, base + 0xa500));
+ clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite(dev, "enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
+ clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite(dev, "enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
+ clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite(dev, "enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
+ clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite(dev, "enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
+ clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite(dev, "enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
+ clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite(dev, "qspi", imx8mp_qspi_sels, base + 0xab80));
+ clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite(dev, "usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
+ clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite(dev, "usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
+ clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite(dev, "i2c1", imx8mp_i2c1_sels, base + 0xad00));
+ clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite(dev, "i2c2", imx8mp_i2c2_sels, base + 0xad80));
+ clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite(dev, "i2c3", imx8mp_i2c3_sels, base + 0xae00));
+ clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite(dev, "i2c4", imx8mp_i2c4_sels, base + 0xae80));
- clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
- clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
- clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
- clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
- clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
- clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
- clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
- clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
- clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
- clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380));
- clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400));
- clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480));
- clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500));
- clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
+ clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite(dev, "uart1", imx8mp_uart1_sels, base + 0xaf00));
+ clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite(dev, "uart2", imx8mp_uart2_sels, base + 0xaf80));
+ clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite(dev, "uart3", imx8mp_uart3_sels, base + 0xb000));
+ clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite(dev, "uart4", imx8mp_uart4_sels, base + 0xb080));
+ clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite(dev, "usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
+ clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite(dev, "usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
+ clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical(dev, "gic", imx8mp_gic_sels, base + 0xb200));
+ clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite(dev, "ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite(dev, "ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical(dev, "pwm1", imx8mp_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical(dev, "pwm2", imx8mp_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical(dev, "pwm3", imx8mp_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical(dev, "pwm4", imx8mp_pwm4_sels, base + 0xb500));
+ clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite(dev, "ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
- clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
- clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
+ clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900));
+ clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
- clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
- clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
+ clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
+ clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
- clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
- clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
- clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
- clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
- clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
- clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
- clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
- clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
- clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
- clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
- clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
- clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
- clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
- clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
- clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0));
- clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
- clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
- clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
- clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
- clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
- clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
- clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
- clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
- clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
- clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
- clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
- clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
- clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
- clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
- clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
- clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));
- clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0));
- clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
- clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
- clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
- clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
- clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
- clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
- clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0));
+ clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags(dev, "dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
+ clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+ clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0));
+ clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4(dev, "gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
+ clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4(dev, "gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
+ clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4(dev, "gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
+ clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4(dev, "gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
+ clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4(dev, "gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
+ clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4(dev, "pcie_root_clk", "pcie_aux", base + 0x4250, 0));
+ clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+ clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4(dev, "qos_root_clk", "ipg_root", base + 0x42c0, 0));
+ clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4(dev, "qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
+ clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
+ clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2(dev, "i2c5_root_clk", "i2c5", base + 0x4330, 0));
+ clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2(dev, "i2c6_root_clk", "i2c6", base + 0x4340, 0));
+ clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4(dev, "sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
+ clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4(dev, "enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
+ clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+ clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+ clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+ clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
+ clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2(dev, "usb_root_clk", "hsio_axi", base + 0x44d0, 0));
+ clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "osc_24m", base + 0x44d0, 0));
+ clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4(dev, "usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+ clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
+ clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
+ clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
+ clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk", "ipg_root", base + 0x45c0, 0));
- clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+ clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MP_CLK_ARM,
- imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+ imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
imx8mp_arm_core_sels,
ARRAY_SIZE(imx8mp_arm_core_sels),
CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index ed4acd7..fe6cba1 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -152,31 +152,31 @@
clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000));
clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL,
- imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2,
+ imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x60, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_ARM_PLL_REF_SEL,
- imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2,
+ imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_GPU_PLL_REF_SEL,
- imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2,
+ imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_VPU_PLL_REF_SEL,
- imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2,
+ imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL,
- imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2,
+ imx_clk_mux(dev, "sys3_pll_ref_sel", base + 0x48, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL,
- imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+ imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL,
- imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2,
+ imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL,
- imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2,
+ imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL,
- imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2,
+ imx_clk_mux(dev, "video_pll2_ref_sel", base + 0x54, 0, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMX8MQ_ARM_PLL,
@@ -207,140 +207,140 @@
/* PLL bypass out */
clk_dm(IMX8MQ_ARM_PLL_BYPASS,
- imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1,
+ imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x28, 4, 1,
arm_pll_bypass_sels,
ARRAY_SIZE(arm_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MQ_GPU_PLL_BYPASS,
- imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1,
+ imx_clk_mux_flags(dev, "gpu_pll_bypass", base + 0x18, 4, 1,
gpu_pll_bypass_sels,
ARRAY_SIZE(gpu_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MQ_VPU_PLL_BYPASS,
- imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1,
+ imx_clk_mux_flags(dev, "vpu_pll_bypass", base + 0x20, 4, 1,
vpu_pll_bypass_sels,
ARRAY_SIZE(vpu_pll_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS,
- imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1,
+ imx_clk_mux_flags(dev, "audio_pll1_bypass", base + 0x0, 4, 1,
audio_pll1_bypass_sels,
ARRAY_SIZE(audio_pll1_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS,
- imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1,
+ imx_clk_mux_flags(dev, "audio_pll2_bypass", base + 0x8, 4, 1,
audio_pll2_bypass_sels,
ARRAY_SIZE(audio_pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS,
- imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1,
+ imx_clk_mux_flags(dev, "video_pll1_bypass", base + 0x10, 4, 1,
video_pll1_bypass_sels,
ARRAY_SIZE(video_pll1_bypass_sels),
CLK_SET_RATE_PARENT));
/* PLL out gate */
clk_dm(IMX8MQ_DRAM_PLL_OUT,
- imx_clk_gate("dram_pll_out", "dram_pll_ref_sel",
+ imx_clk_gate(dev, "dram_pll_out", "dram_pll_ref_sel",
base + 0x60, 13));
clk_dm(IMX8MQ_ARM_PLL_OUT,
- imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+ imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
base + 0x28, 11));
clk_dm(IMX8MQ_GPU_PLL_OUT,
- imx_clk_gate("gpu_pll_out", "gpu_pll_bypass",
+ imx_clk_gate(dev, "gpu_pll_out", "gpu_pll_bypass",
base + 0x18, 11));
clk_dm(IMX8MQ_VPU_PLL_OUT,
- imx_clk_gate("vpu_pll_out", "vpu_pll_bypass",
+ imx_clk_gate(dev, "vpu_pll_out", "vpu_pll_bypass",
base + 0x20, 11));
clk_dm(IMX8MQ_AUDIO_PLL1_OUT,
- imx_clk_gate("audio_pll1_out", "audio_pll1_bypass",
+ imx_clk_gate(dev, "audio_pll1_out", "audio_pll1_bypass",
base + 0x0, 11));
clk_dm(IMX8MQ_AUDIO_PLL2_OUT,
- imx_clk_gate("audio_pll2_out", "audio_pll2_bypass",
+ imx_clk_gate(dev, "audio_pll2_out", "audio_pll2_bypass",
base + 0x8, 11));
clk_dm(IMX8MQ_VIDEO_PLL1_OUT,
- imx_clk_gate("video_pll1_out", "video_pll1_bypass",
+ imx_clk_gate(dev, "video_pll1_out", "video_pll1_bypass",
base + 0x10, 11));
clk_dm(IMX8MQ_SYS1_PLL_OUT,
- imx_clk_gate("sys_pll1_out", "sys1_pll",
+ imx_clk_gate(dev, "sys_pll1_out", "sys1_pll",
base + 0x30, 11));
clk_dm(IMX8MQ_SYS2_PLL_OUT,
- imx_clk_gate("sys_pll2_out", "sys2_pll",
+ imx_clk_gate(dev, "sys_pll2_out", "sys2_pll",
base + 0x3c, 11));
clk_dm(IMX8MQ_SYS3_PLL_OUT,
- imx_clk_gate("sys_pll3_out", "sys3_pll",
+ imx_clk_gate(dev, "sys_pll3_out", "sys3_pll",
base + 0x48, 11));
clk_dm(IMX8MQ_VIDEO2_PLL_OUT,
- imx_clk_gate("video_pll2_out", "video_pll2_ref_sel",
+ imx_clk_gate(dev, "video_pll2_out", "video_pll2_ref_sel",
base + 0x54, 11));
/* SYS PLL fixed output */
clk_dm(IMX8MQ_SYS1_PLL_40M,
- imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+ imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
clk_dm(IMX8MQ_SYS1_PLL_80M,
- imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+ imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
clk_dm(IMX8MQ_SYS1_PLL_100M,
- imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+ imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
clk_dm(IMX8MQ_SYS1_PLL_133M,
- imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+ imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
clk_dm(IMX8MQ_SYS1_PLL_160M,
- imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+ imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
clk_dm(IMX8MQ_SYS1_PLL_200M,
- imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+ imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
clk_dm(IMX8MQ_SYS1_PLL_266M,
- imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+ imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
clk_dm(IMX8MQ_SYS1_PLL_400M,
- imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
clk_dm(IMX8MQ_SYS1_PLL_800M,
- imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+ imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
clk_dm(IMX8MQ_SYS2_PLL_50M,
- imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+ imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
clk_dm(IMX8MQ_SYS2_PLL_100M,
- imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+ imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
clk_dm(IMX8MQ_SYS2_PLL_125M,
- imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+ imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
clk_dm(IMX8MQ_SYS2_PLL_166M,
- imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+ imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
clk_dm(IMX8MQ_SYS2_PLL_200M,
- imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+ imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
clk_dm(IMX8MQ_SYS2_PLL_250M,
- imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+ imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
clk_dm(IMX8MQ_SYS2_PLL_333M,
- imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+ imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
clk_dm(IMX8MQ_SYS2_PLL_500M,
- imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
clk_dm(IMX8MQ_SYS2_PLL_1000M,
- imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+ imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV,
- imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
+ imx_clk_divider(dev, "audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV,
- imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
+ imx_clk_divider(dev, "audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV,
- imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
+ imx_clk_divider(dev, "video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV,
- imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
+ imx_clk_divider(dev, "gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV,
- imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
+ imx_clk_divider(dev, "vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV,
- imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
+ imx_clk_divider(dev, "arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV,
- imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
+ imx_clk_divider(dev, "sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV,
- imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
+ imx_clk_divider(dev, "sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV,
- imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
+ imx_clk_divider(dev, "sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV,
- imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
+ imx_clk_divider(dev, "dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV,
- imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
+ imx_clk_divider(dev, "video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
clk_dm(IMX8MQ_CLK_MON_SEL,
- imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4,
+ imx_clk_mux_flags(dev, "pllout_monitor_sel", base + 0x74, 0, 4,
pllout_monitor_sels,
ARRAY_SIZE(pllout_monitor_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMX8MQ_CLK_MON_CLK2_OUT,
- imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
+ imx_clk_gate4(dev, "pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
base = dev_read_addr_ptr(dev);
if (!base) {
@@ -349,140 +349,140 @@
}
clk_dm(IMX8MQ_CLK_A53_SRC,
- imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+ imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)));
clk_dm(IMX8MQ_CLK_A53_CG,
- imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+ imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
clk_dm(IMX8MQ_CLK_A53_DIV,
- imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+ imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
base + 0x8000, 0, 3));
clk_dm(IMX8MQ_CLK_A53_CORE,
- imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1,
+ imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1,
imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)));
clk_dm(IMX8MQ_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels,
base + 0x9000));
clk_dm(IMX8MQ_CLK_IPG_ROOT,
- imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+ imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MQ_CLK_ENET_AXI,
- imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels,
+ imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels,
base + 0x8880));
clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mq_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MQ_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
/* DRAM */
clk_dm(IMX8MQ_CLK_DRAM_CORE,
- imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1,
+ imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1,
imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels)));
clk_dm(IMX8MQ_CLK_DRAM_ALT,
- imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
+ imx8m_clk_composite(dev, "dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
clk_dm(IMX8MQ_CLK_DRAM_APB,
- imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
+ imx8m_clk_composite_critical(dev, "dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
/* IP */
clk_dm(IMX8MQ_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mq_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MQ_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mq_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MQ_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mq_i2c1_sels, base + 0xad00));
clk_dm(IMX8MQ_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mq_i2c2_sels, base + 0xad80));
clk_dm(IMX8MQ_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mq_i2c3_sels, base + 0xae00));
clk_dm(IMX8MQ_CLK_I2C4,
- imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80));
+ imx8m_clk_composite(dev, "i2c4", imx8mq_i2c4_sels, base + 0xae80));
clk_dm(IMX8MQ_CLK_WDOG,
- imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900));
+ imx8m_clk_composite(dev, "wdog", imx8mq_wdog_sels, base + 0xb900));
clk_dm(IMX8MQ_CLK_UART1,
- imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00));
+ imx8m_clk_composite(dev, "uart1", imx8mq_uart1_sels, base + 0xaf00));
clk_dm(IMX8MQ_CLK_UART2,
- imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80));
+ imx8m_clk_composite(dev, "uart2", imx8mq_uart2_sels, base + 0xaf80));
clk_dm(IMX8MQ_CLK_UART3,
- imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000));
+ imx8m_clk_composite(dev, "uart3", imx8mq_uart3_sels, base + 0xb000));
clk_dm(IMX8MQ_CLK_UART4,
- imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080));
+ imx8m_clk_composite(dev, "uart4", imx8mq_uart4_sels, base + 0xb080));
clk_dm(IMX8MQ_CLK_QSPI,
- imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80));
+ imx8m_clk_composite(dev, "qspi", imx8mq_qspi_sels, base + 0xab80));
clk_dm(IMX8MQ_CLK_USB_CORE_REF,
- imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
+ imx8m_clk_composite(dev, "usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
clk_dm(IMX8MQ_CLK_USB_PHY_REF,
- imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
+ imx8m_clk_composite(dev, "usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
clk_dm(IMX8MQ_CLK_ECSPI1,
- imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
+ imx8m_clk_composite(dev, "ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MQ_CLK_ECSPI2,
- imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
+ imx8m_clk_composite(dev, "ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MQ_CLK_ECSPI3,
- imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
+ imx8m_clk_composite(dev, "ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MQ_CLK_ECSPI1_ROOT,
- imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MQ_CLK_ECSPI2_ROOT,
- imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
clk_dm(IMX8MQ_CLK_ECSPI3_ROOT,
- imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+ imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
clk_dm(IMX8MQ_CLK_I2C1_ROOT,
- imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+ imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MQ_CLK_I2C2_ROOT,
- imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+ imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MQ_CLK_I2C3_ROOT,
- imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+ imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MQ_CLK_I2C4_ROOT,
- imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MQ_CLK_UART1_ROOT,
- imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+ imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
clk_dm(IMX8MQ_CLK_UART2_ROOT,
- imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+ imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
clk_dm(IMX8MQ_CLK_UART3_ROOT,
- imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+ imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
clk_dm(IMX8MQ_CLK_UART4_ROOT,
- imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+ imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
clk_dm(IMX8MQ_CLK_OCOTP_ROOT,
- imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+ imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
clk_dm(IMX8MQ_CLK_USDHC1_ROOT,
- imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+ imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MQ_CLK_USDHC2_ROOT,
- imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+ imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
clk_dm(IMX8MQ_CLK_WDOG1_ROOT,
- imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+ imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
clk_dm(IMX8MQ_CLK_WDOG2_ROOT,
- imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+ imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
clk_dm(IMX8MQ_CLK_WDOG3_ROOT,
- imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+ imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
clk_dm(IMX8MQ_CLK_QSPI_ROOT,
- imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+ imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT,
- imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+ imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT,
- imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
+ imx_clk_gate4(dev, "usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT,
- imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+ imx_clk_gate4(dev, "usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT,
- imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
+ imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
clk_dm(IMX8MQ_CLK_ENET_REF,
- imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels,
+ imx8m_clk_composite(dev, "enet_ref", imx8mq_enet_ref_sels,
base + 0xa980));
clk_dm(IMX8MQ_CLK_ENET_TIMER,
- imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels,
+ imx8m_clk_composite(dev, "enet_timer", imx8mq_enet_timer_sels,
base + 0xaa00));
clk_dm(IMX8MQ_CLK_ENET_PHY_REF,
- imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels,
+ imx8m_clk_composite(dev, "enet_phy", imx8mq_enet_phy_sels,
base + 0xaa80));
clk_dm(IMX8MQ_CLK_ENET1_ROOT,
- imx_clk_gate4("enet1_root_clk", "enet_axi",
+ imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
base + 0x40a0, 0));
clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT,
- imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
+ imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
return 0;
}
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index b31e57a..c311296 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -291,15 +291,15 @@
clk_dm(IMX93_CLK_SYS_PLL_PFD0,
clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000));
clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2,
- imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
clk_dm(IMX93_CLK_SYS_PLL_PFD1,
clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000));
clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2,
- imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
clk_dm(IMX93_CLK_SYS_PLL_PFD2,
clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000));
clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
- imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
+ imx_clk_fixed_factor(dev, "sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
anatop_base = (void *)ANATOP_BASE_ADDR;
@@ -338,7 +338,7 @@
}
clk_dm(IMX93_CLK_A55_SEL,
- imx_clk_mux2("a55_sel", base + 0x4820, 0, 1,
+ imx_clk_mux2(dev, "a55_sel", base + 0x4820, 0, 1,
a55_core_sels, ARRAY_SIZE(a55_core_sels)));
return 0;
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 752434c..c14afda 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -38,26 +38,26 @@
base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
clk_dm(IMXRT1020_CLK_PLL2_SYS,
- imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc",
base + 0x30, 0x1));
clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
- imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
base + 0x10, 0x1));
/* PLL bypass out */
clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
- imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+ imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
pll2_bypass_sels,
ARRAY_SIZE(pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
- imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+ imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
pll3_bypass_sels,
ARRAY_SIZE(pll3_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1020_CLK_PLL3_80M,
- imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+ imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6));
clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
@@ -78,51 +78,51 @@
return -EINVAL;
clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
- imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+ imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2,
pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
clk_dm(IMXRT1020_CLK_PERIPH_SEL,
- imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+ imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1,
periph_sels, ARRAY_SIZE(periph_sels)));
clk_dm(IMXRT1020_CLK_USDHC1_SEL,
- imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMXRT1020_CLK_USDHC2_SEL,
- imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMXRT1020_CLK_LPUART_SEL,
- imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+ imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1,
lpuart_sels, ARRAY_SIZE(lpuart_sels)));
clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
- imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+ imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1,
semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
clk_dm(IMXRT1020_CLK_SEMC_SEL,
- imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+ imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1,
semc_sels, ARRAY_SIZE(semc_sels)));
clk_dm(IMXRT1020_CLK_AHB_PODF,
- imx_clk_divider("ahb_podf", "periph_sel",
+ imx_clk_divider(dev, "ahb_podf", "periph_sel",
base + 0x14, 10, 3));
clk_dm(IMXRT1020_CLK_USDHC1_PODF,
- imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
clk_dm(IMXRT1020_CLK_USDHC2_PODF,
- imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
base + 0x24, 16, 3));
clk_dm(IMXRT1020_CLK_LPUART_PODF,
- imx_clk_divider("lpuart_podf", "lpuart_sel",
+ imx_clk_divider(dev, "lpuart_podf", "lpuart_sel",
base + 0x24, 0, 6));
clk_dm(IMXRT1020_CLK_SEMC_PODF,
- imx_clk_divider("semc_podf", "semc_sel",
+ imx_clk_divider(dev, "semc_podf", "semc_sel",
base + 0x14, 16, 3));
clk_dm(IMXRT1020_CLK_USDHC1,
- imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
clk_dm(IMXRT1020_CLK_USDHC2,
- imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
clk_dm(IMXRT1020_CLK_LPUART1,
- imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+ imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1020_CLK_SEMC,
- imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+ imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4));
#ifdef CONFIG_XPL_BUILD
struct clk *clk, *clk1;
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 2c029ec..ba5b487 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -36,63 +36,63 @@
base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
- imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
+ imx_clk_mux(dev, "pll1_arm_ref_sel", base + 0x0, 14, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
- imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
+ imx_clk_mux(dev, "pll2_sys_ref_sel", base + 0x30, 14, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
- imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
+ imx_clk_mux(dev, "pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
- imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
+ imx_clk_mux(dev, "pll5_video_ref_sel", base + 0xa0, 14, 2,
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMXRT1050_CLK_PLL1_ARM,
- imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
+ imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
base + 0x0, 0x7f));
clk_dm(IMXRT1050_CLK_PLL2_SYS,
- imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
base + 0x30, 0x1));
clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
- imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
+ imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg",
"pll3_usb_otg_ref_sel",
base + 0x10, 0x1));
clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
- imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
+ imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
base + 0xa0, 0x7f));
/* PLL bypass out */
clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
- imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
+ imx_clk_mux_flags(dev, "pll1_bypass", base + 0x0, 16, 1,
pll1_bypass_sels,
ARRAY_SIZE(pll1_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
- imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+ imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
pll2_bypass_sels,
ARRAY_SIZE(pll2_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
- imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+ imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
pll3_bypass_sels,
ARRAY_SIZE(pll3_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
- imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
+ imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1,
pll5_bypass_sels,
ARRAY_SIZE(pll5_bypass_sels),
CLK_SET_RATE_PARENT));
clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
- imx_clk_divider("video_post_div_sel", "pll5_video",
+ imx_clk_divider(dev, "video_post_div_sel", "pll5_video",
base + 0xa0, 19, 2));
clk_dm(IMXRT1050_CLK_VIDEO_DIV,
- imx_clk_divider("video_div", "video_post_div_sel",
+ imx_clk_divider(dev, "video_div", "video_post_div_sel",
base + 0x170, 30, 2));
clk_dm(IMXRT1050_CLK_PLL3_80M,
- imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+ imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6));
clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
@@ -113,73 +113,73 @@
return -EINVAL;
clk_dm(IMXRT1050_CLK_ARM_PODF,
- imx_clk_divider("arm_podf", "pll1_arm",
+ imx_clk_divider(dev, "arm_podf", "pll1_arm",
base + 0x10, 0, 3));
clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
- imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+ imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2,
pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
clk_dm(IMXRT1050_CLK_PERIPH_SEL,
- imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+ imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1,
periph_sels, ARRAY_SIZE(periph_sels)));
clk_dm(IMXRT1050_CLK_USDHC1_SEL,
- imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMXRT1050_CLK_USDHC2_SEL,
- imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
usdhc_sels, ARRAY_SIZE(usdhc_sels)));
clk_dm(IMXRT1050_CLK_LPUART_SEL,
- imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+ imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1,
lpuart_sels, ARRAY_SIZE(lpuart_sels)));
clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
- imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+ imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1,
semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
clk_dm(IMXRT1050_CLK_SEMC_SEL,
- imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+ imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1,
semc_sels, ARRAY_SIZE(semc_sels)));
clk_dm(IMXRT1050_CLK_LCDIF_SEL,
- imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
+ imx_clk_mux(dev, "lcdif_sel", base + 0x38, 15, 3,
lcdif_sels, ARRAY_SIZE(lcdif_sels)));
clk_dm(IMXRT1050_CLK_AHB_PODF,
- imx_clk_divider("ahb_podf", "periph_sel",
+ imx_clk_divider(dev, "ahb_podf", "periph_sel",
base + 0x14, 10, 3));
clk_dm(IMXRT1050_CLK_IPG_PDOF,
- imx_clk_divider("ipg_podf", "ahb_podf",
+ imx_clk_divider(dev, "ipg_podf", "ahb_podf",
base + 0x14, 8, 2));
clk_dm(IMXRT1050_CLK_USDHC1_PODF,
- imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
base + 0x24, 11, 3));
clk_dm(IMXRT1050_CLK_USDHC2_PODF,
- imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
base + 0x24, 16, 3));
clk_dm(IMXRT1050_CLK_LPUART_PODF,
- imx_clk_divider("lpuart_podf", "lpuart_sel",
+ imx_clk_divider(dev, "lpuart_podf", "lpuart_sel",
base + 0x24, 0, 6));
clk_dm(IMXRT1050_CLK_SEMC_PODF,
- imx_clk_divider("semc_podf", "semc_sel",
+ imx_clk_divider(dev, "semc_podf", "semc_sel",
base + 0x14, 16, 3));
clk_dm(IMXRT1050_CLK_LCDIF_PRED,
- imx_clk_divider("lcdif_pred", "lcdif_sel",
+ imx_clk_divider(dev, "lcdif_pred", "lcdif_sel",
base + 0x38, 12, 3));
clk_dm(IMXRT1050_CLK_LCDIF_PODF,
- imx_clk_divider("lcdif_podf", "lcdif_pred",
+ imx_clk_divider(dev, "lcdif_podf", "lcdif_pred",
base + 0x18, 23, 3));
clk_dm(IMXRT1050_CLK_USDHC1,
- imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
clk_dm(IMXRT1050_CLK_USDHC2,
- imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
clk_dm(IMXRT1050_CLK_LPUART1,
- imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+ imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1050_CLK_SEMC,
- imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+ imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4));
clk_dm(IMXRT1050_CLK_LCDIF_APB,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ imx_clk_gate2(dev, "lcdif", "lcdif_podf", base + 0x70, 28));
clk_dm(IMXRT1050_CLK_LCDIF_PIX,
- imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
+ imx_clk_gate2(dev, "lcdif_pix", "lcdif", base + 0x74, 10));
clk_dm(IMXRT1050_CLK_USBOH3,
- imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0));
+ imx_clk_gate2(dev, "usboh3", "pll3_usb_otg", base + 0x80, 0));
struct clk *clk, *clk1;
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
index 88a294f..3f55d0d 100644
--- a/drivers/clk/imx/clk-imxrt1170.c
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -114,20 +114,20 @@
base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
clk_dm(IMXRT1170_CLK_RCOSC_48M,
- imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
+ imx_clk_fixed_factor(dev, "rcosc48M", "rcosc16M", 3, 1));
clk_dm(IMXRT1170_CLK_RCOSC_400M,
- imx_clk_fixed_factor("rcosc400M", "rcosc16M", 25, 1));
+ imx_clk_fixed_factor(dev, "rcosc400M", "rcosc16M", 25, 1));
clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
- imx_clk_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2));
+ imx_clk_fixed_factor(dev, "rcosc48M_div2", "rcosc48M", 1, 2));
clk_dm(IMXRT1170_CLK_PLL_ARM,
- imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc",
base + 0x200, 0xff));
clk_dm(IMXRT1170_CLK_PLL3,
- imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
base + 0x210, 1));
clk_dm(IMXRT1170_CLK_PLL2,
- imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
base + 0x240, 1));
clk_dm(IMXRT1170_CLK_PLL3_PFD0,
@@ -149,7 +149,7 @@
imx_clk_pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3));
clk_dm(IMXRT1170_CLK_PLL3_DIV2,
- imx_clk_fixed_factor("pll3_div2", "pll3_sys", 1, 2));
+ imx_clk_fixed_factor(dev, "pll3_div2", "pll3_sys", 1, 2));
/* CCM clocks */
base = dev_read_addr_ptr(dev);
@@ -157,31 +157,31 @@
return -EINVAL;
clk_dm(IMXRT1170_CLK_LPUART1_SEL,
- imx_clk_mux("lpuart1_sel", base + (25 * 0x80), 8, 3,
+ imx_clk_mux(dev, "lpuart1_sel", base + (25 * 0x80), 8, 3,
lpuart1_sels, ARRAY_SIZE(lpuart1_sels)));
clk_dm(IMXRT1170_CLK_LPUART1,
- imx_clk_divider("lpuart1", "lpuart1_sel",
+ imx_clk_divider(dev, "lpuart1", "lpuart1_sel",
base + (25 * 0x80), 0, 8));
clk_dm(IMXRT1170_CLK_USDHC1_SEL,
- imx_clk_mux("usdhc1_sel", base + (58 * 0x80), 8, 3,
+ imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3,
usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));
clk_dm(IMXRT1170_CLK_USDHC1,
- imx_clk_divider("usdhc1", "usdhc1_sel",
+ imx_clk_divider(dev, "usdhc1", "usdhc1_sel",
base + (58 * 0x80), 0, 8));
clk_dm(IMXRT1170_CLK_GPT1_SEL,
- imx_clk_mux("gpt1_sel", base + (14 * 0x80), 8, 3,
+ imx_clk_mux(dev, "gpt1_sel", base + (14 * 0x80), 8, 3,
gpt1_sels, ARRAY_SIZE(gpt1_sels)));
clk_dm(IMXRT1170_CLK_GPT1,
- imx_clk_divider("gpt1", "gpt1_sel",
+ imx_clk_divider(dev, "gpt1", "gpt1_sel",
base + (14 * 0x80), 0, 8));
clk_dm(IMXRT1170_CLK_SEMC_SEL,
- imx_clk_mux("semc_sel", base + (4 * 0x80), 8, 3,
+ imx_clk_mux(dev, "semc_sel", base + (4 * 0x80), 8, 3,
semc_sels, ARRAY_SIZE(semc_sels)));
clk_dm(IMXRT1170_CLK_SEMC,
- imx_clk_divider("semc", "semc_sel",
+ imx_clk_divider(dev, "semc", "semc_sel",
base + (4 * 0x80), 0, 8));
struct clk *clk, *clk1;
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index c6692f2..85b6a98 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -281,9 +281,9 @@
.get_rate = clk_pllv3_enet_get_rate,
};
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
- const char *parent_name, void __iomem *base,
- u32 div_mask)
+struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type,
+ const char *name, const char *parent_name,
+ void __iomem *base, u32 div_mask)
{
struct clk_pllv3 *pll;
struct clk *clk;
@@ -339,7 +339,8 @@
pll->div_mask = div_mask;
clk = &pll->clk;
- ret = clk_register(clk, drv_name, name, parent_name);
+ ret = clk_register(clk, drv_name, name,
+ clk_resolve_parent_clk(dev, parent_name));
if (ret) {
kfree(pll);
return ERR_PTR(ret);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 27a53ae..7d14dbc 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -78,84 +78,89 @@
void __iomem *base,
const struct imx_pll14xx_clk *pll_clk);
-struct clk *clk_register_gate2(struct device *dev, const char *name,
+struct clk *clk_register_gate2(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx, u8 cgr_val,
u8 clk_gate_flags, unsigned int *share_count);
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
- const char *parent_name, void __iomem *base,
- u32 div_mask);
+struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type,
+ const char *name, const char *parent_name,
+ void __iomem *base, u32 div_mask);
-static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
- void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg,
+ u8 shift)
{
- return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg,
shift, 0x3, 0, NULL);
}
-static inline struct clk *imx_clk_gate2_shared(const char *name,
+static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name,
const char *parent,
void __iomem *reg, u8 shift,
unsigned int *share_count)
{
- return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg,
shift, 0x3, 0, share_count);
}
-static inline struct clk *imx_clk_gate2_shared2(const char *name,
+static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char *name,
const char *parent,
void __iomem *reg, u8 shift,
unsigned int *share_count)
{
- return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
+ return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT |
CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
share_count);
}
-static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+static inline struct clk *imx_clk_gate4(struct udevice *dev, const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
- return clk_register_gate2(NULL, name, parent,
+ return clk_register_gate2(dev, name, parent,
CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
reg, shift, 0x3, 0, NULL);
}
-static inline struct clk *imx_clk_gate4_flags(const char *name,
+static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *name,
const char *parent, void __iomem *reg, u8 shift,
unsigned long flags)
{
- return clk_register_gate2(NULL, name, parent,
+ return clk_register_gate2(dev, name, parent,
flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
reg, shift, 0x3, 0, NULL);
}
-static inline struct clk *imx_clk_fixed_factor(const char *name,
- const char *parent, unsigned int mult, unsigned int div)
+static inline struct clk *
+imx_clk_fixed_factor(struct udevice *dev, const char *name, const char *parent,
+ unsigned int mult, unsigned int div)
{
- return clk_register_fixed_factor(NULL, name, parent,
+ return clk_register_fixed_factor(dev, name, parent,
CLK_SET_RATE_PARENT, mult, div);
}
-static inline struct clk *imx_clk_divider(const char *name, const char *parent,
- void __iomem *reg, u8 shift, u8 width)
+static inline struct clk *imx_clk_divider(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg,
+ u8 shift, u8 width)
{
- return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
reg, shift, width, 0);
}
static inline struct clk *
-imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg,
- u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift)
+imx_clk_busy_divider(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg, u8 shift, u8 width,
+ void __iomem *busy_reg, u8 busy_shift)
{
- return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+ return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
reg, shift, width, 0);
}
-static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
- void __iomem *reg, u8 shift, u8 width)
+static inline struct clk *imx_clk_divider2(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg,
+ u8 shift, u8 width)
{
- return clk_register_divider(NULL, name, parent,
+ return clk_register_divider(dev, name, parent,
CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
reg, shift, width, 0);
}
@@ -167,90 +172,93 @@
u8 shift, u8 width, const char * const *parents,
int num_parents, void (*fixup)(u32 *val));
-static inline struct clk *imx_clk_mux_flags(const char *name,
+static inline struct clk *imx_clk_mux_flags(struct udevice *dev, const char *name,
void __iomem *reg, u8 shift, u8 width,
const char * const *parents, int num_parents,
unsigned long flags)
{
- return clk_register_mux(NULL, name, parents, num_parents,
+ return clk_register_mux(dev, name, parents, num_parents,
flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
width, 0);
}
-static inline struct clk *imx_clk_mux2_flags(const char *name,
+static inline struct clk *imx_clk_mux2_flags(struct udevice *dev, const char *name,
void __iomem *reg, u8 shift, u8 width,
const char * const *parents,
int num_parents, unsigned long flags)
{
- return clk_register_mux(NULL, name, parents, num_parents,
+ return clk_register_mux(dev, name, parents, num_parents,
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
reg, shift, width, 0);
}
-static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
- u8 shift, u8 width, const char * const *parents,
+static inline struct clk *imx_clk_mux(struct udevice *dev, const char *name,
+ void __iomem *reg, u8 shift, u8 width, const char * const *parents,
int num_parents)
{
- return clk_register_mux(NULL, name, parents, num_parents,
+ return clk_register_mux(dev, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
width, 0);
}
static inline struct clk *
-imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width,
+imx_clk_busy_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width,
void __iomem *busy_reg, u8 busy_shift,
const char * const *parents, int num_parents)
{
- return clk_register_mux(NULL, name, parents, num_parents,
+ return clk_register_mux(dev, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT, reg, shift,
width, 0);
}
-static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
{
- return clk_register_mux(NULL, name, parents, num_parents,
+ return clk_register_mux(dev, name, parents, num_parents,
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
reg, shift, width, 0);
}
-static inline struct clk *imx_clk_gate(const char *name, const char *parent,
- void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg,
+ u8 shift)
{
- return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+ return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
shift, 0, NULL);
}
-static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
- void __iomem *reg, u8 shift, unsigned long flags)
+static inline struct clk *imx_clk_gate_flags(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg,
+ u8 shift, unsigned long flags)
{
- return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
+ return clk_register_gate(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg,
shift, 0, NULL);
}
-static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
- void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name,
+ const char *parent, void __iomem *reg,
+ u8 shift)
{
- return clk_register_gate(NULL, name, parent,
+ return clk_register_gate(dev, name, parent,
CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
reg, shift, 0, NULL);
}
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg, unsigned long flags);
-#define __imx8m_clk_composite(name, parent_names, reg, flags) \
- imx8m_clk_composite_flags(name, parent_names, \
+#define __imx8m_clk_composite(dev, name, parent_names, reg, flags) \
+ imx8m_clk_composite_flags(dev, name, parent_names, \
ARRAY_SIZE(parent_names), reg, \
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
-#define imx8m_clk_composite(name, parent_names, reg) \
- __imx8m_clk_composite(name, parent_names, reg, 0)
+#define imx8m_clk_composite(dev, name, parent_names, reg) \
+ __imx8m_clk_composite(dev, name, parent_names, reg, 0)
-#define imx8m_clk_composite_critical(name, parent_names, reg) \
- __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+#define imx8m_clk_composite_critical(dev, name, parent_names, reg) \
+ __imx8m_clk_composite(dev, name, parent_names, reg, CLK_IS_CRITICAL)
struct clk *imx93_clk_composite_flags(const char *name,
const char * const *parent_names,
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cb867ac..3ea01f3 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -31,6 +31,14 @@
on the Snapdragon IPQ4019 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_IPQ9574
+ bool "Qualcomm IPQ9574 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon IPQ9574 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
config CLK_QCOM_QCM2290
bool "Qualcomm QCM2290 GCC"
select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1bc0f15..e13fc8c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
+obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index b5def55..6a53f90 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -54,8 +54,9 @@
};
static const struct gate_clk apq8016_clks[] = {
- GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, 0x00000001),
- GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, 0x00000001),
+ GATE_CLK(GCC_PRNG_AHB_CLK, 0x45004, BIT(8)),
+ GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0)),
+ GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0)),
};
/* SDHCI */
@@ -139,15 +140,14 @@
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
- if (priv->data->num_clks < clk->id) {
+ if (priv->data->num_clks < clk->id || !apq8016_clks[clk->id].reg) {
log_warning("%s: unknown clk id %lu\n", __func__, clk->id);
return 0;
}
- debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
- qcom_gate_clk_en(priv, clk->id);
+ debug("%s: enabling clock %s\n", __func__, apq8016_clks[clk->id].name);
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static struct msm_clk_data apq8016_clk_data = {
diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
new file mode 100644
index 0000000..b0af403
--- /dev/null
+++ b/drivers/clk/qcom/clock-ipq9574.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm ipq9574
+ *
+ * (C) Copyright 2025 Linaro Ltd.
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+#include "clock-qcom.h"
+
+#define GCC_BLSP1_AHB_CBCR 0x1004
+#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x402C
+#define GCC_BLSP1_UART3_APPS_CBCR 0x4054
+
+#define GCC_SDCC1_APPS_CBCR 0x3302C
+#define GCC_SDCC1_AHB_CBCR 0x33034
+#define GCC_SDCC1_APPS_CMD_RCGR 0x33004
+#define GCC_SDCC1_ICE_CORE_CBCR 0x33030
+
+static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case GCC_BLSP1_UART3_APPS_CLK:
+ clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
+ 0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
+ return rate;
+ case GCC_SDCC1_APPS_CLK:
+ clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
+ 11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
+ return rate;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct gate_clk ipq9574_clks[] = {
+ GATE_CLK(GCC_BLSP1_UART3_APPS_CLK, 0x4054, 0x00000001),
+ GATE_CLK(GCC_BLSP1_AHB_CLK, 0x1004, 0x00000001),
+ GATE_CLK(GCC_SDCC1_AHB_CLK, 0x33034, 0x00000001),
+ GATE_CLK(GCC_SDCC1_APPS_CLK, 0x3302C, 0x00000001),
+ GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x33030, 0x00000001),
+};
+
+static int ipq9574_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ debug("%s: clk %s\n", __func__, ipq9574_clks[clk->id].name);
+
+ if (!ipq9574_clks[clk->id].reg)
+ return -EINVAL;
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static const struct qcom_reset_map ipq9574_gcc_resets[] = {
+ [GCC_SDCC_BCR] = { 0x33000 },
+};
+
+static struct msm_clk_data ipq9574_gcc_data = {
+ .resets = ipq9574_gcc_resets,
+ .num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
+ .enable = ipq9574_enable,
+ .set_rate = ipq9574_set_rate,
+};
+
+static const struct udevice_id gcc_ipq9574_of_match[] = {
+ {
+ .compatible = "qcom,ipq9574-gcc",
+ .data = (ulong)&ipq9574_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_ipq9574) = {
+ .name = "gcc_ipq9574",
+ .id = UCLASS_NOP,
+ .of_match = gcc_ipq9574_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
index c78705c..1326b77 100644
--- a/drivers/clk/qcom/clock-qcm2290.c
+++ b/drivers/clk/qcom/clock-qcm2290.c
@@ -134,9 +134,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map qcm2290_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index ff336de..f43edea 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -7,10 +7,12 @@
#include <asm/io.h>
#include <linux/bitfield.h>
+#include <errno.h>
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
+#define CFG_CLK_SRC_GPLL2 (2 << 8)
#define CFG_CLK_SRC_GPLL9 (2 << 8)
#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
#define CFG_CLK_SRC_GPLL6 (4 << 8)
@@ -105,14 +107,19 @@
int source);
void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
-static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
u32 val;
- if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
- return;
+ if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
+ log_err("gcc@%#08llx: unknown clock ID %lu!\n",
+ priv->base, id);
+ return -ENOENT;
+ }
val = readl(priv->base + priv->data->clks[id].reg);
writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+
+ return 0;
}
#endif
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index e31f24e..527cecf 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -73,9 +73,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sa8775p_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 5d343f1..8691f08 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -16,29 +16,64 @@
#include "clock-qcom.h"
-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
+#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
+#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
+#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
+#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
+ F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
+ F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
+ F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+ { }
+};
static ulong sc7280_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
if (clk->id < priv->data->num_clks)
debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
switch (clk->id) {
- case GCC_USB30_PRIM_MOCK_UTMI_CLK:
- WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
- clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
- return rate;
case GCC_USB30_PRIM_MASTER_CLK:
- WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
- 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
- clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
- return rate;
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+ return 19200000;
+ case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
+ clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+ return 19200000;
+ case GCC_USB30_SEC_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_SEC_MOCK_UTMI_CLK:
+ clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+ return 19200000;
+ case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
+ clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+ return 19200000;
+ case GCC_PCIE1_PHY_RCHNG_CLK:
+ clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
+ return 100000000;
default:
- return 0;
+ return rate;
}
}
@@ -50,13 +85,35 @@
GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
+ GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
+ GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
+ GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
+ GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
+ GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
+ GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
+ GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
+ GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
+ GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
+ GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
+ GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
+ GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
+ GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
+ GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
+ GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
+ GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
+ GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
+ GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
+ GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
};
static int sc7280_enable(struct clk *clk)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
- if (priv->data->num_clks < clk->id) {
+ if (priv->data->num_clks <= clk->id) {
debug("%s: unknown clk id %lu\n", __func__, clk->id);
return 0;
}
@@ -71,11 +128,32 @@
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
break;
+ case GCC_AGGRE_USB3_SEC_AXI_CLK:
+ qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
+ fallthrough;
+ case GCC_USB30_SEC_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+ break;
+ case GCC_PCIE_1_PIPE_CLK:
+ clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
+ break;
+ case GCC_PCIE_1_AUX_CLK:
+ clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
+ CFG_CLK_SRC_CXO, 16);
+ break;
+ case GCC_QUPV3_WRAP0_S0_CLK:
+ clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+ break;
+ case GCC_QUPV3_WRAP0_S1_CLK:
+ clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+ break;
+ case GCC_QUPV3_WRAP0_S3_CLK:
+ clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+ break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sc7280_gcc_resets[] = {
@@ -100,8 +178,22 @@
static const struct qcom_power_map sc7280_gdscs[] = {
[GCC_UFS_PHY_GDSC] = { 0x77004 },
[GCC_USB30_PRIM_GDSC] = { 0xf004 },
+ [GCC_USB30_SEC_GDSC] = { 0x9e004 },
+ [GCC_PCIE_1_GDSC] = { 0x8d004 },
+};
+
+static const phys_addr_t sc7280_rcg_addrs[] = {
+ 0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
+ 0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
+ 0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR
};
+static const char *const sc7280_rcg_names[] = {
+ "USB30_PRIM_MASTER_CLK_SRC",
+ "USB30_PRIM_MOCK_UTMI_CLK_SRC",
+ "GCC_PCIE_1_AUX_CLK_SRC",
+};
+
static struct msm_clk_data qcs404_gcc_data = {
.resets = sc7280_gcc_resets,
.num_resets = ARRAY_SIZE(sc7280_gcc_resets),
@@ -113,6 +205,10 @@
.enable = sc7280_enable,
.set_rate = sc7280_set_rate,
+
+ .dbg_rcg_addrs = sc7280_rcg_addrs,
+ .num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs),
+ .dbg_rcg_names = sc7280_rcg_names,
};
static const struct udevice_id gcc_sc7280_of_match[] = {
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index adffb0c..6a0bf16 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -162,9 +162,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sdm845_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c
index 9057dfe..17c2e56 100644
--- a/drivers/clk/qcom/clock-sm6115.c
+++ b/drivers/clk/qcom/clock-sm6115.c
@@ -146,9 +146,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sm6115_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
index 88f2e67..7dd0d56 100644
--- a/drivers/clk/qcom/clock-sm8150.c
+++ b/drivers/clk/qcom/clock-sm8150.c
@@ -243,9 +243,7 @@
break;
};
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sm8150_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
index e322a92..2639684 100644
--- a/drivers/clk/qcom/clock-sm8250.c
+++ b/drivers/clk/qcom/clock-sm8250.c
@@ -195,9 +195,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sm8250_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
index 62b5a40..7c06489 100644
--- a/drivers/clk/qcom/clock-sm8550.c
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -220,9 +220,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sm8550_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
index 9baaecb..3644546 100644
--- a/drivers/clk/qcom/clock-sm8650.c
+++ b/drivers/clk/qcom/clock-sm8650.c
@@ -217,9 +217,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map sm8650_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c
index bd9c6ed..542d624 100644
--- a/drivers/clk/qcom/clock-x1e80100.c
+++ b/drivers/clk/qcom/clock-x1e80100.c
@@ -174,9 +174,7 @@
break;
}
- qcom_gate_clk_en(priv, clk->id);
-
- return 0;
+ return qcom_gate_clk_en(priv, clk->id);
}
static const struct qcom_reset_map x1e80100_gcc_resets[] = {
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 8bdc094..f44db76 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -122,4 +122,11 @@
This enables common clock driver support for platforms based
on Allwinner A64 SoC.
+config CLK_SUN50I_A100
+ bool "Clock driver for Allwinner A100/A133"
+ default MACH_SUN50I_A133
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner A100/A133 SoCs.
+
endif # CLK_SUNXI
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 90a2774..7ff71c7 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -24,3 +24,4 @@
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
+obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o
diff --git a/drivers/clk/sunxi/clk_a100.c b/drivers/clk/sunxi/clk_a100.c
new file mode 100644
index 0000000..b641feb
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a100.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2024 Arm Ltd.
+ */
+
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-a100-ccu.h>
+#include <dt-bindings/reset/sun50i-a100-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a100_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
+
+ [CLK_APB1] = GATE_DUMMY,
+
+ [CLK_DE] = GATE(0x600, BIT(31)),
+ [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
+
+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
+ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
+
+ [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
+ [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
+ [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
+ [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
+
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+
+ [CLK_SPI0] = GATE(0x940, BIT(31)),
+ [CLK_SPI1] = GATE(0x944, BIT(31)),
+ [CLK_SPI2] = GATE(0x948, BIT(31)),
+
+ [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
+ [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
+ [CLK_BUS_SPI2] = GATE(0x96c, BIT(2)),
+
+ [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
+
+ [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
+ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
+
+ [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
+ [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
+
+ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
+ [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
+ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
+ [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
+ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
+
+ [CLK_TCON_LCD] = GATE(0xb60, BIT(31)),
+ [CLK_BUS_TCON_LCD] = GATE(0xb7c, BIT(0)),
+};
+
+static struct ccu_reset a100_resets[] = {
+ [RST_BUS_DE] = RESET(0x60c, BIT(16)),
+
+ [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
+ [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
+ [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
+
+ [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
+
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+
+ [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
+ [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
+ [RST_BUS_SPI2] = RESET(0x96c, BIT(18)),
+
+ [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
+
+ [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
+
+ [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
+
+ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
+ [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
+ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
+ [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
+ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
+
+ [RST_BUS_TCON_LCD] = RESET(0xb7c, BIT(16)),
+};
+
+const struct ccu_desc a100_ccu_desc = {
+ .gates = a100_gates,
+ .resets = a100_resets,
+ .num_gates = ARRAY_SIZE(a100_gates),
+ .num_resets = ARRAY_SIZE(a100_resets),
+};
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 2ef4f45..e0765cb 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -122,6 +122,7 @@
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
extern const struct ccu_desc h616_ccu_desc;
+extern const struct ccu_desc a100_ccu_desc;
extern const struct ccu_desc h6_r_ccu_desc;
extern const struct ccu_desc r40_ccu_desc;
extern const struct ccu_desc v3s_ccu_desc;
@@ -215,6 +216,10 @@
{ .compatible = "allwinner,sun50i-h616-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
#endif
+#ifdef CONFIG_CLK_SUN50I_A100
+ { .compatible = "allwinner,sun50i-a100-ccu",
+ .data = (ulong)&a100_ccu_desc },
+#endif
#ifdef CONFIG_CLK_SUNIV_F1C100S
{ .compatible = "allwinner,suniv-f1c100s-ccu",
.data = (ulong)&f1c100s_ccu_desc },
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 53d31b3..4e1ecca 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -35,11 +35,49 @@
{
switch (imxtype) {
case MXC_CPU_IMX8MM:
- return "8MM";
+ return "8MMQ"; /* Quad-core version of the imx8mm */
+ case MXC_CPU_IMX8MML:
+ return "8MMQL"; /* Quad-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMD:
+ return "8MMD"; /* Dual-core version of the imx8mm */
+ case MXC_CPU_IMX8MMDL:
+ return "8MMDL"; /* Dual-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMS:
+ return "8MMS"; /* Single-core version of the imx8mm */
+ case MXC_CPU_IMX8MMSL:
+ return "8MMSL"; /* Single-core Lite version of the imx8mm */
case MXC_CPU_IMX8MN:
- return "8MN";
+ return "8MNano Quad"; /* Quad-core version */
+ case MXC_CPU_IMX8MND:
+ return "8MNano Dual"; /* Dual-core version */
+ case MXC_CPU_IMX8MNS:
+ return "8MNano Solo"; /* Single-core version */
+ case MXC_CPU_IMX8MNL:
+ return "8MNano QuadLite"; /* Quad-core Lite version */
+ case MXC_CPU_IMX8MNDL:
+ return "8MNano DualLite"; /* Dual-core Lite version */
+ case MXC_CPU_IMX8MNSL:
+ return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
+ case MXC_CPU_IMX8MNUQ:
+ return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
+ case MXC_CPU_IMX8MNUD:
+ return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
+ case MXC_CPU_IMX8MNUS:
+ return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
case MXC_CPU_IMX8MP:
- return "8MP";
+ return "8MP[8]"; /* Quad-core version of the imx8mp */
+ case MXC_CPU_IMX8MPD:
+ return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
+ case MXC_CPU_IMX8MPL:
+ return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
+ case MXC_CPU_IMX8MP6:
+ return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
+ case MXC_CPU_IMX8MQ:
+ return "8MQ"; /* Quad-core version of the imx8mq */
+ case MXC_CPU_IMX8MQL:
+ return "8MQLite"; /* Quad-core Lite version of the imx8mq */
+ case MXC_CPU_IMX8MD:
+ return "8MD"; /* Dual-core version of the imx8mq */
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "8QXP";
@@ -177,19 +215,19 @@
ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
- if (IS_ENABLED(CONFIG_IMX9)) {
+ if (IS_ENABLED(CONFIG_IMX_TMU)) {
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
- grade = "Automotive temperature grade ";
+ grade = "Automotive temperature grade";
break;
case TEMP_INDUSTRIAL:
- grade = "Industrial temperature grade ";
+ grade = "Industrial temperature grade";
break;
case TEMP_EXTCOMMERCIAL:
- grade = "Extended Consumer temperature grade ";
+ grade = "Extended Consumer temperature grade";
break;
default:
- grade = "Consumer temperature grade ";
+ grade = "Consumer temperature grade";
break;
}
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 67d5ac1..4d9f004 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -21,6 +21,13 @@
such as the System Management Controller (SMC) and NVMe and this
driver is required to get that functionality up and running.
+config IMX_MU_MBOX
+ bool "Enable i.MX MU MBOX support"
+ depends on DM_MAILBOX
+ help
+ Enable support for i.MX Messaging Unit for communication with other
+ processors on the SoC using mailbox interface
+
config SANDBOX_MBOX
bool "Enable the sandbox mailbox test driver"
depends on DM_MAILBOX && SANDBOX
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 6072fa1..574add6 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
+obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
new file mode 100644
index 0000000..b1e0465
--- /dev/null
+++ b/drivers/mailbox/imx-mailbox.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <mailbox-uclass.h>
+#include <linux/bitfield.h>
+#include <linux/bug.h>
+#include <linux/iopoll.h>
+#include <linux/compat.h>
+
+/* This driver only exposes the status bits to keep with the
+ * polling methodology of u-boot.
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX_MU_CHANS 24
+
+#define IMX_MU_V2_PAR_OFF 0x4
+#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
+
+enum imx_mu_chan_type {
+ IMX_MU_TYPE_TX = 0, /* Tx */
+ IMX_MU_TYPE_RX = 1, /* Rx */
+ IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
+ IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
+ IMX_MU_TYPE_RST = 4, /* Reset */
+ IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
+};
+
+enum imx_mu_xcr {
+ IMX_MU_CR,
+ IMX_MU_GIER,
+ IMX_MU_GCR,
+ IMX_MU_TCR,
+ IMX_MU_RCR,
+ IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+ IMX_MU_SR,
+ IMX_MU_GSR,
+ IMX_MU_TSR,
+ IMX_MU_RSR,
+ IMX_MU_xSR_MAX,
+};
+
+struct imx_mu_con_priv {
+ unsigned int idx;
+ enum imx_mu_chan_type type;
+ struct mbox_chan *chan;
+};
+
+enum imx_mu_type {
+ IMX_MU_V1,
+ IMX_MU_V2 = BIT(1),
+ IMX_MU_V2_S4 = BIT(15),
+ IMX_MU_V2_IRQ = BIT(16),
+};
+
+struct imx_mu {
+ void __iomem *base;
+ const struct imx_mu_dcfg *dcfg;
+ u32 num_tr;
+ u32 num_rr;
+ /* use pointers to channel as a way to reserve channels */
+ struct mbox_chan *channels[IMX_MU_CHANS];
+ struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
+};
+
+struct imx_mu_dcfg {
+ int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void *data);
+ int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+ int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+ int (*init)(struct imx_mu *plat);
+ int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args *args);
+ enum imx_mu_type type;
+ u32 xTR; /* Transmit Register0 */
+ u32 xRR; /* Receive Register0 */
+ u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
+ u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
+};
+
+#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+
+/* General Purpose Interrupt Enable */
+#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+/* Receive Interrupt Enable */
+#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+/* Transmit Interrupt Enable */
+#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+/* General Purpose Interrupt Request */
+#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
+/* MU reset */
+#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5))
+#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7))
+
+static void imx_mu_write(struct imx_mu *plat, u32 val, u32 offs)
+{
+ iowrite32(val, plat->base + offs);
+}
+
+static u32 imx_mu_read(struct imx_mu *plat, u32 offs)
+{
+ return ioread32(plat->base + offs);
+}
+
+static u32 imx_mu_xcr_rmw(struct imx_mu *plat, enum imx_mu_xcr type, u32 set, u32 clr)
+{
+ u32 val;
+
+ val = imx_mu_read(plat, plat->dcfg->xCR[type]);
+ val &= ~clr;
+ val |= set;
+ imx_mu_write(plat, val, plat->dcfg->xCR[type]);
+
+ return val;
+}
+
+/* check that the channel is open or owned by caller */
+static int imx_mu_check_channel(struct mbox_chan *chan)
+{
+ struct imx_mu *plat = dev_get_plat(chan->dev);
+
+ if (plat->channels[chan->id]) {
+ /* if reserved check that caller owns */
+ if (plat->channels[chan->id] == chan)
+ return 1; /* caller owns the channel */
+
+ return -EACCES;
+ }
+
+ return 0; /* channel empty */
+}
+
+static int imx_mu_chan_request(struct mbox_chan *chan)
+{
+ struct imx_mu *plat = dev_get_plat(chan->dev);
+ struct imx_mu_con_priv *cp;
+ enum imx_mu_chan_type type;
+ int idx;
+
+ type = chan->id / 4;
+ idx = chan->id % 4;
+
+ if (imx_mu_check_channel(chan) < 0) /* check if channel already in use */
+ return -EPERM;
+
+ plat->channels[chan->id] = chan;
+ chan->con_priv = kcalloc(1, sizeof(struct imx_mu_con_priv), 0);
+ if (!chan->con_priv)
+ return -ENOMEM;
+ cp = chan->con_priv;
+ cp->idx = idx;
+ cp->type = type;
+ cp->chan = chan;
+
+ switch (type) {
+ case IMX_MU_TYPE_RX:
+ imx_mu_xcr_rmw(plat, IMX_MU_RCR, IMX_MU_xCR_RIEn(plat->dcfg->type, idx), 0);
+ break;
+ case IMX_MU_TYPE_TXDB_V2:
+ case IMX_MU_TYPE_TXDB:
+ case IMX_MU_TYPE_RXDB:
+ imx_mu_xcr_rmw(plat, IMX_MU_GIER, IMX_MU_xCR_GIEn(plat->dcfg->type, idx), 0);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int imx_mu_chan_free(struct mbox_chan *chan)
+{
+ struct imx_mu *plat = dev_get_plat(chan->dev);
+ struct imx_mu_con_priv *cp = chan->con_priv;
+
+ if (imx_mu_check_channel(chan) <= 0) /* check that the channel is also not empty */
+ return -EINVAL;
+
+ /* if you own channel and channel is NOT empty */
+ plat->channels[chan->id] = NULL;
+ switch (cp->type) {
+ case IMX_MU_TYPE_TX:
+ imx_mu_xcr_rmw(plat, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(plat->dcfg->type, cp->idx));
+ break;
+ case IMX_MU_TYPE_RX:
+ imx_mu_xcr_rmw(plat, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(plat->dcfg->type, cp->idx));
+ break;
+ case IMX_MU_TYPE_TXDB_V2:
+ case IMX_MU_TYPE_TXDB:
+ case IMX_MU_TYPE_RXDB:
+ imx_mu_xcr_rmw(plat, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx));
+ break;
+ default:
+ break;
+ }
+
+ kfree(cp);
+
+ return 0;
+}
+
+static int imx_mu_send(struct mbox_chan *chan, const void *data)
+{
+ struct imx_mu *plat = dev_get_plat(chan->dev);
+ struct imx_mu_con_priv *cp = chan->con_priv;
+
+ if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */
+ return -EPERM;
+
+ return plat->dcfg->tx(plat, cp, data);
+}
+
+static int imx_mu_recv(struct mbox_chan *chan, void *data)
+{
+ struct imx_mu *plat = dev_get_plat(chan->dev);
+ struct imx_mu_con_priv *cp = chan->con_priv;
+ u32 ctrl, val;
+
+ if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */
+ return -EPERM;
+
+ switch (cp->type) {
+ case IMX_MU_TYPE_TXDB_V2:
+ case IMX_MU_TYPE_RXDB:
+ /* check if GSR[GIRn] bit is set */
+ if (readx_poll_timeout(ioread32, plat->base + plat->dcfg->xSR[IMX_MU_GSR],
+ val, val & BIT(cp->idx), 1000000) < 0)
+ return -EBUSY;
+
+ ctrl = imx_mu_read(plat, plat->dcfg->xCR[IMX_MU_GIER]);
+ val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]);
+ val &= IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx) &
+ (ctrl & IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx));
+ break;
+ default:
+ dev_warn(chan->dev, "Unhandled channel type %d\n", cp->type);
+ return -EOPNOTSUPP;
+ };
+
+ if (val == IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx))
+ plat->dcfg->rxdb(plat, cp);
+
+ return 0;
+}
+
+static int imx_mu_of_to_plat(struct udevice *dev)
+{
+ struct imx_mu *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ plat->base = (struct mu_type *)addr;
+
+ return 0;
+}
+
+static int imx_mu_init_generic(struct imx_mu *plat)
+{
+ unsigned int i;
+ unsigned int val;
+
+ if (plat->num_rr > 4 || plat->num_tr > 4) {
+ WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
+ /* Set default MU configuration */
+ for (i = 0; i < IMX_MU_xCR_MAX; i++)
+ imx_mu_write(plat, 0, plat->dcfg->xCR[i]);
+
+ /* Clear any pending GIP */
+ val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]);
+ imx_mu_write(plat, val, plat->dcfg->xSR[IMX_MU_GSR]);
+
+ /* Clear any pending RSR */
+ for (i = 0; i < plat->num_rr; i++)
+ imx_mu_read(plat, plat->dcfg->xRR + i * 4);
+
+ return 0;
+}
+
+static int imx_mu_generic_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args)
+{
+ enum imx_mu_chan_type type;
+ int idx, cid;
+
+ if (args->args_count != 2) {
+ dev_err(chan->dev, "Invalid argument count %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ type = args->args[0]; /* channel type */
+ idx = args->args[1]; /* index */
+
+ cid = type * 4 + idx;
+ if (cid >= IMX_MU_CHANS) {
+ dev_err(chan->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n",
+ cid, type, idx);
+ return -EINVAL;
+ }
+
+ chan->id = cid;
+
+ return 0;
+}
+
+static int imx_mu_generic_tx(struct imx_mu *plat, struct imx_mu_con_priv *cp,
+ const void *data)
+{
+ switch (cp->type) {
+ case IMX_MU_TYPE_TXDB_V2:
+ imx_mu_xcr_rmw(plat, IMX_MU_GCR, IMX_MU_xCR_GIRn(plat->dcfg->type, cp->idx), 0);
+ break;
+ default:
+ dev_warn(cp->chan->dev, "Send data on wrong channel type: %d\n", cp->type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int imx_mu_generic_rxdb(struct imx_mu *plat, struct imx_mu_con_priv *cp)
+{
+ imx_mu_write(plat, IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx),
+ plat->dcfg->xSR[IMX_MU_GSR]);
+
+ return 0;
+}
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
+ .tx = imx_mu_generic_tx,
+ .rxdb = imx_mu_generic_rxdb,
+ .init = imx_mu_init_generic,
+ .of_xlate = imx_mu_generic_of_xlate,
+ .type = IMX_MU_V1,
+ .xTR = 0x0,
+ .xRR = 0x10,
+ .xSR = {0x20, 0x20, 0x20, 0x20},
+ .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
+ .tx = imx_mu_generic_tx,
+ .rxdb = imx_mu_generic_rxdb,
+ .init = imx_mu_init_generic,
+ .of_xlate = imx_mu_generic_of_xlate,
+ .type = IMX_MU_V1,
+ .xTR = 0x20,
+ .xRR = 0x40,
+ .xSR = {0x60, 0x60, 0x60, 0x60},
+ .xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx95 = {
+ .tx = imx_mu_generic_tx,
+ .rxdb = imx_mu_generic_rxdb,
+ .init = imx_mu_init_generic,
+ .of_xlate = imx_mu_generic_of_xlate,
+ .type = IMX_MU_V2,
+ .xTR = 0x200,
+ .xRR = 0x280,
+ .xSR = {0xC, 0x118, 0x124, 0x12C},
+ .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
+};
+
+static const struct udevice_id ids[] = {
+ { .compatible = "fsl,imx6sx-mu", .data = (ulong)&imx_mu_cfg_imx6sx },
+ { .compatible = "fsl,imx7ulp-mu", .data = (ulong)&imx_mu_cfg_imx7ulp },
+ { .compatible = "fsl,imx95-mu", .data = (ulong)&imx_mu_cfg_imx95 },
+ { }
+};
+
+int imx_mu_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args)
+{
+ struct imx_mu *plat = dev_get_plat(chan->dev);
+
+ return plat->dcfg->of_xlate(chan, args);
+}
+
+struct mbox_ops imx_mu_ops = {
+ .of_xlate = imx_mu_of_xlate,
+ .request = imx_mu_chan_request,
+ .rfree = imx_mu_chan_free,
+ .send = imx_mu_send,
+ .recv = imx_mu_recv,
+};
+
+static void imx_mu_get_tr_rr(struct imx_mu *plat)
+{
+ u32 val;
+
+ if (plat->dcfg->type & IMX_MU_V2) {
+ val = imx_mu_read(plat, IMX_MU_V2_PAR_OFF);
+ plat->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
+ plat->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
+ } else {
+ plat->num_tr = 4;
+ plat->num_rr = 4;
+ }
+}
+
+static int imx_mu_probe(struct udevice *dev)
+{
+ struct imx_mu *plat = dev_get_plat(dev);
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ plat->dcfg = (void *)dev_get_driver_data(dev);
+
+ imx_mu_get_tr_rr(plat);
+
+ ret = plat->dcfg->init(plat);
+ if (ret) {
+ dev_err(dev, "Failed to init MU\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(imx_mu) = {
+ .name = "imx-mu",
+ .id = UCLASS_MAILBOX,
+ .of_match = ids,
+ .of_to_plat = imx_mu_of_to_plat,
+ .plat_auto = sizeof(struct imx_mu),
+ .probe = imx_mu_probe,
+ .ops = &imx_mu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 713d93a..851aa73 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -270,5 +270,4 @@
.id = UCLASS_NOP,
.of_match = zynqmp_ipi_ids,
.probe = zynqmp_ipi_probe,
- .flags = DM_FLAG_PROBE_AFTER_BIND,
};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ab56bd3..6740591 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -928,6 +928,12 @@
bool "QIXIS-based eSDHC quirk detection"
depends on FSL_ESDHC && FSL_QIXIS
+config ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+ bool
+ depends on FSL_ESDHC || FSL_ESDHC_IMX
+ def_bool y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_T2080 \
+ || FSL_ESDHC_IMX
+
config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index d7a45ef0..926113f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -40,12 +40,6 @@
#include <linux/iopoll.h>
#include <linux/dma-mapping.h>
-#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
-#ifdef CONFIG_FSL_USDHC
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
-#endif
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
@@ -376,7 +370,7 @@
(timeout == 4 || timeout == 8 || timeout == 12))
timeout++;
- if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
+ if (IS_ENABLED(CONFIG_ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
timeout = 0xE;
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 27bb705..ac77fb0 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -10,6 +10,7 @@
#include <clk.h>
#include <dm.h>
#include <malloc.h>
+#include <reset.h>
#include <sdhci.h>
#include <wait_bit.h>
#include <asm/global_data.h>
@@ -153,9 +154,18 @@
const struct msm_sdhc_variant_info *var_info;
struct sdhci_host *host = &prv->host;
u32 core_version, core_minor, core_major;
+ struct reset_ctl bcr_rst;
u32 caps;
int ret;
+ ret = reset_get_by_index(dev, 0, &bcr_rst);
+ if (!ret) {
+ reset_assert(&bcr_rst);
+ udelay(200);
+ reset_deassert(&bcr_rst);
+ udelay(200);
+ }
+
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
host->max_clk = 0;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0b56d14..951e6ac 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -92,6 +92,13 @@
pll = CCM_MMC_CTRL_PLL6;
pll_hz = clock_get_pll6();
#endif
+ /*
+ * On the D1/R528/T113 mux source 1 refers to PLL_PERIPH0(1x),
+ * like for the older SoCs. However we still have the hidden
+ * divider of 2x, so compensate for that here.
+ */
+ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+ pll_hz /= 2;
}
div = pll_hz / hz;
@@ -442,6 +449,26 @@
return error;
}
+static void sunxi_mmc_reset(void *regs)
+{
+ /* Reset controller */
+ writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL);
+ udelay(1000);
+
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+ /* Reset card */
+ writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST);
+ udelay(10);
+ writel(SUNXI_MMC_HWRST_DEASSERT, regs + SUNXI_MMC_HWRST);
+ udelay(300);
+
+ /* Setup FIFO R/W threshold. Needed on H616. */
+ writel(SUNXI_MMC_THLDC_READ_THLD(512) |
+ SUNXI_MMC_THLDC_WRITE_EN |
+ SUNXI_MMC_THLDC_READ_EN, regs + SUNXI_MMC_THLDC);
+ }
+}
+
/* non-DM code here is used by the (ARM) SPL only */
#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -489,9 +516,7 @@
{
struct sunxi_mmc_priv *priv = mmc->priv;
- /* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
- udelay(1000);
+ sunxi_mmc_reset(priv->reg);
return 0;
}
@@ -684,9 +709,7 @@
upriv->mmc = &plat->mmc;
- /* Reset controller */
- writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
- udelay(1000);
+ sunxi_mmc_reset(priv->reg);
return 0;
}
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
index f4ae5a7..7186516 100644
--- a/drivers/mmc/sunxi_mmc.h
+++ b/drivers/mmc/sunxi_mmc.h
@@ -37,7 +37,9 @@
u32 res0; /* 0x54 reserved */
u32 a12a; /* 0x58 Auto command 12 argument */
u32 ntsr; /* 0x5c New timing set register */
- u32 res1[8];
+ u32 res1[6];
+ u32 hwrst; /* 0x78 Hardware Reset */
+ u32 res5;
u32 dmac; /* 0x80 internal DMA control */
u32 dlba; /* 0x84 internal DMA descr list base address */
u32 idst; /* 0x88 internal DMA status */
@@ -46,7 +48,8 @@
u32 cbda; /* 0x94 */
u32 res2[26];
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
- u32 res3[17];
+ u32 thldc; /* 0x100 Threshold control */
+ u32 res3[16];
u32 samp_dl;
u32 res4[46];
#endif
@@ -57,6 +60,7 @@
#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
+#define SUNXI_MMC_GCTRL 0x000
#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
@@ -123,6 +127,10 @@
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
+#define SUNXI_MMC_HWRST 0x078
+#define SUNXI_MMC_HWRST_ASSERT (0x0 << 0)
+#define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0)
+
#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
@@ -133,6 +141,12 @@
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
#define SUNXI_MMC_COMMON_RESET (1 << 18)
+#define SUNXI_MMC_THLDC 0x100
+#define SUNXI_MMC_THLDC_READ_EN (0x1 << 0)
+#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1)
+#define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2)
+#define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16)
+
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
#endif /* _SUNXI_MMC_H */
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 609bdff..adb271d 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -190,6 +190,21 @@
def_bool y
depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
+config NAND_CADENCE
+ bool "Support Cadence NAND controller as a DT device"
+ depends on OF_CONTROL && DM_MTD
+ select SYS_NAND_SELF_INIT
+ select SPL_SYS_NAND_SELF_INIT
+ select SPL_NAND_BASE
+ select SPL_NAND_DRIVERS
+ select SPL_NAND_IDENT
+ select SPL_NAND_INIT
+ select SPL_NAND_ECC
+ imply CMD_NAND
+ help
+ Enable the driver for NAND flash on platforms using a Cadence NAND
+ controller as a DT device.
+
config NAND_DENALI
bool
select SYS_NAND_SELF_INIT
@@ -673,7 +688,7 @@
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
MVEBU_SPL_BOOT_DEVICE_NAND || \
(NAND_ATMEL && SPL_NAND_SUPPORT) || \
- SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX
+ SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX || NAND_CADENCE
depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
help
Number of data bytes in one page for the NAND chip on the
@@ -775,6 +790,13 @@
so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
SPL-NAND driver with software ECC correction support.
+config SPL_NAND_CADENCE
+ bool "Support Cadence NAND controller for SPL"
+ depends on SPL_NAND_SUPPORT
+ help
+ This is a small implementation of the Cadence NAND controller
+ for use on SPL.
+
config SPL_NAND_DENALI
bool "Support Denali NAND controller for SPL"
depends on SPL_NAND_SUPPORT
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index b47a3d7..34cba77 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -10,6 +10,7 @@
endif
obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_CADENCE) += cadence_spl.o
obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
@@ -51,6 +52,7 @@
obj-$(CONFIG_DM_NAND_ATMEL) += atmel/
obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
+obj-$(CONFIG_NAND_CADENCE) += cadence_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c
new file mode 100644
index 0000000..27aa7f9
--- /dev/null
+++ b/drivers/mtd/nand/raw/cadence_nand.c
@@ -0,0 +1,2423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cadence NAND flash controller driver
+ *
+ * Copyright (C) 2019 Cadence
+ *
+ * Author: Piotr Sroka <piotrs@cadence.com>
+ *
+ */
+
+#include <cadence-nand.h>
+#include <clk.h>
+#include <dm.h>
+#include <hang.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <nand.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitfield.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+static inline struct
+cdns_nand_chip *to_cdns_nand_chip(struct nand_chip *chip)
+{
+ return container_of(chip, struct cdns_nand_chip, chip);
+}
+
+static inline struct
+cadence_nand_info *to_cadence_nand_info(struct nand_hw_control *controller)
+{
+ return container_of(controller, struct cadence_nand_info, controller);
+}
+
+static bool
+cadence_nand_dma_buf_ok(struct cadence_nand_info *cadence, const void *buf,
+ u32 buf_len)
+{
+ u8 data_dma_width = cadence->caps2.data_dma_width;
+
+ return buf &&
+ likely(IS_ALIGNED((uintptr_t)buf, data_dma_width)) &&
+ likely(IS_ALIGNED(buf_len, DMA_DATA_SIZE_ALIGN));
+}
+
+static int cadence_nand_wait_for_value(struct cadence_nand_info *cadence,
+ u32 reg_offset, u32 timeout_us,
+ u32 mask, bool is_clear)
+{
+ u32 val;
+ int ret;
+
+ ret = readl_poll_sleep_timeout(cadence->reg + reg_offset,
+ val, !(val & mask) == is_clear,
+ 10, timeout_us);
+
+ if (ret < 0) {
+ dev_err(cadence->dev,
+ "Timeout while waiting for reg %x with mask %x is clear %d\n",
+ reg_offset, mask, is_clear);
+ }
+
+ return ret;
+}
+
+static int cadence_nand_set_ecc_enable(struct cadence_nand_info *cadence,
+ bool enable)
+{
+ u32 reg;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ reg = readl_relaxed(cadence->reg + ECC_CONFIG_0);
+
+ if (enable)
+ reg |= ECC_CONFIG_0_ECC_EN;
+ else
+ reg &= ~ECC_CONFIG_0_ECC_EN;
+
+ writel_relaxed(reg, cadence->reg + ECC_CONFIG_0);
+
+ return 0;
+}
+
+static void cadence_nand_set_ecc_strength(struct cadence_nand_info *cadence,
+ u8 corr_str_idx)
+{
+ u32 reg;
+
+ if (cadence->curr_corr_str_idx == corr_str_idx)
+ return;
+
+ reg = readl_relaxed(cadence->reg + ECC_CONFIG_0);
+ reg &= ~ECC_CONFIG_0_CORR_STR;
+ reg |= FIELD_PREP(ECC_CONFIG_0_CORR_STR, corr_str_idx);
+ writel_relaxed(reg, cadence->reg + ECC_CONFIG_0);
+
+ cadence->curr_corr_str_idx = corr_str_idx;
+}
+
+static int cadence_nand_get_ecc_strength_idx(struct cadence_nand_info *cadence,
+ u8 strength)
+{
+ int i, corr_str_idx = -1;
+
+ for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
+ if (cadence->ecc_strengths[i] == strength) {
+ corr_str_idx = i;
+ break;
+ }
+ }
+
+ return corr_str_idx;
+}
+
+static int cadence_nand_set_skip_marker_val(struct cadence_nand_info *cadence,
+ u16 marker_value)
+{
+ u32 reg;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ reg = readl_relaxed(cadence->reg + SKIP_BYTES_CONF);
+ reg &= ~SKIP_BYTES_MARKER_VALUE;
+ reg |= FIELD_PREP(SKIP_BYTES_MARKER_VALUE,
+ marker_value);
+
+ writel_relaxed(reg, cadence->reg + SKIP_BYTES_CONF);
+
+ return 0;
+}
+
+static int cadence_nand_set_skip_bytes_conf(struct cadence_nand_info *cadence,
+ u8 num_of_bytes,
+ u32 offset_value,
+ int enable)
+{
+ u32 reg, skip_bytes_offset;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ if (!enable) {
+ num_of_bytes = 0;
+ offset_value = 0;
+ }
+
+ reg = readl_relaxed(cadence->reg + SKIP_BYTES_CONF);
+ reg &= ~SKIP_BYTES_NUM_OF_BYTES;
+ reg |= FIELD_PREP(SKIP_BYTES_NUM_OF_BYTES,
+ num_of_bytes);
+ skip_bytes_offset = FIELD_PREP(SKIP_BYTES_OFFSET_VALUE,
+ offset_value);
+
+ writel_relaxed(reg, cadence->reg + SKIP_BYTES_CONF);
+ writel_relaxed(skip_bytes_offset, cadence->reg + SKIP_BYTES_OFFSET);
+
+ return 0;
+}
+
+/* Functions enables/disables hardware detection of erased data */
+static void cadence_nand_set_erase_detection(struct cadence_nand_info *cadence,
+ bool enable,
+ u8 bitflips_threshold)
+{
+ u32 reg;
+
+ reg = readl_relaxed(cadence->reg + ECC_CONFIG_0);
+
+ if (enable)
+ reg |= ECC_CONFIG_0_ERASE_DET_EN;
+ else
+ reg &= ~ECC_CONFIG_0_ERASE_DET_EN;
+
+ writel_relaxed(reg, cadence->reg + ECC_CONFIG_0);
+ writel_relaxed(bitflips_threshold, cadence->reg + ECC_CONFIG_1);
+}
+
+static int cadence_nand_set_access_width16(struct cadence_nand_info *cadence,
+ bool bit_bus16)
+{
+ u32 reg;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ reg = readl_relaxed(cadence->reg + COMMON_SET);
+ if (!bit_bus16)
+ reg &= ~COMMON_SET_DEVICE_16BIT;
+ else
+ reg |= COMMON_SET_DEVICE_16BIT;
+ writel_relaxed(reg, cadence->reg + COMMON_SET);
+
+ return 0;
+}
+
+static void
+cadence_nand_clear_interrupt(struct cadence_nand_info *cadence,
+ struct cadence_nand_irq_status *irq_status)
+{
+ writel_relaxed(irq_status->status, cadence->reg + INTR_STATUS);
+ writel_relaxed(irq_status->trd_status,
+ cadence->reg + TRD_COMP_INT_STATUS);
+ writel_relaxed(irq_status->trd_error,
+ cadence->reg + TRD_ERR_INT_STATUS);
+}
+
+static void
+cadence_nand_read_int_status(struct cadence_nand_info *cadence,
+ struct cadence_nand_irq_status *irq_status)
+{
+ irq_status->status = readl_relaxed(cadence->reg + INTR_STATUS);
+ irq_status->trd_status = readl_relaxed(cadence->reg
+ + TRD_COMP_INT_STATUS);
+ irq_status->trd_error = readl_relaxed(cadence->reg
+ + TRD_ERR_INT_STATUS);
+}
+
+static u32 irq_detected(struct cadence_nand_info *cadence,
+ struct cadence_nand_irq_status *irq_status)
+{
+ cadence_nand_read_int_status(cadence, irq_status);
+
+ return irq_status->status || irq_status->trd_status ||
+ irq_status->trd_error;
+}
+
+static void cadence_nand_reset_irq(struct cadence_nand_info *cadence)
+{
+ memset(&cadence->irq_status, 0, sizeof(cadence->irq_status));
+ memset(&cadence->irq_mask, 0, sizeof(cadence->irq_mask));
+}
+
+/*
+ * This is the interrupt service routine. It handles all interrupts
+ * sent to this device.
+ */
+static irqreturn_t cadence_nand_isr(struct cadence_nand_info *cadence)
+{
+ struct cadence_nand_irq_status irq_status;
+ irqreturn_t result = IRQ_NONE;
+
+ if (irq_detected(cadence, &irq_status)) {
+ /* Handle interrupt. */
+ /* First acknowledge it. */
+ cadence_nand_clear_interrupt(cadence, &irq_status);
+ /* Status in the device context for someone to read. */
+ cadence->irq_status.status |= irq_status.status;
+ cadence->irq_status.trd_status |= irq_status.trd_status;
+ cadence->irq_status.trd_error |= irq_status.trd_error;
+ /* Tell the OS that we've handled this. */
+ result = IRQ_HANDLED;
+ }
+ return result;
+}
+
+static void cadence_nand_set_irq_mask(struct cadence_nand_info *cadence,
+ struct cadence_nand_irq_status *irq_mask)
+{
+ writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status,
+ cadence->reg + INTR_ENABLE);
+
+ writel_relaxed(irq_mask->trd_error,
+ cadence->reg + TRD_ERR_INT_STATUS_EN);
+}
+
+static void
+cadence_nand_wait_for_irq(struct cadence_nand_info *cadence,
+ struct cadence_nand_irq_status *irq_mask,
+ struct cadence_nand_irq_status *irq_status)
+{
+ irqreturn_t result = IRQ_NONE;
+ u32 start = get_timer(0);
+
+ while (get_timer(start) < TIMEOUT_US) {
+ result = cadence_nand_isr(cadence);
+
+ if (result == IRQ_HANDLED) {
+ *irq_status = cadence->irq_status;
+ break;
+ }
+ udelay(1);
+ }
+
+ if (!result) {
+ /* Timeout error. */
+ dev_err(cadence->dev, "timeout occurred:\n");
+ dev_err(cadence->dev, "\tstatus = 0x%x, mask = 0x%x\n",
+ irq_status->status, irq_mask->status);
+ dev_err(cadence->dev,
+ "\ttrd_status = 0x%x, trd_status mask = 0x%x\n",
+ irq_status->trd_status, irq_mask->trd_status);
+ dev_err(cadence->dev,
+ "\t trd_error = 0x%x, trd_error mask = 0x%x\n",
+ irq_status->trd_error, irq_mask->trd_error);
+ }
+}
+
+/* Execute generic command on NAND controller. */
+static int cadence_nand_generic_cmd_send(struct cadence_nand_info *cadence,
+ u8 chip_nr,
+ u64 mini_ctrl_cmd)
+{
+ u32 mini_ctrl_cmd_l, mini_ctrl_cmd_h, reg;
+
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_CS, chip_nr);
+ mini_ctrl_cmd_l = mini_ctrl_cmd & 0xFFFFFFFF;
+ mini_ctrl_cmd_h = mini_ctrl_cmd >> 32;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ cadence_nand_reset_irq(cadence);
+
+ writel_relaxed(mini_ctrl_cmd_l, cadence->reg + CMD_REG2);
+ writel_relaxed(mini_ctrl_cmd_h, cadence->reg + CMD_REG3);
+
+ /* Select generic command. */
+ reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_GEN);
+ /* Thread number. */
+ reg |= FIELD_PREP(CMD_REG0_TN, 0);
+
+ /* Issue command. */
+ writel_relaxed(reg, cadence->reg + CMD_REG0);
+ cadence->buf_index = 0;
+
+ return 0;
+}
+
+/* Wait for data on slave DMA interface. */
+static int cadence_nand_wait_on_sdma(struct cadence_nand_info *cadence, u8 *out_sdma_trd,
+ u32 *out_sdma_size)
+{
+ struct cadence_nand_irq_status irq_mask, irq_status;
+
+ irq_mask.trd_status = 0;
+ irq_mask.trd_error = 0;
+ irq_mask.status = INTR_STATUS_SDMA_TRIGG
+ | INTR_STATUS_SDMA_ERR
+ | INTR_STATUS_UNSUPP_CMD;
+
+ cadence_nand_set_irq_mask(cadence, &irq_mask);
+ cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status);
+ if (irq_status.status == 0) {
+ dev_err(cadence->dev, "Timeout while waiting for SDMA\n");
+ return -ETIMEDOUT;
+ }
+
+ if (irq_status.status & INTR_STATUS_SDMA_TRIGG) {
+ *out_sdma_size = readl_relaxed(cadence->reg + SDMA_SIZE);
+ *out_sdma_trd = readl_relaxed(cadence->reg + SDMA_TRD_NUM);
+ *out_sdma_trd =
+ FIELD_GET(SDMA_TRD_NUM_SDMA_TRD, *out_sdma_trd);
+ } else {
+ dev_err(cadence->dev, "SDMA error - irq_status %x\n",
+ irq_status.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void cadence_nand_get_caps(struct cadence_nand_info *cadence)
+{
+ u32 reg;
+
+ reg = readl_relaxed(cadence->reg + CTRL_FEATURES);
+
+ cadence->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg);
+
+ if (FIELD_GET(CTRL_FEATURES_DMA_DWITH64, reg))
+ cadence->caps2.data_dma_width = 8;
+ else
+ cadence->caps2.data_dma_width = 4;
+
+ if (reg & CTRL_FEATURES_CONTROL_DATA)
+ cadence->caps2.data_control_supp = true;
+
+ if (reg & (CTRL_FEATURES_NVDDR_2_3
+ | CTRL_FEATURES_NVDDR))
+ cadence->caps2.is_phy_type_dll = true;
+}
+
+/* Prepare CDMA descriptor. */
+static void
+cadence_nand_cdma_desc_prepare(struct cadence_nand_info *cadence,
+ char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,
+ dma_addr_t ctrl_data_ptr, u16 ctype)
+{
+ struct cadence_nand_cdma_desc *cdma_desc = cadence->cdma_desc;
+
+ memset(cdma_desc, 0, sizeof(struct cadence_nand_cdma_desc));
+
+ /* Set fields for one descriptor. */
+ cdma_desc->flash_pointer = flash_ptr;
+ if (cadence->ctrl_rev >= 13)
+ cdma_desc->bank = nf_mem;
+ else
+ cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT);
+
+ cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
+ cdma_desc->command_flags |= CDMA_CF_INT;
+
+ cdma_desc->memory_pointer = mem_ptr;
+ cdma_desc->status = 0;
+ cdma_desc->sync_flag_pointer = 0;
+ cdma_desc->sync_arguments = 0;
+
+ cdma_desc->command_type = ctype;
+ cdma_desc->ctrl_data_ptr = ctrl_data_ptr;
+
+ flush_cache((dma_addr_t)cadence->cdma_desc,
+ ROUND(sizeof(struct cadence_nand_cdma_desc),
+ ARCH_DMA_MINALIGN));
+}
+
+static u8 cadence_nand_check_desc_error(struct cadence_nand_info *cadence,
+ u32 desc_status)
+{
+ if (desc_status & CDMA_CS_ERP)
+ return STAT_ERASED;
+
+ if (desc_status & CDMA_CS_UNCE)
+ return STAT_ECC_UNCORR;
+
+ if (desc_status & CDMA_CS_ERR) {
+ dev_err(cadence->dev, ":CDMA desc error flag detected.\n");
+ return STAT_FAIL;
+ }
+
+ if (FIELD_GET(CDMA_CS_MAXERR, desc_status))
+ return STAT_ECC_CORR;
+
+ return STAT_FAIL;
+}
+
+static int cadence_nand_cdma_finish(struct cadence_nand_info *cadence)
+{
+ struct cadence_nand_cdma_desc *desc_ptr = cadence->cdma_desc;
+ u8 status = STAT_BUSY;
+
+ invalidate_dcache_range((dma_addr_t)cadence->cdma_desc,
+ (dma_addr_t)cadence->cdma_desc +
+ ROUND(sizeof(struct cadence_nand_cdma_desc),
+ ARCH_DMA_MINALIGN));
+
+ if (desc_ptr->status & CDMA_CS_FAIL) {
+ status = cadence_nand_check_desc_error(cadence,
+ desc_ptr->status);
+ dev_err(cadence->dev, ":CDMA error %x\n", desc_ptr->status);
+ } else if (desc_ptr->status & CDMA_CS_COMP) {
+ /* Descriptor finished with no errors. */
+ if (desc_ptr->command_flags & CDMA_CF_CONT) {
+ dev_info(cadence->dev, "DMA unsupported flag is set");
+ status = STAT_UNKNOWN;
+ } else {
+ /* Last descriptor. */
+ status = STAT_OK;
+ }
+ }
+
+ return status;
+}
+
+static int cadence_nand_cdma_send(struct cadence_nand_info *cadence,
+ u8 thread)
+{
+ u32 reg;
+ int status;
+
+ /* Wait for thread ready. */
+ status = cadence_nand_wait_for_value(cadence, TRD_STATUS,
+ TIMEOUT_US,
+ BIT(thread), true);
+ if (status)
+ return status;
+
+ cadence_nand_reset_irq(cadence);
+
+ writel_relaxed((u32)cadence->dma_cdma_desc,
+ cadence->reg + CMD_REG2);
+ writel_relaxed(0, cadence->reg + CMD_REG3);
+
+ /* Select CDMA mode. */
+ reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_CDMA);
+ /* Thread number. */
+ reg |= FIELD_PREP(CMD_REG0_TN, thread);
+ /* Issue command. */
+ writel_relaxed(reg, cadence->reg + CMD_REG0);
+
+ return 0;
+}
+
+/* Send SDMA command and wait for finish. */
+static u32
+cadence_nand_cdma_send_and_wait(struct cadence_nand_info *cadence,
+ u8 thread)
+{
+ struct cadence_nand_irq_status irq_mask, irq_status = {0};
+ int status;
+ u32 val;
+
+ irq_mask.trd_status = BIT(thread);
+ irq_mask.trd_error = BIT(thread);
+ irq_mask.status = INTR_STATUS_CDMA_TERR;
+
+ cadence_nand_set_irq_mask(cadence, &irq_mask);
+
+ status = cadence_nand_cdma_send(cadence, thread);
+ if (status)
+ return status;
+
+ /* Make sure the descriptor processing is complete */
+ status = readl_poll_timeout(cadence->reg + TRD_COMP_INT_STATUS, val,
+ (val & BIT(thread)), TIMEOUT_US);
+ if (status) {
+ pr_err("cmd thread completion timeout!\n");
+ return status;
+ }
+
+ cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status);
+
+ if (irq_status.status == 0 && irq_status.trd_status == 0 &&
+ irq_status.trd_error == 0) {
+ dev_err(cadence->dev, "CDMA command timeout\n");
+ return -ETIMEDOUT;
+ }
+ if (irq_status.status & irq_mask.status) {
+ dev_err(cadence->dev, "CDMA command failed\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/*
+ * ECC size depends on configured ECC strength and on maximum supported
+ * ECC step size.
+ */
+static int cadence_nand_calc_ecc_bytes(int max_step_size, int strength)
+{
+ int nbytes = DIV_ROUND_UP(fls(8 * max_step_size) * strength, 8);
+
+ return ALIGN(nbytes, 2);
+}
+
+#define CADENCE_NAND_CALC_ECC_BYTES(max_step_size) \
+ static int \
+ cadence_nand_calc_ecc_bytes_##max_step_size(int step_size, \
+ int strength)\
+ {\
+ return cadence_nand_calc_ecc_bytes(max_step_size, strength);\
+ }
+
+CADENCE_NAND_CALC_ECC_BYTES(256)
+CADENCE_NAND_CALC_ECC_BYTES(512)
+CADENCE_NAND_CALC_ECC_BYTES(1024)
+CADENCE_NAND_CALC_ECC_BYTES(2048)
+CADENCE_NAND_CALC_ECC_BYTES(4096)
+
+/* Function reads BCH capabilities. */
+static int cadence_nand_read_bch_caps(struct cadence_nand_info *cadence)
+{
+ struct nand_ecc_caps *ecc_caps = &cadence->ecc_caps;
+ int max_step_size = 0, nstrengths, i;
+ u32 reg;
+
+ reg = readl_relaxed(cadence->reg + BCH_CFG_3);
+ cadence->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg);
+ if (cadence->bch_metadata_size < 4) {
+ dev_err(cadence->dev,
+ "Driver needs at least 4 bytes of BCH meta data\n");
+ return -EIO;
+ }
+
+ reg = readl_relaxed(cadence->reg + BCH_CFG_0);
+ cadence->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg);
+ cadence->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg);
+ cadence->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg);
+ cadence->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg);
+
+ reg = readl_relaxed(cadence->reg + BCH_CFG_1);
+ cadence->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg);
+ cadence->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg);
+ cadence->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg);
+ cadence->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg);
+
+ reg = readl_relaxed(cadence->reg + BCH_CFG_2);
+ cadence->ecc_stepinfos[0].stepsize =
+ FIELD_GET(BCH_CFG_2_SECT_0, reg);
+
+ cadence->ecc_stepinfos[1].stepsize =
+ FIELD_GET(BCH_CFG_2_SECT_1, reg);
+
+ nstrengths = 0;
+ for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
+ if (cadence->ecc_strengths[i] != 0)
+ nstrengths++;
+ }
+
+ ecc_caps->nstepinfos = 0;
+ for (i = 0; i < BCH_MAX_NUM_SECTOR_SIZES; i++) {
+ /* ECC strengths are common for all step infos. */
+ cadence->ecc_stepinfos[i].nstrengths = nstrengths;
+ cadence->ecc_stepinfos[i].strengths =
+ cadence->ecc_strengths;
+
+ if (cadence->ecc_stepinfos[i].stepsize != 0)
+ ecc_caps->nstepinfos++;
+
+ if (cadence->ecc_stepinfos[i].stepsize > max_step_size)
+ max_step_size = cadence->ecc_stepinfos[i].stepsize;
+ }
+ ecc_caps->stepinfos = &cadence->ecc_stepinfos[0];
+
+ switch (max_step_size) {
+ case 256:
+ ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256;
+ break;
+ case 512:
+ ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512;
+ break;
+ case 1024:
+ ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024;
+ break;
+ case 2048:
+ ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048;
+ break;
+ case 4096:
+ ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096;
+ break;
+ default:
+ dev_err(cadence->dev,
+ "Unsupported sector size(ecc step size) %d\n",
+ max_step_size);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/* Hardware initialization. */
+static int cadence_nand_hw_init(struct cadence_nand_info *cadence)
+{
+ int status;
+ u32 reg;
+
+ status = cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_INIT_COMP, false);
+ if (status)
+ return status;
+
+ reg = readl_relaxed(cadence->reg + CTRL_VERSION);
+ cadence->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg);
+
+ dev_info(cadence->dev,
+ "%s: cadence nand controller version reg %x\n",
+ __func__, reg);
+
+ /* Disable cache and multiplane. */
+ writel_relaxed(0, cadence->reg + MULTIPLANE_CFG);
+ writel_relaxed(0, cadence->reg + CACHE_CFG);
+
+ /* Clear all interrupts. */
+ writel_relaxed(0xFFFFFFFF, cadence->reg + INTR_STATUS);
+
+ cadence_nand_get_caps(cadence);
+ if (cadence_nand_read_bch_caps(cadence))
+ return -EIO;
+
+ /*
+ * Set IO width access to 8.
+ * It is because during SW device discovering width access
+ * is expected to be 8.
+ */
+ status = cadence_nand_set_access_width16(cadence, false);
+
+ return status;
+}
+
+#define TT_MAIN_OOB_AREAS 2
+#define TT_RAW_PAGE 3
+#define TT_BBM 4
+#define TT_MAIN_OOB_AREA_EXT 5
+
+/* Prepare size of data to transfer. */
+static void
+cadence_nand_prepare_data_size(struct mtd_info *mtd,
+ int transfer_type)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ u32 sec_size = 0, offset = 0, sec_cnt = 1;
+ u32 last_sec_size = cdns_chip->sector_size;
+ u32 data_ctrl_size = 0;
+ u32 reg = 0;
+
+ if (cadence->curr_trans_type == transfer_type)
+ return;
+
+ switch (transfer_type) {
+ case TT_MAIN_OOB_AREA_EXT:
+ sec_cnt = cdns_chip->sector_count;
+ sec_size = cdns_chip->sector_size;
+ data_ctrl_size = cdns_chip->avail_oob_size;
+ break;
+ case TT_MAIN_OOB_AREAS:
+ sec_cnt = cdns_chip->sector_count;
+ last_sec_size = cdns_chip->sector_size
+ + cdns_chip->avail_oob_size;
+ sec_size = cdns_chip->sector_size;
+ break;
+ case TT_RAW_PAGE:
+ last_sec_size = mtd->writesize + mtd->oobsize;
+ break;
+ case TT_BBM:
+ offset = mtd->writesize + cdns_chip->bbm_offs;
+ last_sec_size = 8;
+ break;
+ }
+
+ reg = 0;
+ reg |= FIELD_PREP(TRAN_CFG_0_OFFSET, offset);
+ reg |= FIELD_PREP(TRAN_CFG_0_SEC_CNT, sec_cnt);
+ writel_relaxed(reg, cadence->reg + TRAN_CFG_0);
+
+ reg = 0;
+ reg |= FIELD_PREP(TRAN_CFG_1_LAST_SEC_SIZE, last_sec_size);
+ reg |= FIELD_PREP(TRAN_CFG_1_SECTOR_SIZE, sec_size);
+ writel_relaxed(reg, cadence->reg + TRAN_CFG_1);
+
+ if (cadence->caps2.data_control_supp) {
+ reg = readl_relaxed(cadence->reg + CONTROL_DATA_CTRL);
+ reg &= ~CONTROL_DATA_CTRL_SIZE;
+ reg |= FIELD_PREP(CONTROL_DATA_CTRL_SIZE, data_ctrl_size);
+ writel_relaxed(reg, cadence->reg + CONTROL_DATA_CTRL);
+ }
+
+ cadence->curr_trans_type = transfer_type;
+}
+
+static int
+cadence_nand_cdma_transfer(struct cadence_nand_info *cadence, u8 chip_nr,
+ int page, void *buf, void *ctrl_dat, u32 buf_size,
+ u32 ctrl_dat_size, enum dma_data_direction dir,
+ bool with_ecc)
+{
+ dma_addr_t dma_buf, dma_ctrl_dat = 0;
+ u8 thread_nr = chip_nr;
+ int status;
+ u16 ctype;
+
+ if (dir == DMA_FROM_DEVICE)
+ ctype = CDMA_CT_RD;
+ else
+ ctype = CDMA_CT_WR;
+
+ cadence_nand_set_ecc_enable(cadence, with_ecc);
+
+ dma_buf = dma_map_single(buf, buf_size, dir);
+ if (dma_mapping_error(cadence->dev, dma_buf)) {
+ dev_err(cadence->dev, "Failed to map DMA buffer\n");
+ return -EIO;
+ }
+
+ if (ctrl_dat && ctrl_dat_size) {
+ dma_ctrl_dat = dma_map_single(ctrl_dat,
+ ctrl_dat_size, dir);
+ if (dma_mapping_error(cadence->dev, dma_ctrl_dat)) {
+ dma_unmap_single(dma_buf,
+ buf_size, dir);
+ dev_err(cadence->dev, "Failed to map DMA buffer\n");
+ return -EIO;
+ }
+ }
+
+ cadence_nand_cdma_desc_prepare(cadence, chip_nr, page,
+ dma_buf, dma_ctrl_dat, ctype);
+
+ status = cadence_nand_cdma_send_and_wait(cadence, thread_nr);
+
+ dma_unmap_single(dma_buf,
+ buf_size, dir);
+
+ if (ctrl_dat && ctrl_dat_size)
+ dma_unmap_single(dma_ctrl_dat,
+ ctrl_dat_size, dir);
+ if (status)
+ return status;
+
+ return cadence_nand_cdma_finish(cadence);
+}
+
+static void cadence_nand_set_timings(struct cadence_nand_info *cadence,
+ struct cadence_nand_timings *t)
+{
+ writel_relaxed(t->async_toggle_timings,
+ cadence->reg + ASYNC_TOGGLE_TIMINGS);
+ writel_relaxed(t->timings0, cadence->reg + TIMINGS0);
+ writel_relaxed(t->timings1, cadence->reg + TIMINGS1);
+ writel_relaxed(t->timings2, cadence->reg + TIMINGS2);
+
+ if (cadence->caps2.is_phy_type_dll)
+ writel_relaxed(t->dll_phy_ctrl, cadence->reg + DLL_PHY_CTRL);
+
+ writel_relaxed(t->phy_ctrl, cadence->reg + PHY_CTRL);
+
+ if (cadence->caps2.is_phy_type_dll) {
+ writel_relaxed(0, cadence->reg + PHY_TSEL);
+ writel_relaxed(2, cadence->reg + PHY_DQ_TIMING);
+ writel_relaxed(t->phy_dqs_timing,
+ cadence->reg + PHY_DQS_TIMING);
+ writel_relaxed(t->phy_gate_lpbk_ctrl,
+ cadence->reg + PHY_GATE_LPBK_CTRL);
+ writel_relaxed(PHY_DLL_MASTER_CTRL_BYPASS_MODE,
+ cadence->reg + PHY_DLL_MASTER_CTRL);
+ writel_relaxed(0, cadence->reg + PHY_DLL_SLAVE_CTRL);
+ }
+}
+
+static int cadence_nand_select_target(struct nand_chip *chip)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+ if (chip == cadence->selected_chip)
+ return 0;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ cadence_nand_set_timings(cadence, &cdns_chip->timings);
+
+ cadence_nand_set_ecc_strength(cadence,
+ cdns_chip->corr_str_idx);
+
+ cadence_nand_set_erase_detection(cadence, true,
+ chip->ecc.strength);
+
+ cadence->curr_trans_type = -1;
+ cadence->selected_chip = chip;
+
+ return 0;
+}
+
+static int cadence_nand_erase(struct mtd_info *mtd, int page)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ int status;
+ u8 thread_nr = cdns_chip->cs[chip->cur_cs];
+
+ cadence_nand_cdma_desc_prepare(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, 0, 0,
+ CDMA_CT_ERASE);
+ status = cadence_nand_cdma_send_and_wait(cadence, thread_nr);
+ if (status) {
+ dev_err(cadence->dev, "erase operation failed\n");
+ return -EIO;
+ }
+
+ status = cadence_nand_cdma_finish(cadence);
+ if (status)
+ return status;
+
+ return 0;
+}
+
+static int cadence_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, int oobavail)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ int ret;
+
+ /*
+ * If .size and .strength are already set (usually by DT),
+ * check if they are supported by this controller.
+ */
+ if (chip->ecc.size && chip->ecc.strength)
+ return nand_check_ecc_caps(chip, &cadence->ecc_caps, oobavail);
+
+ /*
+ * We want .size and .strength closest to the chip's requirement
+ * unless NAND_ECC_MAXIMIZE is requested.
+ */
+ if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
+ ret = nand_match_ecc_req(chip, &cadence->ecc_caps, oobavail);
+ if (!ret)
+ return 0;
+ }
+
+ /* Max ECC strength is the last thing we can do */
+ return nand_maximize_ecc(chip, &cadence->ecc_caps, oobavail);
+}
+
+static int cadence_nand_read_bbm(struct mtd_info *mtd, struct nand_chip *chip, int page, u8 *buf)
+{
+ int status;
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+ cadence_nand_prepare_data_size(mtd, TT_BBM);
+
+ cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0);
+
+ /*
+ * Read only bad block marker from offset
+ * defined by a memory manufacturer.
+ */
+ status = cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, cadence->buf, NULL,
+ mtd->oobsize,
+ 0, DMA_FROM_DEVICE, false);
+ if (status) {
+ dev_err(cadence->dev, "read BBM failed\n");
+ return -EIO;
+ }
+
+ memcpy(buf + cdns_chip->bbm_offs, cadence->buf, cdns_chip->bbm_len);
+
+ return 0;
+}
+
+static int cadence_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const u8 *buf, int oob_required, int page)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ int status;
+ u16 marker_val = 0xFFFF;
+
+ status = cadence_nand_select_target(chip);
+ if (status)
+ return status;
+
+ cadence_nand_set_skip_bytes_conf(cadence, cdns_chip->bbm_len,
+ mtd->writesize
+ + cdns_chip->bbm_offs,
+ 1);
+
+ if (oob_required) {
+ marker_val = *(u16 *)(chip->oob_poi
+ + cdns_chip->bbm_offs);
+ } else {
+ /* Set oob data to 0xFF. */
+ memset(cadence->buf + mtd->writesize, 0xFF,
+ cdns_chip->avail_oob_size);
+ }
+
+ cadence_nand_set_skip_marker_val(cadence, marker_val);
+
+ cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT);
+
+ if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
+ cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
+ u8 *oob;
+
+ if (oob_required)
+ oob = chip->oob_poi;
+ else
+ oob = cadence->buf + mtd->writesize;
+
+ status = cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, (void *)buf, oob,
+ mtd->writesize,
+ cdns_chip->avail_oob_size,
+ DMA_TO_DEVICE, true);
+ if (status) {
+ dev_err(cadence->dev, "write page failed\n");
+ return -EIO;
+ }
+
+ return 0;
+ }
+
+ if (oob_required) {
+ /* Transfer the data to the oob area. */
+ memcpy(cadence->buf + mtd->writesize, chip->oob_poi,
+ cdns_chip->avail_oob_size);
+ }
+
+ memcpy(cadence->buf, buf, mtd->writesize);
+
+ cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREAS);
+
+ return cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, cadence->buf, NULL,
+ mtd->writesize
+ + cdns_chip->avail_oob_size,
+ 0, DMA_TO_DEVICE, true);
+}
+
+static int cadence_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+
+ memset(cadence->buf, 0xFF, mtd->writesize);
+
+ return cadence_nand_write_page(mtd, chip, cadence->buf, 1, page);
+}
+
+static int cadence_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ const u8 *buf, int oob_required, int page)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ void *tmp_buf = cadence->buf;
+ int oob_skip = cdns_chip->bbm_len;
+ size_t size = writesize + oobsize;
+ int i, pos, len;
+ int status;
+
+ status = cadence_nand_select_target(chip);
+ if (status)
+ return status;
+
+ /*
+ * Fill the buffer with 0xff first except the full page transfer.
+ * This simplifies the logic.
+ */
+ if (!buf || !oob_required)
+ memset(tmp_buf, 0xff, size);
+
+ cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0);
+
+ /* Arrange the buffer for syndrome payload/ecc layout. */
+ if (buf) {
+ for (i = 0; i < ecc_steps; i++) {
+ pos = i * (ecc_size + ecc_bytes);
+ len = ecc_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(tmp_buf + pos, buf, len);
+ buf += len;
+ if (len < ecc_size) {
+ len = ecc_size - len;
+ memcpy(tmp_buf + writesize + oob_skip, buf,
+ len);
+ buf += len;
+ }
+ }
+ }
+
+ if (oob_required) {
+ const u8 *oob = chip->oob_poi;
+ u32 oob_data_offset = (cdns_chip->sector_count - 1) *
+ (cdns_chip->sector_size + chip->ecc.bytes)
+ + cdns_chip->sector_size + oob_skip;
+
+ /* BBM at the beginning of the OOB area. */
+ memcpy(tmp_buf + writesize, oob, oob_skip);
+
+ /* OOB free. */
+ memcpy(tmp_buf + oob_data_offset, oob,
+ cdns_chip->avail_oob_size);
+ oob += cdns_chip->avail_oob_size;
+
+ /* OOB ECC. */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ if (i == (ecc_steps - 1))
+ pos += cdns_chip->avail_oob_size;
+
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(tmp_buf + pos, oob, len);
+ oob += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ memcpy(tmp_buf + writesize + oob_skip, oob,
+ len);
+ oob += len;
+ }
+ }
+ }
+
+ cadence_nand_prepare_data_size(mtd, TT_RAW_PAGE);
+
+ return cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, cadence->buf, NULL,
+ mtd->writesize +
+ mtd->oobsize,
+ 0, DMA_TO_DEVICE, false);
+}
+
+static int cadence_nand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ return cadence_nand_write_page_raw(mtd, chip, NULL, true, page);
+}
+
+static int cadence_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ u8 *buf, int oob_required, int page)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ int status;
+ int ecc_err_count = 0;
+
+ status = cadence_nand_select_target(chip);
+ if (status)
+ return status;
+
+ cadence_nand_set_skip_bytes_conf(cadence, cdns_chip->bbm_len,
+ mtd->writesize
+ + cdns_chip->bbm_offs, 1);
+
+ /*
+ * If data buffer can be accessed by DMA and data_control feature
+ * is supported then transfer data and oob directly.
+ */
+ if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
+ cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
+ u8 *oob;
+
+ if (oob_required)
+ oob = chip->oob_poi;
+ else
+ oob = cadence->buf + mtd->writesize;
+
+ cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT);
+ status = cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, buf, oob,
+ mtd->writesize,
+ cdns_chip->avail_oob_size,
+ DMA_FROM_DEVICE, true);
+ /* Otherwise use bounce buffer. */
+ } else {
+ cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREAS);
+ status = cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, cadence->buf,
+ NULL, mtd->writesize
+ + cdns_chip->avail_oob_size,
+ 0, DMA_FROM_DEVICE, true);
+
+ memcpy(buf, cadence->buf, mtd->writesize);
+ if (oob_required)
+ memcpy(chip->oob_poi,
+ cadence->buf + mtd->writesize,
+ mtd->oobsize);
+ }
+
+ switch (status) {
+ case STAT_ECC_UNCORR:
+ mtd->ecc_stats.failed++;
+ ecc_err_count++;
+ break;
+ case STAT_ECC_CORR:
+ ecc_err_count = FIELD_GET(CDMA_CS_MAXERR,
+ cadence->cdma_desc->status);
+ mtd->ecc_stats.corrected += ecc_err_count;
+ break;
+ case STAT_ERASED:
+ case STAT_OK:
+ break;
+ default:
+ dev_err(cadence->dev, "read page failed\n");
+ return -EIO;
+ }
+
+ if (oob_required)
+ if (cadence_nand_read_bbm(mtd, chip, page, chip->oob_poi))
+ return -EIO;
+
+ return ecc_err_count;
+}
+
+static int cadence_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+
+ return cadence_nand_read_page(mtd, chip, cadence->buf, 1, page);
+}
+
+static int cadence_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ u8 *buf, int oob_required, int page)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ int oob_skip = cdns_chip->bbm_len;
+ int writesize = mtd->writesize;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ void *tmp_buf = cadence->buf;
+ int i, pos, len;
+ int status;
+
+ status = cadence_nand_select_target(chip);
+ if (status)
+ return status;
+
+ cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0);
+
+ cadence_nand_prepare_data_size(mtd, TT_RAW_PAGE);
+ status = cadence_nand_cdma_transfer(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ page, cadence->buf, NULL,
+ mtd->writesize
+ + mtd->oobsize,
+ 0, DMA_FROM_DEVICE, false);
+
+ switch (status) {
+ case STAT_ERASED:
+ case STAT_OK:
+ break;
+ default:
+ dev_err(cadence->dev, "read raw page failed\n");
+ return -EIO;
+ }
+
+ /* Arrange the buffer for syndrome payload/ecc layout. */
+ if (buf) {
+ for (i = 0; i < ecc_steps; i++) {
+ pos = i * (ecc_size + ecc_bytes);
+ len = ecc_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(buf, tmp_buf + pos, len);
+ buf += len;
+ if (len < ecc_size) {
+ len = ecc_size - len;
+ memcpy(buf, tmp_buf + writesize + oob_skip,
+ len);
+ buf += len;
+ }
+ }
+ }
+
+ if (oob_required) {
+ u8 *oob = chip->oob_poi;
+ u32 oob_data_offset = (cdns_chip->sector_count - 1) *
+ (cdns_chip->sector_size + chip->ecc.bytes)
+ + cdns_chip->sector_size + oob_skip;
+
+ /* OOB free. */
+ memcpy(oob, tmp_buf + oob_data_offset,
+ cdns_chip->avail_oob_size);
+
+ /* BBM at the beginning of the OOB area. */
+ memcpy(oob, tmp_buf + writesize, oob_skip);
+
+ oob += cdns_chip->avail_oob_size;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (i == (ecc_steps - 1))
+ pos += cdns_chip->avail_oob_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(oob, tmp_buf + pos, len);
+ oob += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ memcpy(oob, tmp_buf + writesize + oob_skip,
+ len);
+ oob += len;
+ }
+ }
+ }
+ return 0;
+}
+
+static int cadence_nand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ return cadence_nand_read_page_raw(mtd, chip, NULL, true, page);
+}
+
+static void cadence_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ u8 thread_nr = 0;
+ u32 sdma_size;
+ int status;
+ int len_in_words = len >> 2;
+
+ /* Wait until slave DMA interface is ready to data transfer. */
+ status = cadence_nand_wait_on_sdma(cadence, &thread_nr, &sdma_size);
+ if (status) {
+ pr_err("Wait on sdma failed:%x\n", status);
+ hang();
+ }
+
+ if (!cadence->caps1->has_dma) {
+ readsq(cadence->io.virt, buf, len_in_words);
+
+ if (sdma_size > len) {
+ memcpy(cadence->buf, buf + (len_in_words << 2),
+ len - (len_in_words << 2));
+ readsl(cadence->io.virt, cadence->buf,
+ sdma_size / 4 - len_in_words);
+ }
+ }
+}
+
+static void cadence_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ u8 thread_nr = 0;
+ u32 sdma_size;
+ int status;
+ int len_in_words = len >> 2;
+
+ /* Wait until slave DMA interface is ready to data transfer. */
+ status = cadence_nand_wait_on_sdma(cadence, &thread_nr, &sdma_size);
+ if (status) {
+ pr_err("Wait on sdma failed:%x\n", status);
+ hang();
+ }
+
+ if (!cadence->caps1->has_dma) {
+ writesq(cadence->io.virt, buf, len_in_words);
+
+ if (sdma_size > len) {
+ memcpy(cadence->buf, buf + (len_in_words << 2),
+ len - (len_in_words << 2));
+ writesl(cadence->io.virt, cadence->buf,
+ sdma_size / 4 - len_in_words);
+ }
+ }
+}
+
+static int cadence_nand_cmd_opcode(struct nand_chip *chip, unsigned int op_id)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ u64 mini_ctrl_cmd = 0;
+ int ret;
+
+ mini_ctrl_cmd |= GCMD_LAY_TWB;
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR, GCMD_LAY_INSTR_CMD);
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_CMD, op_id);
+
+ ret = cadence_nand_generic_cmd_send(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ mini_ctrl_cmd);
+
+ if (ret)
+ dev_err(cadence->dev, "send cmd %x failed\n",
+ op_id);
+
+ return ret;
+}
+
+static int cadence_nand_cmd_address(struct nand_chip *chip,
+ unsigned int naddrs, const u8 *addrs)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ u64 address = 0;
+ u64 mini_ctrl_cmd = 0;
+ int ret;
+ int i;
+
+ mini_ctrl_cmd |= GCMD_LAY_TWB;
+
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
+ GCMD_LAY_INSTR_ADDR);
+
+ for (i = 0; i < naddrs; i++)
+ address |= (u64)addrs[i] << (8 * i);
+
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR,
+ address);
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR_SIZE,
+ naddrs - 1);
+
+ ret = cadence_nand_generic_cmd_send(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ mini_ctrl_cmd);
+
+ if (ret)
+ pr_err("send address %llx failed\n", address);
+
+ return ret;
+}
+
+static int cadence_nand_cmd_data(struct nand_chip *chip,
+ unsigned int len, u8 mode)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ u64 mini_ctrl_cmd = 0;
+ int ret;
+
+ mini_ctrl_cmd |= GCMD_LAY_TWB;
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
+ GCMD_LAY_INSTR_DATA);
+
+ if (mode)
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_DIR, GCMD_DIR_WRITE);
+
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_SECT_CNT, 1);
+ mini_ctrl_cmd |= FIELD_PREP(GCMD_LAST_SIZE, len);
+
+ ret = cadence_nand_generic_cmd_send(cadence,
+ cdns_chip->cs[chip->cur_cs],
+ mini_ctrl_cmd);
+
+ if (ret) {
+ pr_err("send generic data cmd failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int cadence_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ int status;
+
+ status = cadence_nand_wait_for_value(cadence, RBN_SETINGS,
+ TIMEOUT_US,
+ BIT(cdns_chip->cs[chip->cur_cs]),
+ false);
+ return status;
+}
+
+static int cadence_nand_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = cdns_chip->bbm_len;
+ oobregion->length = cdns_chip->avail_oob_size
+ - cdns_chip->bbm_len;
+
+ return 0;
+}
+
+static int cadence_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = cdns_chip->avail_oob_size;
+ oobregion->length = chip->ecc.total;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops cadence_nand_ooblayout_ops = {
+ .rfree = cadence_nand_ooblayout_free,
+ .ecc = cadence_nand_ooblayout_ecc,
+};
+
+static int calc_cycl(u32 timing, u32 clock)
+{
+ if (timing == 0 || clock == 0)
+ return 0;
+
+ if ((timing % clock) > 0)
+ return timing / clock;
+ else
+ return timing / clock - 1;
+}
+
+/* Calculate max data valid window. */
+static inline u32 calc_tdvw_max(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
+ u32 board_delay_skew_min, u32 ext_mode)
+{
+ if (ext_mode == 0)
+ clk_period /= 2;
+
+ return (trp_cnt + 1) * clk_period + trhoh_min +
+ board_delay_skew_min;
+}
+
+/* Calculate data valid window. */
+static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
+ u32 trea_max, u32 ext_mode)
+{
+ if (ext_mode == 0)
+ clk_period /= 2;
+
+ return (trp_cnt + 1) * clk_period + trhoh_min - trea_max;
+}
+
+static inline int of_get_child_count(const ofnode node)
+{
+ return fdtdec_get_child_count(gd->fdt_blob, ofnode_to_offset(node));
+}
+
+static int cadence_setup_data_interface(struct mtd_info *mtd, int chipnr,
+ const struct nand_data_interface *conf)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(mtd_to_nand(mtd));
+ const struct nand_sdr_timings *sdr;
+ struct cadence_nand_timings *t = &cdns_chip->timings;
+ u32 reg;
+ u32 board_delay = cadence->board_delay;
+ u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
+ cadence->nf_clk_rate);
+ u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt;
+ u32 tfeat_cnt, trhz_cnt, tvdly_cnt;
+ u32 trhw_cnt, twb_cnt, twh_cnt = 0, twhr_cnt;
+ u32 twp_cnt = 0, trp_cnt = 0, trh_cnt = 0;
+ u32 if_skew = cadence->caps1->if_skew;
+ u32 board_delay_skew_min = board_delay - if_skew;
+ u32 board_delay_skew_max = board_delay + if_skew;
+ u32 dqs_sampl_res, phony_dqs_mod;
+ u32 tdvw, tdvw_min, tdvw_max;
+ u32 ext_rd_mode, ext_wr_mode;
+ u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0;
+ u32 sampling_point;
+
+ sdr = nand_get_sdr_timings(conf);
+ if (IS_ERR(sdr))
+ return PTR_ERR(sdr);
+
+ memset(t, 0, sizeof(*t));
+ /* Sampling point calculation. */
+ if (cadence->caps2.is_phy_type_dll)
+ phony_dqs_mod = 2;
+ else
+ phony_dqs_mod = 1;
+
+ dqs_sampl_res = clk_period / phony_dqs_mod;
+
+ tdvw_min = sdr->tREA_max + board_delay_skew_max;
+ /*
+ * The idea of those calculation is to get the optimum value
+ * for tRP and tRH timings. If it is NOT possible to sample data
+ * with optimal tRP/tRH settings, the parameters will be extended.
+ * If clk_period is 50ns (the lowest value) this condition is met
+ * for SDR timing modes 1, 2, 3, 4 and 5.
+ * If clk_period is 20ns the condition is met only for SDR timing
+ * mode 5.
+ */
+ if (sdr->tRC_min <= clk_period &&
+ sdr->tRP_min <= (clk_period / 2) &&
+ sdr->tREH_min <= (clk_period / 2)) {
+ /* Performance mode. */
+ ext_rd_mode = 0;
+ tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
+ sdr->tREA_max, ext_rd_mode);
+ tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min,
+ board_delay_skew_min,
+ ext_rd_mode);
+ /*
+ * Check if data valid window and sampling point can be found
+ * and is not on the edge (ie. we have hold margin).
+ * If not extend the tRP timings.
+ */
+ if (tdvw > 0) {
+ if (tdvw_max <= tdvw_min ||
+ (tdvw_max % dqs_sampl_res) == 0) {
+ /*
+ * No valid sampling point so the RE pulse need
+ * to be widen widening by half clock cycle.
+ */
+ ext_rd_mode = 1;
+ }
+ } else {
+ /*
+ * There is no valid window
+ * to be able to sample data the tRP need to be widen.
+ * Very safe calculations are performed here.
+ */
+ trp_cnt = (sdr->tREA_max + board_delay_skew_max
+ + dqs_sampl_res) / clk_period;
+ ext_rd_mode = 1;
+ }
+
+ } else {
+ /* Extended read mode. */
+ u32 trh;
+
+ ext_rd_mode = 1;
+ trp_cnt = calc_cycl(sdr->tRP_min, clk_period);
+ trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period);
+ if (sdr->tREH_min >= trh)
+ trh_cnt = calc_cycl(sdr->tREH_min, clk_period);
+ else
+ trh_cnt = calc_cycl(trh, clk_period);
+
+ tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
+ sdr->tREA_max, ext_rd_mode);
+ /*
+ * Check if data valid window and sampling point can be found
+ * or if it is at the edge check if previous is valid
+ * - if not extend the tRP timings.
+ */
+ if (tdvw > 0) {
+ tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
+ sdr->tRHOH_min,
+ board_delay_skew_min,
+ ext_rd_mode);
+
+ if ((((tdvw_max / dqs_sampl_res)
+ * dqs_sampl_res) <= tdvw_min) ||
+ (((tdvw_max % dqs_sampl_res) == 0) &&
+ (((tdvw_max / dqs_sampl_res - 1)
+ * dqs_sampl_res) <= tdvw_min))) {
+ /*
+ * Data valid window width is lower than
+ * sampling resolution and do not hit any
+ * sampling point to be sure the sampling point
+ * will be found the RE low pulse width will be
+ * extended by one clock cycle.
+ */
+ trp_cnt = trp_cnt + 1;
+ }
+ } else {
+ /*
+ * There is no valid window to be able to sample data.
+ * The tRP need to be widen.
+ * Very safe calculations are performed here.
+ */
+ trp_cnt = (sdr->tREA_max + board_delay_skew_max
+ + dqs_sampl_res) / clk_period;
+ }
+ }
+
+ tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
+ sdr->tRHOH_min,
+ board_delay_skew_min, ext_rd_mode);
+
+ if (sdr->tWC_min <= clk_period &&
+ (sdr->tWP_min + if_skew) <= (clk_period / 2) &&
+ (sdr->tWH_min + if_skew) <= (clk_period / 2)) {
+ ext_wr_mode = 0;
+ } else {
+ u32 twh;
+
+ ext_wr_mode = 1;
+ twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period);
+ if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew))
+ twp_cnt = calc_cycl(sdr->tALS_min + if_skew,
+ clk_period);
+
+ twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period);
+ if (sdr->tWH_min >= twh)
+ twh = sdr->tWH_min;
+
+ twh_cnt = calc_cycl(twh + if_skew, clk_period);
+ }
+
+ reg = FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRH, trh_cnt);
+ reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRP, trp_cnt);
+ reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWH, twh_cnt);
+ reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWP, twp_cnt);
+ t->async_toggle_timings = reg;
+ dev_dbg(cadence->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg);
+
+ tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period);
+ tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period);
+ twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period);
+ trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period);
+ reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt);
+
+ /*
+ * If timing exceeds delay field in timing register
+ * then use maximum value.
+ */
+ if (FIELD_FIT(TIMINGS0_TCCS, tccs_cnt))
+ reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt);
+ else
+ reg |= TIMINGS0_TCCS;
+
+ reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt);
+ reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt);
+ t->timings0 = reg;
+ dev_dbg(cadence->dev, "TIMINGS0_SDR\t%x\n", reg);
+
+ /* The following is related to single signal so skew is not needed. */
+ trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period);
+ trhz_cnt = trhz_cnt + 1;
+ twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period);
+ /*
+ * Because of the two stage syncflop the value must be increased by 3
+ * first value is related with sync, second value is related
+ * with output if delay.
+ */
+ twb_cnt = twb_cnt + 3 + 5;
+ /*
+ * The following is related to the we edge of the random data input
+ * sequence so skew is not needed.
+ */
+ tvdly_cnt = calc_cycl(500000 + if_skew, clk_period);
+ reg = FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt);
+ reg |= FIELD_PREP(TIMINGS1_TWB, twb_cnt);
+ reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt);
+ t->timings1 = reg;
+ dev_dbg(cadence->dev, "TIMINGS1_SDR\t%x\n", reg);
+
+ tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period);
+ if (tfeat_cnt < twb_cnt)
+ tfeat_cnt = twb_cnt;
+
+ tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period);
+ tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period);
+
+ reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt);
+ reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt);
+ reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt);
+ t->timings2 = reg;
+ dev_dbg(cadence->dev, "TIMINGS2_SDR\t%x\n", reg);
+
+ if (cadence->caps2.is_phy_type_dll) {
+ reg = DLL_PHY_CTRL_DLL_RST_N;
+ if (ext_wr_mode)
+ reg |= DLL_PHY_CTRL_EXTENDED_WR_MODE;
+ if (ext_rd_mode)
+ reg |= DLL_PHY_CTRL_EXTENDED_RD_MODE;
+
+ reg |= FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, 7);
+ reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, 7);
+ t->dll_phy_ctrl = reg;
+ dev_dbg(cadence->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg);
+ }
+
+ /* Sampling point calculation. */
+ if ((tdvw_max % dqs_sampl_res) > 0)
+ sampling_point = tdvw_max / dqs_sampl_res;
+ else
+ sampling_point = (tdvw_max / dqs_sampl_res - 1);
+
+ if (sampling_point * dqs_sampl_res > tdvw_min) {
+ dll_phy_dqs_timing =
+ FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, 4);
+ dll_phy_dqs_timing |= PHY_DQS_TIMING_USE_PHONY_DQS;
+ phony_dqs_timing = sampling_point / phony_dqs_mod;
+
+ if ((sampling_point % 2) > 0) {
+ dll_phy_dqs_timing |= PHY_DQS_TIMING_PHONY_DQS_SEL;
+ if ((tdvw_max % dqs_sampl_res) == 0)
+ /*
+ * Calculation for sampling point at the edge
+ * of data and being odd number.
+ */
+ phony_dqs_timing = (tdvw_max / dqs_sampl_res)
+ / phony_dqs_mod - 1;
+
+ if (!cadence->caps2.is_phy_type_dll)
+ phony_dqs_timing--;
+
+ } else {
+ phony_dqs_timing--;
+ }
+ rd_del_sel = phony_dqs_timing + 3;
+ } else {
+ dev_warn(cadence->dev,
+ "ERROR : cannot find valid sampling point\n");
+ }
+
+ reg = FIELD_PREP(PHY_CTRL_PHONY_DQS, phony_dqs_timing);
+ if (cadence->caps2.is_phy_type_dll)
+ reg |= PHY_CTRL_SDR_DQS;
+ t->phy_ctrl = reg;
+ dev_dbg(cadence->dev, "PHY_CTRL_REG_SDR\t%x\n", reg);
+
+ if (cadence->caps2.is_phy_type_dll) {
+ dev_dbg(cadence->dev, "PHY_TSEL_REG_SDR\t%x\n", 0);
+ dev_dbg(cadence->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2);
+ dev_dbg(cadence->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n",
+ dll_phy_dqs_timing);
+ t->phy_dqs_timing = dll_phy_dqs_timing;
+
+ reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel);
+ dev_dbg(cadence->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n",
+ reg);
+ t->phy_gate_lpbk_ctrl = reg;
+
+ dev_dbg(cadence->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n",
+ PHY_DLL_MASTER_CTRL_BYPASS_MODE);
+ dev_dbg(cadence->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0);
+ }
+ return 0;
+}
+
+static int cadence_nand_attach_chip(struct nand_chip *chip)
+{
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+ static struct nand_ecclayout nand_oob;
+ u32 ecc_size;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
+
+ if (chip->options & NAND_BUSWIDTH_16) {
+ ret = cadence_nand_set_access_width16(cadence, true);
+ if (ret)
+ return ret;
+ }
+
+ chip->options |= NAND_USE_BOUNCE_BUFFER;
+ chip->bbt_options |= NAND_BBT_USE_FLASH;
+ chip->bbt_options |= NAND_BBT_NO_OOB;
+ chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+
+ cdns_chip->bbm_offs = chip->badblockpos;
+ cdns_chip->bbm_offs &= ~0x01;
+ /* this value should be even number */
+ cdns_chip->bbm_len = 2;
+
+ ret = cadence_ecc_setup(mtd, chip, mtd->oobsize - cdns_chip->bbm_len);
+ if (ret) {
+ dev_err(cadence->dev, "ECC configuration failed\n");
+ return ret;
+ }
+
+ dev_dbg(cadence->dev,
+ "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
+ chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+
+ /* Error correction configuration. */
+ cdns_chip->sector_size = chip->ecc.size;
+ cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
+ ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
+
+ cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
+
+ if (cdns_chip->avail_oob_size > cadence->bch_metadata_size)
+ cdns_chip->avail_oob_size = cadence->bch_metadata_size;
+
+ if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
+ > mtd->oobsize)
+ cdns_chip->avail_oob_size -= 4;
+
+ ret = cadence_nand_get_ecc_strength_idx(cadence, chip->ecc.strength);
+ if (ret < 0)
+ return -EINVAL;
+
+ cdns_chip->corr_str_idx = (u8)ret;
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ cadence_nand_set_ecc_strength(cadence,
+ cdns_chip->corr_str_idx);
+
+ cadence_nand_set_erase_detection(cadence, true,
+ chip->ecc.strength);
+
+ dev_dbg(cadence->dev,
+ "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
+ chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+
+ /* Override the default read operations. */
+ chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
+ chip->ecc.read_page = cadence_nand_read_page;
+ chip->ecc.read_page_raw = cadence_nand_read_page_raw;
+ chip->ecc.write_page = cadence_nand_write_page;
+ chip->ecc.write_page_raw = cadence_nand_write_page_raw;
+ chip->ecc.read_oob = cadence_nand_read_oob;
+ chip->ecc.write_oob = cadence_nand_write_oob;
+ chip->ecc.read_oob_raw = cadence_nand_read_oob_raw;
+ chip->ecc.write_oob_raw = cadence_nand_write_oob_raw;
+ chip->erase = cadence_nand_erase;
+
+ if ((mtd->writesize + mtd->oobsize) > cadence->buf_size)
+ cadence->buf_size = mtd->writesize + mtd->oobsize;
+
+ mtd_set_ooblayout(mtd, &cadence_nand_ooblayout_ops);
+
+ nand_oob.eccbytes = cdns_chip->chip.ecc.bytes;
+ cdns_chip->chip.ecc.layout = &nand_oob;
+
+ return 0;
+}
+
+/* Dummy implementation: we don't support multiple chips */
+static void cadence_nand_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ switch (chipnr) {
+ case -1:
+ case 0:
+ break;
+
+ default:
+ WARN_ON(chipnr);
+ }
+}
+
+static int cadence_nand_status(struct mtd_info *mtd, unsigned int command)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int ret = 0;
+
+ ret = cadence_nand_cmd_opcode(chip, command);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_cmd_data(chip, 1, GCMD_DIR_READ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int cadence_nand_readid(struct mtd_info *mtd, int offset_in_page, unsigned int command)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ u8 addrs = (u8)offset_in_page;
+ int ret = 0;
+
+ ret = cadence_nand_cmd_opcode(chip, command);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &addrs);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_cmd_data(chip, 8, GCMD_DIR_READ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int cadence_nand_param(struct mtd_info *mtd, u8 offset_in_page, unsigned int command)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int ret = 0;
+
+ ret = cadence_nand_cmd_opcode(chip, command);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &offset_in_page);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_waitfunc(mtd, chip);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_cmd_data(chip, sizeof(struct nand_jedec_params), GCMD_DIR_READ);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int cadence_nand_reset(struct mtd_info *mtd, unsigned int command)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int ret = 0;
+
+ ret = cadence_nand_cmd_opcode(chip, command);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_waitfunc(mtd, chip);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int cadence_nand_features(struct mtd_info *mtd, u8 offset_in_page, u32 command)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int ret = 0;
+
+ ret = cadence_nand_cmd_opcode(chip, command);
+ if (ret)
+ return ret;
+
+ ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &offset_in_page);
+ if (ret)
+ return ret;
+
+ if (command == NAND_CMD_GET_FEATURES)
+ ret = cadence_nand_cmd_data(chip, ONFI_SUBFEATURE_PARAM_LEN,
+ GCMD_DIR_READ);
+ else
+ ret = cadence_nand_cmd_data(chip, ONFI_SUBFEATURE_PARAM_LEN,
+ GCMD_DIR_WRITE);
+
+ return ret;
+}
+
+static void cadence_nand_cmdfunc(struct mtd_info *mtd, unsigned int command,
+ int offset_in_page, int page)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ int ret = 0;
+
+ cadence->cmd = command;
+ switch (command) {
+ case NAND_CMD_STATUS:
+ ret = cadence_nand_status(mtd, command);
+ break;
+
+ case NAND_CMD_READID:
+ ret = cadence_nand_readid(mtd, offset_in_page, command);
+ break;
+
+ case NAND_CMD_PARAM:
+ ret = cadence_nand_param(mtd, offset_in_page, command);
+ break;
+
+ case NAND_CMD_RESET:
+ ret = cadence_nand_reset(mtd, command);
+ break;
+
+ case NAND_CMD_SET_FEATURES:
+ case NAND_CMD_GET_FEATURES:
+ ret = cadence_nand_features(mtd, offset_in_page, command);
+ break;
+ /*
+ * ecc will override other command for read, write and erase
+ */
+ default:
+ break;
+ }
+
+ if (cadence->cmd == NAND_CMD_RESET) {
+ ret = cadence_nand_select_target(chip);
+ if (ret)
+ dev_err(cadence->dev, "Chip select failure after reset\n");
+ }
+
+ if (ret != 0)
+ printf("ERROR:%s:command:0x%x\n", __func__, cadence->cmd);
+}
+
+static int cadence_nand_dev_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+
+ if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+ TIMEOUT_US,
+ CTRL_STATUS_CTRL_BUSY, true))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static u8 cadence_nand_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+ u32 size = 1;
+ u8 val;
+
+ if (cadence->buf_index == 0) {
+ if (cadence->cmd == NAND_CMD_READID)
+ size = 8;
+ else if (cadence->cmd == NAND_CMD_PARAM)
+ size = sizeof(struct nand_jedec_params);
+ else if (cadence->cmd == NAND_CMD_GET_FEATURES)
+ size = ONFI_SUBFEATURE_PARAM_LEN;
+
+ cadence_nand_read_buf(mtd, &cadence->buf[0], size);
+ }
+
+ val = *(&cadence->buf[0] + cadence->buf_index);
+ cadence->buf_index++;
+
+ return val;
+}
+
+static void cadence_nand_write_byte(struct mtd_info *mtd, u8 byte)
+{
+ cadence_nand_write_buf(mtd, &byte, 1);
+}
+
+static int cadence_nand_chip_init(struct cadence_nand_info *cadence, ofnode node)
+{
+ struct cdns_nand_chip *cdns_chip;
+ struct nand_chip *chip;
+ struct mtd_info *mtd;
+ int ret, i;
+ int nsels;
+ u32 cs;
+
+ if (!ofnode_get_property(node, "reg", &nsels))
+ return -ENODEV;
+
+ nsels /= sizeof(u32);
+ if (nsels <= 0) {
+ dev_err(cadence->dev, "invalid reg property size %d\n", nsels);
+ return -EINVAL;
+ }
+
+ cdns_chip = devm_kzalloc(cadence->dev, sizeof(*cdns_chip) +
+ (nsels * sizeof(u8)), GFP_KERNEL);
+ if (!cdns_chip)
+ return -ENODEV;
+
+ cdns_chip->nsels = nsels;
+ for (i = 0; i < nsels; i++) {
+ /* Retrieve CS id. */
+ ret = ofnode_read_u32_index(node, "reg", i, &cs);
+ if (ret) {
+ dev_err(cadence->dev,
+ "could not retrieve reg property: %d\n",
+ ret);
+ goto free_buf;
+ }
+
+ if (cs >= cadence->caps2.max_banks) {
+ dev_err(cadence->dev,
+ "invalid reg value: %u (max CS = %d)\n",
+ cs, cadence->caps2.max_banks);
+ ret = -EINVAL;
+ goto free_buf;
+ }
+
+ if (test_and_set_bit(cs, &cadence->assigned_cs)) {
+ dev_err(cadence->dev,
+ "CS %d already assigned\n", cs);
+ ret = -EINVAL;
+ goto free_buf;
+ }
+
+ cdns_chip->cs[i] = cs;
+ }
+
+ chip = &cdns_chip->chip;
+ chip->controller = &cadence->controller;
+ nand_set_flash_node(chip, node);
+ mtd = nand_to_mtd(chip);
+ mtd->dev->parent = cadence->dev;
+
+ chip->options |= NAND_BUSWIDTH_AUTO;
+ chip->select_chip = cadence_nand_select_chip;
+ chip->cmdfunc = cadence_nand_cmdfunc;
+ chip->dev_ready = cadence_nand_dev_ready;
+ chip->read_byte = cadence_nand_read_byte;
+ chip->write_byte = cadence_nand_write_byte;
+ chip->waitfunc = cadence_nand_waitfunc;
+ chip->read_buf = cadence_nand_read_buf;
+ chip->write_buf = cadence_nand_write_buf;
+ chip->setup_data_interface = cadence_setup_data_interface;
+
+ ret = nand_scan_ident(mtd, 1, NULL);
+ if (ret) {
+ dev_err(cadence->dev, "Chip identification failure\n");
+ goto free_buf;
+ }
+
+ ret = cadence_nand_attach_chip(chip);
+ if (ret) {
+ dev_err(cadence->dev, "Chip not able to attached\n");
+ goto free_buf;
+ }
+
+ ret = nand_scan_tail(mtd);
+ if (ret) {
+ dev_err(cadence->dev, "could not scan the nand chip\n");
+ goto free_buf;
+ }
+
+ ret = nand_register(0, mtd);
+ if (ret) {
+ dev_err(cadence->dev, "Failed to register MTD: %d\n", ret);
+ goto free_buf;
+ }
+
+ return 0;
+
+free_buf:
+ devm_kfree(cadence->dev, cdns_chip);
+ return ret;
+}
+
+static int cadence_nand_chips_init(struct cadence_nand_info *cadence)
+{
+ struct udevice *dev = cadence->dev;
+ ofnode node = dev_ofnode(dev);
+ ofnode nand_node;
+ int max_cs = cadence->caps2.max_banks;
+ int nchips, ret;
+
+ nchips = of_get_child_count(node);
+
+ if (nchips > max_cs) {
+ dev_err(cadence->dev,
+ "too many NAND chips: %d (max = %d CS)\n",
+ nchips, max_cs);
+ return -EINVAL;
+ }
+
+ ofnode_for_each_subnode(nand_node, node) {
+ ret = cadence_nand_chip_init(cadence, nand_node);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cadence_nand_init(struct cadence_nand_info *cadence)
+{
+ int ret;
+
+ cadence->cdma_desc = dma_alloc_coherent(sizeof(*cadence->cdma_desc),
+ (unsigned long *)&cadence->dma_cdma_desc);
+ if (!cadence->cdma_desc)
+ return -ENOMEM;
+
+ cadence->buf_size = SZ_16K;
+ cadence->buf = kmalloc(cadence->buf_size, GFP_KERNEL);
+ if (!cadence->buf) {
+ ret = -ENOMEM;
+ goto free_buf_desc;
+ }
+
+ //Hardware initialization
+ ret = cadence_nand_hw_init(cadence);
+ if (ret)
+ goto free_buf;
+
+ cadence->curr_corr_str_idx = 0xFF;
+
+ ret = cadence_nand_chips_init(cadence);
+ if (ret) {
+ dev_err(cadence->dev, "Failed to register MTD: %d\n",
+ ret);
+ goto free_buf;
+ }
+
+ kfree(cadence->buf);
+ cadence->buf = kzalloc(cadence->buf_size, GFP_KERNEL);
+ if (!cadence->buf) {
+ ret = -ENOMEM;
+ goto free_buf_desc;
+ }
+
+ return 0;
+
+free_buf:
+ kfree(cadence->buf);
+
+free_buf_desc:
+ dma_free_coherent(cadence->cdma_desc);
+
+ return ret;
+}
+
+static const struct cadence_nand_dt_devdata cadence_nand_default = {
+ .if_skew = 0,
+ .has_dma = 0,
+};
+
+static const struct udevice_id cadence_nand_dt_ids[] = {
+ {
+ .compatible = "cdns,nand",
+ .data = (unsigned long)&cadence_nand_default
+ }, {}
+};
+
+static int cadence_nand_dt_probe(struct udevice *dev)
+{
+ struct cadence_nand_info *cadence = dev_get_priv(dev);
+ const struct udevice_id *of_id;
+ const struct cadence_nand_dt_devdata *devdata;
+ struct resource res;
+ int ret;
+ u32 val;
+
+ if (!dev) {
+ dev_warn(dev, "Device ptr null\n");
+ return -EINVAL;
+ }
+
+ of_id = &cadence_nand_dt_ids[0];
+ devdata = (struct cadence_nand_dt_devdata *)of_id->data;
+
+ cadence->caps1 = devdata;
+ cadence->dev = dev;
+
+ ret = clk_get_by_index(dev, 0, &cadence->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&cadence->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOMEM) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+ cadence->nf_clk_rate = clk_get_rate(&cadence->clk);
+
+ ret = reset_get_by_index(dev, 1, &cadence->softphy_reset);
+ if (ret) {
+ if (ret != -ENOMEM)
+ dev_warn(dev, "Can't get softphy_reset: %d\n", ret);
+ } else {
+ reset_deassert(&cadence->softphy_reset);
+ }
+
+ ret = reset_get_by_index(dev, 0, &cadence->nand_reset);
+ if (ret) {
+ if (ret != -ENOMEM)
+ dev_warn(dev, "Can't get nand_reset: %d\n", ret);
+ } else {
+ reset_deassert(&cadence->nand_reset);
+ }
+
+ ret = dev_read_resource_byname(dev, "reg", &res);
+ if (ret)
+ return ret;
+ cadence->reg = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = dev_read_resource_byname(dev, "sdma", &res);
+ if (ret)
+ return ret;
+ cadence->io.dma = res.start;
+ cadence->io.virt = devm_ioremap(dev, res.start, resource_size(&res));
+
+ ret = ofnode_read_u32(dev_ofnode(dev->parent),
+ "cdns,board-delay-ps", &val);
+ if (ret) {
+ val = 4830;
+ dev_info(cadence->dev,
+ "missing cdns,board-delay-ps property, %d was set\n",
+ val);
+ }
+ cadence->board_delay = val;
+
+ ret = cadence_nand_init(cadence);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(cadence_nand_dt) = {
+ .name = "cadence-nand-dt",
+ .id = UCLASS_MTD,
+ .of_match = cadence_nand_dt_ids,
+ .probe = cadence_nand_dt_probe,
+ .priv_auto = sizeof(struct cadence_nand_info),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(cadence_nand_dt),
+ &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize Cadence NAND controller. (error %d)\n",
+ ret);
+}
diff --git a/drivers/mtd/nand/raw/cadence_spl.c b/drivers/mtd/nand/raw/cadence_spl.c
new file mode 100644
index 0000000..17058e4
--- /dev/null
+++ b/drivers/mtd/nand/raw/cadence_spl.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <cadence-nand.h>
+#include <dm.h>
+#include <hang.h>
+#include <nand.h>
+#include <system-constants.h>
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+
+ mtd = get_nand_dev_by_index(nand_curr_device);
+ if (!mtd)
+ hang();
+ chip = mtd_to_nand(mtd);
+
+ if (chip->select_chip)
+ chip->select_chip(mtd, -1);
+}
+
+static int nand_is_bad_block(int block)
+{
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+ loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE;
+
+ mtd = get_nand_dev_by_index(nand_curr_device);
+ if (!mtd)
+ hang();
+ chip = mtd_to_nand(mtd);
+
+ return chip->block_bad(mtd, ofs);
+}
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+ struct mtd_info *mtd;
+ int page_addr = block * SYS_NAND_BLOCK_PAGES + page;
+ loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE;
+ int ret;
+ size_t len = CONFIG_SYS_NAND_PAGE_SIZE;
+
+ mtd = get_nand_dev_by_index(nand_curr_device);
+ if (!mtd)
+ hang();
+
+ ret = nand_read(mtd, ofs, &len, dst);
+ if (ret)
+ printf("nand_read failed %d\n", ret);
+
+ return ret;
+}
+#include "nand_spl_loaders.c"
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
index 28c851f10..7e683f4 100644
--- a/drivers/mtd/nand/raw/meson_nand.c
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -618,9 +618,7 @@
memcpy(meson_chip->data_buf, buf, mtd->writesize);
memset(meson_chip->info_buf, 0, chip->ecc.steps * PER_INFO_BYTE);
-
- if (oob_required)
- meson_nfc_set_user_byte(chip, chip->oob_poi);
+ meson_nfc_set_user_byte(chip, chip->oob_poi);
return meson_nfc_write_page_sub(chip, page, false);
}
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 1b65c6f..bb5460e 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -306,6 +306,35 @@
ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
}
+/*
+ * nand_bbm_get_next_page - Get the next page for bad block markers
+ * @chip: The NAND chip
+ * @page: First page to start checking for bad block marker usage
+ *
+ * Returns an integer that corresponds to the page offset within a block, for
+ * a page that is used to store bad block markers. If no more pages are
+ * available, -EINVAL is returned.
+ */
+int nand_bbm_get_next_page(struct nand_chip *chip, int page)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int last_page = ((mtd->erasesize - mtd->writesize) >>
+ chip->page_shift) & chip->pagemask;
+ unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
+ | NAND_BBM_LASTPAGE;
+
+ if (page == 0 && !(chip->options & bbm_flags))
+ return 0;
+ if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
+ return 0;
+ if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
+ return 1;
+ if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
+ return last_page;
+
+ return -EINVAL;
+}
+
/**
* nand_block_bad - [DEFAULT] Read bad block marker from the chip
* @mtd: MTD device structure
@@ -315,40 +344,32 @@
*/
static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
- int page, res = 0, i = 0;
struct nand_chip *chip = mtd_to_nand(mtd);
- u16 bad;
+ int first_page, page_offset;
+ int res;
+ u8 bad;
- if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
- ofs += mtd->erasesize - mtd->writesize;
+ first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+ page_offset = nand_bbm_get_next_page(chip, 0);
- page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+ while (page_offset >= 0) {
+ res = chip->ecc.read_oob(mtd, chip, first_page + page_offset);
+ if (res < 0)
+ return res;
- do {
- if (chip->options & NAND_BUSWIDTH_16) {
- chip->cmdfunc(mtd, NAND_CMD_READOOB,
- chip->badblockpos & 0xFE, page);
- bad = cpu_to_le16(chip->read_word(mtd));
- if (chip->badblockpos & 0x1)
- bad >>= 8;
- else
- bad &= 0xFF;
- } else {
- chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
- page);
- bad = chip->read_byte(mtd);
- }
+ bad = chip->oob_poi[chip->badblockpos];
if (likely(chip->badblockbits == 8))
res = bad != 0xFF;
else
res = hweight8(bad) < chip->badblockbits;
- ofs += mtd->writesize;
- page = (int)(ofs >> chip->page_shift) & chip->pagemask;
- i++;
- } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+ if (res)
+ return res;
+
+ page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
+ }
- return res;
+ return 0;
}
/**
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index c48ae6e..ee8eae1 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -389,10 +389,126 @@
#define KSZ9131RN_DLL_ENABLE_DELAY 0
#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
+#define KSZ9131RN_COMMON_CTRL 0
+#define KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE BIT(4)
+
+#define KSZ9131RN_LED_ERRATA_REG 0x1e
+#define KSZ9131RN_LED_ERRATA_BIT BIT(9)
+
+#define KSZ9131RN_CONTROL_PAD_SKEW 4
+#define KSZ9131RN_RX_DATA_PAD_SKEW 5
+#define KSZ9131RN_TX_DATA_PAD_SKEW 6
+#define KSZ9131RN_CLK_PAD_SKEW 8
+
+#define KSZ9131RN_SKEW_5BIT_MAX 2400
+#define KSZ9131RN_SKEW_4BIT_MAX 800
+#define KSZ9131RN_OFFSET 700
+#define KSZ9131RN_STEP 100
+
+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
+ ofnode of_node,
+ u16 reg, size_t field_sz,
+ const char *field[], u8 numfields)
+{
+ int val[4] = {-(1 + KSZ9131RN_OFFSET), -(2 + KSZ9131RN_OFFSET),
+ -(3 + KSZ9131RN_OFFSET), -(4 + KSZ9131RN_OFFSET)};
+ int skewval, skewmax = 0;
+ int matches = 0;
+ u16 maxval;
+ u16 newval;
+ u16 mask;
+ int i;
+
+ /* psec properties in dts should mean x pico seconds */
+ if (field_sz == 5)
+ skewmax = KSZ9131RN_SKEW_5BIT_MAX;
+ else
+ skewmax = KSZ9131RN_SKEW_4BIT_MAX;
+
+ for (i = 0; i < numfields; i++)
+ if (!ofnode_read_s32(of_node, field[i], &skewval)) {
+ if (skewval < -KSZ9131RN_OFFSET)
+ skewval = -KSZ9131RN_OFFSET;
+ else if (skewval > skewmax)
+ skewval = skewmax;
+
+ val[i] = skewval + KSZ9131RN_OFFSET;
+ matches++;
+ }
+
+ if (!matches)
+ return 0;
+
+ if (matches < numfields)
+ newval = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg);
+ else
+ newval = 0;
+
+ maxval = (field_sz == 4) ? 0xf : 0x1f;
+ for (i = 0; i < numfields; i++)
+ if (val[i] != -(i + 1 + KSZ9131RN_OFFSET)) {
+ mask = 0xffff;
+ mask ^= maxval << (field_sz * i);
+ newval = (newval & mask) |
+ (((val[i] / KSZ9131RN_STEP) & maxval)
+ << (field_sz * i));
+ }
+
+ return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg, newval);
+}
+
+static int ksz9131_of_load_all_skew_values(struct phy_device *phydev)
+{
+ const char *control_skews[2] = { "txen-skew-psec", "rxdv-skew-psec" };
+ const char *clk_skews[2] = { "rxc-skew-psec", "txc-skew-psec" };
+ const char *rx_data_skews[4] = {
+ "rxd0-skew-psec", "rxd1-skew-psec",
+ "rxd2-skew-psec", "rxd3-skew-psec"
+ };
+ const char *tx_data_skews[4] = {
+ "txd0-skew-psec", "txd1-skew-psec",
+ "txd2-skew-psec", "txd3-skew-psec"
+ };
+ struct ofnode_phandle_args phandle_args;
+ int ret;
+
+ /*
+ * Silently ignore failure here as the device tree is not required to
+ * contain a phy node.
+ */
+ if (dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL, 0, 0,
+ &phandle_args))
+ return 0;
+
+ if (!ofnode_valid(phandle_args.node))
+ return 0;
+
+ ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_CLK_PAD_SKEW, 5,
+ clk_skews, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_CONTROL_PAD_SKEW, 4,
+ control_skews, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_RX_DATA_PAD_SKEW, 4,
+ rx_data_skews, 4);
+ if (ret < 0)
+ return ret;
+
+ return ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_TX_DATA_PAD_SKEW, 4,
+ tx_data_skews, 4);
+}
+
static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
{
- struct phy_driver *drv = phydev->drv;
- u16 rxcdll_val, txcdll_val, val;
+ u16 rxcdll_val, txcdll_val;
int ret;
switch (phydev->interface) {
@@ -416,24 +532,37 @@
return 0;
}
- val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_RXC_DLL_CTRL);
- val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
- val |= rxcdll_val;
- ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_RXC_DLL_CTRL, val);
- if (ret)
+ ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ rxcdll_val);
+ if (ret < 0)
return ret;
- val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_TXC_DLL_CTRL);
+ return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ txcdll_val);
+}
+
+/* Silicon Errata DS80000693B
+ *
+ * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
+ * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
+ * according to the datasheet (off if there is no link).
+ */
+static int ksz9131_led_errata(struct phy_device *phydev)
+{
+ int reg;
- val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
- val |= txcdll_val;
- ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_TXC_DLL_CTRL, val);
+ reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_COMMON_CTRL);
+ if (reg < 0)
+ return reg;
- return ret;
+ if (!(reg & KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE))
+ return 0;
+
+ return phy_set_bits(phydev, MDIO_DEVAD_NONE, KSZ9131RN_LED_ERRATA_REG,
+ KSZ9131RN_LED_ERRATA_BIT);
}
static int ksz9131_config(struct phy_device *phydev)
@@ -446,6 +575,14 @@
return ret;
}
+ ret = ksz9131_of_load_all_skew_values(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_led_errata(phydev);
+ if (ret < 0)
+ return ret;
+
/* add an option to disable the gigabit feature of this PHY */
if (env_get("disable_giga")) {
unsigned features;
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c39bef1..539fd37 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -592,7 +592,7 @@
ret = clk_get_bulk(dev, ð->clks);
if (ret < 0)
- goto err_mdio_alloc;
+ goto err_clk_get;
mdiodev = mdio_alloc();
if (!mdiodev) {
@@ -614,23 +614,25 @@
/* Bring up PHY */
ret = clk_enable_bulk(ð->clks);
if (ret)
- goto err_mdio_register;
+ goto err_clk_enable;
ret = ravb_reset(dev);
if (ret)
- goto err_mdio_reset;
+ goto err_clk_enable;
ret = ravb_phy_config(dev);
if (ret)
- goto err_mdio_reset;
+ goto err_clk_enable;
return 0;
-err_mdio_reset:
- clk_release_bulk(ð->clks);
+err_clk_enable:
+ mdio_unregister(mdiodev);
err_mdio_register:
mdio_free(mdiodev);
err_mdio_alloc:
+ clk_release_bulk(ð->clks);
+err_clk_get:
unmap_physmem(eth->iobase, MAP_NOCACHE);
return ret;
}
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index c70b42f..3c62fc0 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -661,7 +661,7 @@
dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
if (pdata->max_speed)
- dev_err(dev, "Port %u speed froced to %uMbit\n",
+ dev_err(dev, "Port %u speed forced to %uMbit\n",
priv->port_id, pdata->max_speed);
return 0;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e12347e..d3fe90d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -163,8 +163,8 @@
config PHY_RCAR_GEN3
tristate "Renesas R-Car Gen3 USB PHY"
- depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR
- default y if RCAR_GEN3
+ depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L)
+ default y if (RCAR_GEN3 || RZG2L)
help
Support for the Renesas R-Car Gen3 USB PHY. This driver operates the
PHY connected to EHCI USB module and controls USB OTG operation.
@@ -309,5 +309,6 @@
source "drivers/phy/ti/Kconfig"
source "drivers/phy/qcom/Kconfig"
source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c35f929..ce4ea28 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@
obj-y += ti/
obj-y += qcom/
obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c
index 8c004ea..d06861c 100644
--- a/drivers/phy/phy-rcar-gen3.c
+++ b/drivers/phy/phy-rcar-gen3.c
@@ -55,6 +55,7 @@
/* VBCTRL */
#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
+#define USB2_VBCTRL_VBOUT BIT(0)
/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN BIT(19)
@@ -68,6 +69,13 @@
#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)
+/* RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON BIT(0)
+
+/* Device flags */
+#define RCAR_GEN3_PHY_NO_ADPCTRL BIT(0)
+
struct rcar_gen3_phy {
fdt_addr_t regs;
struct clk clk;
@@ -122,15 +130,50 @@
return regulator_set_enable(priv->vbus_supply, false);
}
+static bool rcar_gen3_phy_check_id(struct phy *phy)
+{
+ const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
+ struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+ ulong flags = dev_get_driver_data(phy->dev);
+ u32 val;
+
+ if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+ val = readl(priv->regs + USB2_LINECTRL1);
+ return !!(val & USB2_LINECTRL1_USB2_IDMON);
+ }
+
+ val = readl(priv->regs + USB2_ADPCTRL);
+ return (val & adpdevmask) == adpdevmask;
+}
+
+static void rcar_gen3_phy_set_vbus(struct phy *phy, bool enable)
+{
+ struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+ ulong flags = dev_get_driver_data(phy->dev);
+ u32 bits = USB2_ADPCTRL_DRVVBUS;
+ u64 reg = USB2_ADPCTRL;
+
+ if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+ bits = USB2_VBCTRL_VBOUT;
+ reg = USB2_VBCTRL;
+ }
+
+ if (enable)
+ setbits_le32(priv->regs + reg, bits);
+ else
+ clrbits_le32(priv->regs + reg, bits);
+}
+
static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
int submode)
{
- const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
- u32 adpctrl;
+ ulong flags = dev_get_driver_data(phy->dev);
if (mode == PHY_MODE_USB_OTG) {
if (submode) {
+ u32 obint_enable_bits;
+
/* OTG submode is used as initialization indicator */
writel(USB2_INT_ENABLE_UCOM_INTEN |
USB2_INT_ENABLE_USBH_INTB_EN |
@@ -138,13 +181,16 @@
priv->regs + USB2_INT_ENABLE);
setbits_le32(priv->regs + USB2_VBCTRL,
USB2_VBCTRL_DRVVBUSSEL);
- writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG,
- priv->regs + USB2_OBINTSTA);
- setbits_le32(priv->regs + USB2_OBINTEN,
- USB2_OBINT_SESSVLDCHG |
- USB2_OBINT_IDDIGCHG);
- setbits_le32(priv->regs + USB2_ADPCTRL,
- USB2_ADPCTRL_IDPULLUP);
+ if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+ obint_enable_bits = USB2_OBINT_IDCHG_EN;
+ } else {
+ obint_enable_bits = USB2_OBINT_SESSVLDCHG |
+ USB2_OBINT_IDDIGCHG;
+ setbits_le32(priv->regs + USB2_ADPCTRL,
+ USB2_ADPCTRL_IDPULLUP);
+ }
+ writel(obint_enable_bits, priv->regs + USB2_OBINTSTA);
+ setbits_le32(priv->regs + USB2_OBINTEN, obint_enable_bits);
clrsetbits_le32(priv->regs + USB2_LINECTRL1,
USB2_LINECTRL1_DP_RPD |
USB2_LINECTRL1_DM_RPD |
@@ -154,8 +200,7 @@
USB2_LINECTRL1_DMRPD_EN);
}
- adpctrl = readl(priv->regs + USB2_ADPCTRL);
- if ((adpctrl & adpdevmask) == adpdevmask)
+ if (rcar_gen3_phy_check_id(phy))
mode = PHY_MODE_USB_DEVICE;
else
mode = PHY_MODE_USB_HOST;
@@ -165,13 +210,13 @@
clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
setbits_le32(priv->regs + USB2_LINECTRL1,
USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
- setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+ rcar_gen3_phy_set_vbus(phy, true);
} else if (mode == PHY_MODE_USB_DEVICE) {
setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
clrsetbits_le32(priv->regs + USB2_LINECTRL1,
USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD,
USB2_LINECTRL1_DM_RPD);
- clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+ rcar_gen3_phy_set_vbus(phy, false);
} else {
dev_err(phy->dev, "Unknown mode %d\n", mode);
return -EINVAL;
@@ -226,7 +271,13 @@
}
static const struct udevice_id rcar_gen3_phy_of_match[] = {
- { .compatible = "renesas,rcar-gen3-usb2-phy", },
+ {
+ .compatible = "renesas,rcar-gen3-usb2-phy",
+ },
+ {
+ .compatible = "renesas,rzg2l-usb2-phy",
+ .data = RCAR_GEN3_PHY_NO_ADPCTRL,
+ },
{ },
};
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 0000000..d11338e
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,21 @@
+#
+# PHY drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_PCIE
+ bool "Starfive JH7110 PCIe 2.0 PHY driver"
+ depends on PHY
+ help
+ Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
+ Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
+
+config PHY_STARFIVE_JH7110_USB2
+ bool "Starfive JH7110 USB 2.0 PHY driver"
+ depends on PHY
+ help
+ Enable this to support the Starfive JH7110 USB 2.0 PHY.
+ Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 0000000..82f25aa
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 0000000..a305828
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include "phy-jh7110-usb-syscon.h"
+
+#define PCIE_KVCO_LEVEL_OFF 0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c
+#define PCIE_USB3_PHY_SS_MODE BIT(4)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80
+#define PHY_KVCO_FINE_TUNE_LEVEL 0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define PCIE_USB3_PHY_MODE 0x1
+#define PCIE_BUS_WIDTH 0x2
+#define PCIE_USB3_PHY_ENABLE 0x1
+#define PCIE_USB3_PHY_SPLIT 0x1
+
+struct jh7110_pcie_phy {
+ struct phy *phy;
+ struct regmap *stg_syscon;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ struct regmap_field *phy_mode;
+ struct regmap_field *bus_width;
+ struct regmap_field *usb3_phy_en;
+ struct regmap_field *usb_split;
+ enum phy_mode mode;
+};
+
+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
+{
+ unsigned int phy_mode, width, usb3_phy, ss_mode, split;
+
+ /* default is PCIe mode */
+ if (!data->stg_syscon || !data->sys_syscon) {
+ if (usb_mode) {
+ dev_err(data->phy->dev, "doesn't support USB3 mode\n");
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ if (usb_mode) {
+ phy_mode = PCIE_USB3_PHY_MODE;
+ width = 0;
+ usb3_phy = PCIE_USB3_PHY_ENABLE;
+ ss_mode = PCIE_USB3_PHY_SS_MODE;
+ split = 0;
+ } else {
+ phy_mode = 0;
+ width = PCIE_BUS_WIDTH;
+ usb3_phy = 0;
+ ss_mode = 0;
+ split = PCIE_USB3_PHY_SPLIT;
+ }
+
+ regmap_field_write(data->phy_mode, phy_mode);
+ regmap_field_write(data->bus_width, width);
+ regmap_field_write(data->usb3_phy_en, usb3_phy);
+ clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
+ PCIE_USB3_PHY_SS_MODE, ss_mode);
+ regmap_field_write(data->usb_split, split);
+
+ return 0;
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_pcie_phy *pcie_phy = dev_get_priv(dev);
+ int ret;
+
+ if (mode == pcie_phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ ret = phy_pcie_mode_set(pcie_phy, 1);
+ if (ret)
+ return ret;
+ break;
+ case PHY_MODE_PCIE:
+ phy_pcie_mode_set(pcie_phy, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_dbg(phy->dev, "Changing PHY mode to %d\n", mode);
+ pcie_phy->mode = mode;
+
+ return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+ .set_mode = jh7110_pcie_phy_set_mode,
+};
+
+static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct reg_field phy_mode = REG_FIELD(mode, 20, 21);
+ struct reg_field bus_width = REG_FIELD(usb3, 2, 3);
+ struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4);
+
+ phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode);
+ if (IS_ERR(phy->phy_mode)) {
+ dev_err(dev, "PHY mode reg field init failed\n");
+ return PTR_ERR(phy->phy_mode);
+ }
+
+ phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width);
+ if (IS_ERR(phy->bus_width)) {
+ dev_err(dev, "PHY bus width reg field init failed\n");
+ return PTR_ERR(phy->bus_width);
+ }
+
+ phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en);
+ if (IS_ERR(phy->usb3_phy_en)) {
+ dev_err(dev, "USB3 PHY enable field init failed\n");
+ return PTR_ERR(phy->bus_width);
+ }
+
+ return 0;
+}
+
+static int phy_sys_regfield_init(struct udevice *dev, int split)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct reg_field usb_split = REG_FIELD(split, USB_PDRSTN_SPLIT_BIT, USB_PDRSTN_SPLIT_BIT);
+
+ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+ if (IS_ERR(phy->usb_split)) {
+ dev_err(dev, "USB split field init failed\n");
+ return PTR_ERR(phy->usb_split);
+ }
+
+ return 0;
+}
+
+static int starfive_pcie_phy_get_syscon(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ struct ofnode_phandle_args sys_phandle, stg_phandle;
+ int ret;
+
+ /* get corresponding syscon phandle */
+ ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,
+ &sys_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,
+ &stg_phandle);
+
+ if (ret < 0) {
+ dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
+ /* get syscon register offset */
+ if (!IS_ERR(phy->sys_syscon)) {
+ ret = phy_sys_regfield_init(dev, SYSCON_USB_PDRSTN_REG_OFFSET);
+ if (ret)
+ return ret;
+ } else {
+ phy->sys_syscon = NULL;
+ }
+
+ phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
+ if (!IS_ERR(phy->stg_syscon))
+ return phy_stg_regfield_init(dev, stg_phandle.args[0],
+ stg_phandle.args[1]);
+ else
+ phy->stg_syscon = NULL;
+
+ return 0;
+}
+
+int jh7110_pcie_phy_probe(struct udevice *dev)
+{
+ struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+ int rc;
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ rc = starfive_pcie_phy_get_syscon(dev);
+ if (rc)
+ return rc;
+
+ phy_kvco_gain_set(phy);
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_pcie_phy[] = {
+ { .compatible = "starfive,jh7110-pcie-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_pcie_phy) = {
+ .name = "jh7110_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_pcie_phy,
+ .probe = jh7110_pcie_phy_probe,
+ .ops = &jh7110_pcie_phy_ops,
+ .priv_auto = sizeof(struct jh7110_pcie_phy),
+};
diff --git a/drivers/phy/starfive/phy-jh7110-usb-syscon.h b/drivers/phy/starfive/phy-jh7110-usb-syscon.h
new file mode 100644
index 0000000..0eb66f0
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb-syscon.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef PHY_JH7110_USB_SYSCON_H_
+#define PHY_JH7110_USB_SYSCON_H_
+
+#define SYSCON_USB_PDRSTN_REG_OFFSET 0x18
+#define USB_PDRSTN_SPLIT_BIT 17
+
+#endif
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 0000000..1a28381
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include "phy-jh7110-usb-syscon.h"
+
+#define USB_LS_KEEPALIVE_OFF 0x4
+#define USB_LS_KEEPALIVE_ENABLE BIT(4)
+#define USB_PHY_CLK_RATE 125000000
+
+struct jh7110_usb2_phy {
+ struct phy *phy;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ struct clk *usb_125m_clk;
+ struct clk *app_125m;
+ struct regmap_field *usb_split;
+ enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+ /* Host mode enable the LS speed keep-alive signal */
+ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+ USB_LS_KEEPALIVE_ENABLE,
+ set ? USB_LS_KEEPALIVE_ENABLE : 0);
+}
+
+static int usb2_phy_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+
+ if (mode == usb2_phy->mode)
+ return 0;
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ dev_dbg(dev, "Changing PHY to %d\n", mode);
+ usb2_phy->mode = mode;
+ usb2_set_ls_keepalive(usb2_phy, (mode != PHY_MODE_USB_DEVICE));
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* set default split usb 2.0 only mode */
+ regmap_field_write(usb2_phy->usb_split, true);
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_set_rate(usb2_phy->usb_125m_clk, USB_PHY_CLK_RATE);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set 125m clock\n");
+ return ret;
+ }
+
+ return clk_prepare_enable(usb2_phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+
+ clk_disable_unprepare(usb2_phy->app_125m);
+
+ return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+ struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+ ofnode node;
+ struct reg_field usb_split;
+ int ret;
+
+ phy->regs = dev_read_addr_ptr(dev);
+ if (!phy->regs)
+ return -EINVAL;
+
+ node = ofnode_by_compatible(ofnode_null(), "starfive,jh7110-sys-syscon");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "Can't get syscon dev node\n");
+ return -ENODEV;
+ }
+
+ phy->sys_syscon = syscon_node_to_regmap(node);
+ if (IS_ERR(phy->sys_syscon)) {
+ dev_err(dev, "Can't get syscon regmap: %d\n", ret);
+ return PTR_ERR(phy->sys_syscon);
+ }
+
+ usb_split.reg = SYSCON_USB_PDRSTN_REG_OFFSET;
+ usb_split.lsb = USB_PDRSTN_SPLIT_BIT;
+ usb_split.msb = USB_PDRSTN_SPLIT_BIT;
+ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+ if (IS_ERR(phy->usb_split)) {
+ dev_err(dev, "USB split field init failed\n");
+ return PTR_ERR(phy->usb_split);
+ }
+
+ phy->usb_125m_clk = devm_clk_get(dev, "125m");
+ if (IS_ERR(phy->usb_125m_clk)) {
+ dev_err(dev, "Failed to get 125m clock\n");
+ return PTR_ERR(phy->usb_125m_clk);
+ }
+
+ phy->app_125m = devm_clk_get(dev, "app_125m");
+ if (IS_ERR(phy->app_125m)) {
+ dev_err(dev, "Failed to get app 125m clock\n");
+ return PTR_ERR(phy->app_125m);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id jh7110_usb2_phy[] = {
+ { .compatible = "starfive,jh7110-usb-phy"},
+ {},
+};
+
+U_BOOT_DRIVER(jh7110_usb2_phy) = {
+ .name = "jh7110_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = jh7110_usb2_phy,
+ .probe = jh7110_usb2_phy_probe,
+ .ops = &jh7110_usb2_phy_ops,
+ .priv_auto = sizeof(struct jh7110_usb2_phy),
+};
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d3eb699..f4a3942 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -7,84 +7,98 @@
menu "Qualcomm pinctrl drivers"
config PINCTRL_QCOM_APQ8016
- bool "Qualcomm APQ8016 GCC"
+ bool "Qualcomm APQ8016 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the MSM8916 / APQ8016
Snapdragon 410 SoC, as well as the associated GPIO driver.
config PINCTRL_QCOM_APQ8096
- bool "Qualcomm APQ8096 GCC"
+ bool "Qualcomm APQ8096 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
Snapdragon 820 SoC, as well as the associated GPIO driver.
config PINCTRL_QCOM_IPQ4019
- bool "Qualcomm IPQ4019 GCC"
+ bool "Qualcomm IPQ4019 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the IPQ4019 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_IPQ9574
+ bool "Qualcomm IPQ9574 Pinctrl"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the IPQ9574 SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_QCM2290
- bool "Qualcomm QCM2290 GCC"
+ bool "Qualcomm QCM2290 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_QCS404
- bool "Qualcomm QCS404 GCC"
+ bool "Qualcomm QCS404 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SC7280
+ bool "Qualcomm SC7280/QCM6490 Pinctrl"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SC7280 SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_SDM845
- bool "Qualcomm SDM845 GCC"
+ bool "Qualcomm SDM845 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_SM6115
- bool "Qualcomm SM6115 GCC"
+ bool "Qualcomm SM6115 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_SM8150
- bool "Qualcomm SM8150 GCC"
+ bool "Qualcomm SM8150 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_SM8250
- bool "Qualcomm SM8250 GCC"
+ bool "Qualcomm SM8250 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_SM8550
- bool "Qualcomm SM8550 GCC"
+ bool "Qualcomm SM8550 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_SM8650
- bool "Qualcomm SM8650 GCC"
+ bool "Qualcomm SM8650 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_X1E80100
- bool "Qualcomm X1E80100 GCC"
+ bool "Qualcomm X1E80100 Pinctrl"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC,
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06d3c95..94cdc6e 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,9 +5,11 @@
obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 0c74378..9ae07d4 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -50,8 +50,8 @@
}
}
-static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int apq8016_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 132ece8..eaa927c 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -43,8 +43,8 @@
}
}
-static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int apq8096_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 3215c67..dafcd49 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -311,8 +311,7 @@
return pin_name;
}
-static unsigned int ipq4019_get_function_mux(unsigned int pin,
- unsigned int selector)
+static int ipq4019_get_function_mux(unsigned int pin, unsigned int selector)
{
unsigned int i;
const msm_pin_function *func = ipq4019_pin_functions + pin;
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
new file mode 100644
index 0000000..ce09072
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pinctrl driver for Qualcomm ipq9574
+ *
+ * (C) Copyright 2025 Linaro Ltd.
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum ipq9574_functions {
+ msm_mux_blsp0_spi,
+ msm_mux_blsp0_uart,
+ msm_mux_blsp1_i2c,
+ msm_mux_blsp1_spi,
+ msm_mux_blsp1_uart,
+ msm_mux_blsp2_i2c,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp2_uart,
+ msm_mux_blsp3_i2c,
+ msm_mux_blsp3_spi,
+ msm_mux_blsp3_uart,
+ msm_mux_blsp4_i2c,
+ msm_mux_blsp4_spi,
+ msm_mux_blsp4_uart,
+ msm_mux_blsp5_i2c,
+ msm_mux_blsp5_uart,
+ msm_mux_gpio,
+ msm_mux_mdc,
+ msm_mux_mdio,
+ msm_mux_pcie0_clk,
+ msm_mux_pcie0_wake,
+ msm_mux_pcie1_clk,
+ msm_mux_pcie1_wake,
+ msm_mux_pcie2_clk,
+ msm_mux_pcie2_wake,
+ msm_mux_pcie3_clk,
+ msm_mux_pcie3_wake,
+ msm_mux_qspi_data,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_sdc_data,
+ msm_mux_sdc_clk,
+ msm_mux_sdc_cmd,
+ msm_mux_sdc_rclk,
+ msm_mux_NA,
+};
+
+#define MSM_PIN_FUNCTION(fname) \
+ [msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ MSM_PIN_FUNCTION(blsp0_spi),
+ MSM_PIN_FUNCTION(blsp0_uart),
+ MSM_PIN_FUNCTION(blsp1_i2c),
+ MSM_PIN_FUNCTION(blsp1_spi),
+ MSM_PIN_FUNCTION(blsp1_uart),
+ MSM_PIN_FUNCTION(blsp2_i2c),
+ MSM_PIN_FUNCTION(blsp2_spi),
+ MSM_PIN_FUNCTION(blsp2_uart),
+ MSM_PIN_FUNCTION(blsp3_i2c),
+ MSM_PIN_FUNCTION(blsp3_spi),
+ MSM_PIN_FUNCTION(blsp3_uart),
+ MSM_PIN_FUNCTION(blsp4_i2c),
+ MSM_PIN_FUNCTION(blsp4_spi),
+ MSM_PIN_FUNCTION(blsp4_uart),
+ MSM_PIN_FUNCTION(blsp5_i2c),
+ MSM_PIN_FUNCTION(blsp5_uart),
+ MSM_PIN_FUNCTION(gpio),
+ MSM_PIN_FUNCTION(mdc),
+ MSM_PIN_FUNCTION(mdio),
+ MSM_PIN_FUNCTION(pcie0_clk),
+ MSM_PIN_FUNCTION(pcie0_wake),
+ MSM_PIN_FUNCTION(pcie1_clk),
+ MSM_PIN_FUNCTION(pcie1_wake),
+ MSM_PIN_FUNCTION(pcie2_clk),
+ MSM_PIN_FUNCTION(pcie2_wake),
+ MSM_PIN_FUNCTION(pcie3_clk),
+ MSM_PIN_FUNCTION(pcie3_wake),
+ MSM_PIN_FUNCTION(qspi_data),
+ MSM_PIN_FUNCTION(qspi_clk),
+ MSM_PIN_FUNCTION(qspi_cs),
+ MSM_PIN_FUNCTION(sdc_data),
+ MSM_PIN_FUNCTION(sdc_clk),
+ MSM_PIN_FUNCTION(sdc_cmd),
+ MSM_PIN_FUNCTION(sdc_rclk),
+};
+
+typedef unsigned int msm_pin_function[10];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ [id] = { msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9, \
+ }
+
+static const msm_pin_function ipq9574_pin_functions[] = {
+ PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+ PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+ PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+ PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+ PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+ PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+ PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const char *ipq9574_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *ipq9574_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+ return pin_name;
+}
+
+static int ipq9574_get_function_mux(unsigned int pin, unsigned int selector)
+{
+ unsigned int i;
+ const msm_pin_function *func = ipq9574_pin_functions + pin;
+
+ for (i = 0; i < 10; i++)
+ if ((*func)[i] == selector)
+ return i;
+
+ debug("Can't find requested function for pin:selector %u:%u\n",
+ pin, selector);
+
+ return -EINVAL;
+}
+
+static const struct msm_pinctrl_data ipq9574_data = {
+ .pin_data = {
+ .pin_count = 65,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = ipq9574_get_function_name,
+ .get_function_mux = ipq9574_get_function_mux,
+ .get_pin_name = ipq9574_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
+ { /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_ipq9574) = {
+ .name = "pinctrl_ipq9574",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
index af969e1..0c2222c 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
@@ -38,7 +38,7 @@
return pin_name;
}
-static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 26a3fba..24d0319 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -92,7 +92,10 @@
unsigned int func_selector)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
- u32 func = priv->data->get_function_mux(pin_selector, func_selector);
+ int func = priv->data->get_function_mux(pin_selector, func_selector);
+
+ if (func < 0)
+ return func;
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
index 49b7bfb..cd167e6 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.h
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -18,8 +18,7 @@
int functions_count;
const char *(*get_function_name)(struct udevice *dev,
unsigned int selector);
- unsigned int (*get_function_mux)(unsigned int pin,
- unsigned int selector);
+ int (*get_function_mux)(unsigned int pin, unsigned int selector);
const char *(*get_pin_name)(struct udevice *dev,
unsigned int selector);
};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index fb6defa..c272595 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -93,8 +93,8 @@
}
}
-static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int qcs404_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c
new file mode 100644
index 0000000..fe87947
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sc7280 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define WEST 0x00000000
+#define SOUTH 0x00400000
+#define NORTH 0x00800000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ { "qup05", 1 },
+ { "gpio", 0 },
+ { "pcie1_clkreqn", 3},
+};
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ }
+
+static const struct msm_special_pin_data sc7280_special_pins_data[] = {
+ [0] = UFS_RESET("ufs_reset", SOUTH + 0xbe000),
+ [1] = SDC_PINGROUP("sdc1_rclk", 0xb3004, 0, 6),
+ [2] = SDC_PINGROUP("sdc1_clk", 0xb3000, 13, 6),
+ [3] = SDC_PINGROUP("sdc1_cmd", 0xb3000, 11, 3),
+ [4] = SDC_PINGROUP("sdc1_data", 0xb3000, 9, 0),
+ [5] = SDC_PINGROUP("sdc2_clk", 0xb4000, 14, 6),
+ [6] = SDC_PINGROUP("sdc2_cmd", 0xb4000, 11, 3),
+ [7] = SDC_PINGROUP("sdc2_data", 0xb4000, 9, 0),
+};
+
+static const char *sc7280_get_function_name(struct udevice *dev, unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sc7280_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ if (selector >= 175 && selector <= 182)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
+ sc7280_special_pins_data[selector - 175].name);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static int sc7280_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sc7280_data = {
+ .pin_data = {
+ .pin_count = 183,
+ .special_pins_start = 175,
+ .special_pins_data = sc7280_special_pins_data,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sc7280_get_function_name,
+ .get_function_mux = sc7280_get_function_mux,
+ .get_pin_name = sc7280_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ {
+ .compatible = "qcom,sc7280-pinctrl",
+ .data = (ulong)&sc7280_data
+ },
+ { /* Sentinel */ } };
+
+U_BOOT_DRIVER(pinctrl_sc7280) = {
+ .name = "pinctrl_sc7280",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index f1a23f5..3f55fc8 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -80,8 +80,8 @@
return pin_name;
}
-static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int sdm845_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c
index f07f39f..7e80ea3 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c
@@ -167,7 +167,7 @@
return pin_name;
}
-static unsigned int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
index 1fb2ffb..fe789e8 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
@@ -123,8 +123,8 @@
return pin_name;
}
-static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int sm8150_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c
index b21cdc4..d544765 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c
@@ -99,7 +99,7 @@
return pin_name;
}
-static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c
index 25b972a..f7fcad0 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -68,8 +68,8 @@
return pin_name;
}
-static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int sm8550_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c
index 9146d6a..6b9d56b 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@ -69,8 +69,8 @@
return pin_name;
}
-static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int sm8650_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c
index f39dc42..319667b 100644
--- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c
+++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c
@@ -72,8 +72,8 @@
return pin_name;
}
-static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
- unsigned int selector)
+static int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index cbd6179..65e8192 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,6 +124,16 @@
default MACH_SUN50I_H616
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_A100
+ bool "Support for the Allwinner A100/A133 PIO"
+ default MACH_SUN50I_A133
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+ bool "Support for the Allwinner A100/A133 R-PIO"
+ default MACH_SUN50I_A133
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN20I_D1
bool "Support for the Allwinner D1/R528 PIO"
default MACH_SUN8I_R528
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 37ea937..c38edf7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -774,6 +774,41 @@
.num_banks = 1,
};
+static const struct sunxi_pinctrl_function sun50i_a100_pinctrl_functions[] = {
+ { "emac0", 5 }, /* PH0-PH16 */
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 }, /* PF0-PF5 */
+ { "mmc1", 2 }, /* PG0-PG5 */
+ { "mmc2", 3 }, /* PC0-PC16 */
+ { "spi0", 4 }, /* PC2-PC4, PC7, PC12, PC15-PC16 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+ { "uart0", 3 }, /* PF2-PF4 */
+#else
+ { "uart0", 2 }, /* PB9-PB10 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_pinctrl_desc = {
+ .functions = sun50i_a100_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_a100_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_A,
+ .num_banks = 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a100_r_pinctrl_functions[] = {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "s_i2c0", 2 },
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc = {
+ .functions = sun50i_a100_r_pinctrl_functions,
+ .num_functions = ARRAY_SIZE(sun50i_a100_r_pinctrl_functions),
+ .first_bank = SUNXI_GPIO_L,
+ .num_banks = 1,
+};
+
static const struct udevice_id sunxi_pinctrl_ids[] = {
#ifdef CONFIG_PINCTRL_SUNIV_F1C100S
{
@@ -937,6 +972,18 @@
.data = (ulong)&sun50i_h616_r_pinctrl_desc,
},
#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100
+ {
+ .compatible = "allwinner,sun50i-a100-pinctrl",
+ .data = (ulong)&sun50i_a100_pinctrl_desc,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100_R
+ {
+ .compatible = "allwinner,sun50i-a100-r-pinctrl",
+ .data = (ulong)&sun50i_a100_r_pinctrl_desc,
+ },
+#endif
{}
};
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index e6b957f..b04be16 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -23,18 +23,18 @@
return;
}
- drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
- drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
- drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
- drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
+ drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", PMUX_SLWF_NONE);
+ drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", PMUX_SLWR_NONE);
+ drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", PMUX_DRVUP_NONE);
+ drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", PMUX_DRVDN_NONE);
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
- drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
+ drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", PMUX_LPMD_NONE);
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
- drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+ drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
- drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+ drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
#endif
for (i = 1; i < drvcnt; i++)
@@ -142,31 +142,31 @@
pinmux_group[0].func = i;
- pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
- pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
+ pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL);
+ pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", PMUX_TRI_TRISTATE);
#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
- pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
+ pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", PMUX_PIN_NONE);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
- pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
+ pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", PMUX_PIN_LOCK_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
- pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
+ pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", PMUX_PIN_OD_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
- pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
+ pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", PMUX_PIN_IO_RESET_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
- pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
+ pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", PMUX_PIN_RCV_SEL_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
- pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
+ pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", PMUX_PIN_E_IO_HV_DEFAULT);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
- pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+ pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
#endif
#ifdef TEGRA_PMX_PINS_HAVE_HSM
- pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+ pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
#endif
for (i = 1; i < pincnt; i++)
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 4b81aeb..eed6505 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -116,6 +116,12 @@
---help---
Select this to enable support for the AXP717 PMIC found on some boards.
+config AXP803_POWER
+ bool "AXP803 PMIC support"
+ select AXP_PMIC_BUS
+ ---help---
+ Select this to enable support for the AXP803 PMIC found on some boards.
+
config AXP809_POWER
bool "axp809 pmic support"
depends on MACH_SUN9I
@@ -142,10 +148,20 @@
endchoice
+config AXP_I2C_ADDRESS
+ hex "AXP PMIC I2C address"
+ depends on ARCH_SUNXI && !SUNXI_NO_PMIC
+ default 0x36 if AXP305_POWER
+ default 0x36 if AXP313_POWER
+ default 0x30 if AXP152_POWER
+ default 0x34
+ ---help---
+ I2C address of the AXP PMIC, used for the SPL only.
+
config AXP_DCDC1_VOLT
int "axp pmic dcdc1 voltage"
- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
- default 3300 if AXP818_POWER || MACH_SUN8I_R40
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER
+ default 3300 if AXP818_POWER || MACH_SUN8I_R40 || AXP803_POWER
default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
@@ -158,11 +174,12 @@
config AXP_DCDC2_VOLT
int "axp pmic dcdc2 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER || AXP803_POWER
default 900 if AXP818_POWER
default 1400 if AXP152_POWER || AXP209_POWER
default 1000 if AXP313_POWER
default 1000 if AXP717_POWER
+ default 1000 if AXP803_POWER
default 1200 if MACH_SUN6I
default 1100 if MACH_SUN8I
default 0 if MACH_SUN9I
@@ -219,7 +236,7 @@
config AXP_DCDC5_VOLT
int "axp pmic dcdc5 voltage"
- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+ depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER
default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
---help---
Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 3f4d56f..3363191 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -17,6 +17,7 @@
obj-$(CONFIG_AXP717_POWER) += axp_spl.o
obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
+obj-$(CONFIG_AXP803_POWER) += axp_spl.o
endif
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_SY8106A_POWER) += sy8106a.o
diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c
index 3c86eb2..7c51a9b 100644
--- a/drivers/power/axp_spl.c
+++ b/drivers/power/axp_spl.c
@@ -36,6 +36,23 @@
#define AXP_SHUTDOWN_REG 0x27
#define AXP_SHUTDOWN_MASK BIT(0)
+#elif defined(CONFIG_AXP803_POWER) /* AXP803 */
+
+static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
+ { 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
+ { 0x10, BIT(1), 0x21, 0x7f, 500, 1300, 10, 70 },
+ { 0x10, BIT(2), 0x22, 0x7f, 500, 1300, 10, 70 },
+ { 0x10, BIT(3), 0x23, 0x7f, 500, 1300, 10, 70 },
+ { 0x10, BIT(4), 0x24, 0x7f, 800, 1840, 10, 32 },
+ { 0x10, BIT(5), 0x25, 0x7f, 600, 1520, 10, 50 },
+};
+
+#define AXP_CHIP_VERSION 0x3
+#define AXP_CHIP_VERSION_MASK 0xcf
+#define AXP_CHIP_ID 0x41
+#define AXP_SHUTDOWN_REG 0x32
+#define AXP_SHUTDOWN_MASK BIT(7)
+
#elif defined(CONFIG_AXP313_POWER) /* AXP313 */
static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 958f337..8f102a9 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -478,3 +478,11 @@
features for REGULATOR TPS65219 and the family of TPS65219 PMICs.
TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs.
The driver implements get/set api for value and enable.
+
+config REGULATOR_RZG2L_USBPHY
+ bool "Enable driver for RZ/G2L USB PHY VBUS supply"
+ depends on DM_REGULATOR
+ help
+ Enable this option to support controlling the VBUS supply in
+ the USB PHY peripheral of the Renesas RZ/G2L SoC. This option
+ is required in order to use the USB OTG port.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index ca6c89d..4382d4b 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -42,3 +42,4 @@
obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o
obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o
+obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o
diff --git a/drivers/power/regulator/rzg2l-usbphy-regulator.c b/drivers/power/regulator/rzg2l-usbphy-regulator.c
new file mode 100644
index 0000000..451f04c
--- /dev/null
+++ b/drivers/power/regulator/rzg2l-usbphy-regulator.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <power/regulator.h>
+#include <renesas/rzg2l-usbphy.h>
+
+#define VBENCTL 0x03c
+#define VBENCTL_VBUS_SEL BIT(0)
+
+static int rzg2l_usbphy_regulator_set_enable(struct udevice *dev, bool enable)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+ if (enable)
+ clrbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+ else
+ setbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_regulator_get_enable(struct udevice *dev)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+ return !!readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL;
+}
+
+static const struct dm_regulator_ops rzg2l_usbphy_regulator_ops = {
+ .get_enable = rzg2l_usbphy_regulator_get_enable,
+ .set_enable = rzg2l_usbphy_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(rzg2l_usbphy_regulator) = {
+ .name = "rzg2l_usbphy_regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &rzg2l_usbphy_regulator_ops,
+};
diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 5cf2eba..898e353 100644
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -30,6 +30,7 @@
enum mtk_pwm_reg_ver {
PWM_REG_V1,
PWM_REG_V2,
+ PWM_REG_V3,
};
static const unsigned int mtk_pwm_reg_offset_v1[] = {
@@ -40,6 +41,10 @@
0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
};
+static const unsigned int mtk_pwm_reg_offset_v3[] = {
+ 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800
+};
+
struct mtk_pwm_soc {
unsigned int num_pwms;
bool pwm45_fixup;
@@ -60,6 +65,10 @@
u32 offset;
switch (priv->soc->reg_ver) {
+ case PWM_REG_V3:
+ offset = mtk_pwm_reg_offset_v3[channel];
+ break;
+
case PWM_REG_V2:
offset = mtk_pwm_reg_offset_v2[channel];
break;
@@ -203,6 +212,12 @@
.reg_ver = PWM_REG_V1,
};
+static const struct mtk_pwm_soc mt7987_data = {
+ .num_pwms = 3,
+ .pwm45_fixup = false,
+ .reg_ver = PWM_REG_V3,
+};
+
static const struct mtk_pwm_soc mt7988_data = {
.num_pwms = 8,
.pwm45_fixup = false,
@@ -215,6 +230,7 @@
{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+ { .compatible = "mediatek,mt7987-pwm", .data = (ulong)&mt7987_data },
{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
{ }
};
diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c
index d24b7c5..4cbc6ae 100644
--- a/drivers/ram/renesas/dbsc5/dbsc5.c
+++ b/drivers/ram/renesas/dbsc5/dbsc5.c
@@ -59,7 +59,8 @@
struct renesas_dbsc5_data r8a779g0_dbsc5_data = {
.clock_node = "renesas,r8a779g0-cpg-mssr",
- .reset_node = "renesas,r8a779g0-rst"
+ .reset_node = "renesas,r8a779g0-rst",
+ .otp_node = "renesas,r8a779g0-otp",
};
static const struct udevice_id renesas_dbsc5_ids[] = {
diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h
index c410eb0..bf22fcb 100644
--- a/drivers/ram/renesas/dbsc5/dbsc5.h
+++ b/drivers/ram/renesas/dbsc5/dbsc5.h
@@ -23,6 +23,7 @@
struct renesas_dbsc5_data {
const char *clock_node;
const char *reset_node;
+ const char *otp_node;
};
#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */
diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 210a68f..ca8a7fb 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -4,6 +4,7 @@
*/
#include <asm/io.h>
+#include <dbsc5.h>
#include <dm.h>
#include <errno.h>
#include <hang.h>
@@ -12,13 +13,6 @@
#include <linux/sizes.h>
#include "dbsc5.h"
-/* The number of channels V4H has */
-#define DRAM_CH_CNT 4
-/* The number of slices V4H has */
-#define SLICE_CNT 2
-/* The number of chip select V4H has */
-#define CS_CNT 2
-
/* Number of array elements in Data Slice */
#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100
/* Number of array elements in Data Slice */
@@ -220,6 +214,7 @@
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F)
#define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043)
#define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D)
+#define PHY_SLV_DLY_CTRL_GATE_DISABLE DDR_REGDEF(0x10, 0x01, 0x104E)
#define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050)
#define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055)
#define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055)
@@ -469,7 +464,7 @@
0x00000000, 0x00500050, 0x00500050, 0x00500050,
0x00500050, 0x0D000050, 0x10100004, 0x06102010,
0x61619041, 0x07097000, 0x00644180, 0x00803280,
- 0x00808001, 0x13010100, 0x02000016, 0x10001003,
+ 0x00808001, 0x13010101, 0x02000016, 0x10001003,
0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140,
0x00000100, 0x000001D1, 0x05000068, 0x00030402,
0x01400000, 0x80800300, 0x00160010, 0x76543210,
@@ -512,8 +507,8 @@
0x00040101, 0x00000000, 0x00000000, 0x00000064,
0x00000000, 0x00000000, 0x39421B42, 0x00010124,
0x00520052, 0x00000052, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x07030102,
+ 0x00010001, 0x00000000, 0x00000000, 0x00010001,
+ 0x00000000, 0x00000000, 0x00010001, 0x07030102,
0x01030307, 0x00000054, 0x00004096, 0x08200820,
0x08200820, 0x08200820, 0x08200820, 0x00000820,
0x004103B8, 0x0000003F, 0x000C0006, 0x00000000,
@@ -1294,7 +1289,7 @@
};
static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = {
- PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03
+ PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02
};
static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = {
@@ -1330,6 +1325,11 @@
#define DBSC_DBACEN 0x200
#define DBSC_DBRFEN 0x204
#define DBSC_DBCMD 0x208
+#define DBSC_DBCMD_CMD_OPCODE_PD 0x8
+#define DBSC_DBCMD_CMD_OPCODE_MRW 0xe
+#define DBSC_DBCMD_CMD_OPCODE_MRR 0xf
+#define DBSC_DBCMD_CMD_CHANNEL_ALL 0x8
+#define DBSC_DBCMD_CMD_RANK_ALL 0x4
#define DBSC_DBWAIT 0x210
#define DBSC_DBBL 0x400
#define DBSC_DBBLA 0x400
@@ -1374,46 +1374,6 @@
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
-struct renesas_dbsc5_board_config {
- /* Channels in use */
- u8 bdcfg_phyvalid;
- /* Read vref (SoC) training range */
- u32 bdcfg_vref_r;
- /* Write vref (MR14, MR15) training range */
- u16 bdcfg_vref_w;
- /* CA vref (MR12) training range */
- u16 bdcfg_vref_ca;
- /* RFM required check */
- bool bdcfg_rfm_chk;
-
- /* Board parameter about channels */
- struct {
- /*
- * 0x00: 4Gb dual channel die / 2Gb single channel die
- * 0x01: 6Gb dual channel die / 3Gb single channel die
- * 0x02: 8Gb dual channel die / 4Gb single channel die
- * 0x03: 12Gb dual channel die / 6Gb single channel die
- * 0x04: 16Gb dual channel die / 8Gb single channel die
- * 0x05: 24Gb dual channel die / 12Gb single channel die
- * 0x06: 32Gb dual channel die / 16Gb single channel die
- * 0x07: 24Gb single channel die
- * 0x08: 32Gb single channel die
- * 0xFF: NO_MEMORY
- */
- u8 bdcfg_ddr_density[CS_CNT];
- /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
- u32 bdcfg_ca_swap;
- /* SoC dqsX([1][0]) -> MEM dqsY: */
- u8 bdcfg_dqs_swap;
- /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
- u32 bdcfg_dq_swap[SLICE_CNT];
- /* SoC dm -> MEM dqY/dm: (8 means DM) */
- u8 bdcfg_dm_swap[SLICE_CNT];
- /* SoC ckeX([1][0]) -> MEM csY */
- u8 bdcfg_cs_swap;
- } ch[4];
-};
-
struct renesas_dbsc5_dram_priv {
void __iomem *regs;
void __iomem *cpg_regs;
@@ -1713,14 +1673,17 @@
{
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
- u32 i, ch, reg;
+ u32 i, ch, chk, reg;
for (i = 0; i < 2; i++) {
do {
reg = status;
- r_foreach_vch(dev, ch)
+ chk = 0;
+ r_foreach_vch(dev, ch) {
reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch));
- } while (reg != status);
+ chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch));
+ }
+ } while (reg != status && !(chk & BIT(0)));
}
}
@@ -1778,24 +1741,20 @@
}
/**
- * dbsc5_reg_write() - DRAM Command Write Access
+ * dbsc5_wait_dbwait() - DRAM Command Wait Access Completion
* @dev: DBSC5 device
- * @cmd DRAM command.
*
- * First, execute the dummy read to DBSC_DBCMD.
- * Confirm that no DBSC command operation is in progress 0.
- * Write the contents of the command to be sent to DRAM.
+ * Wait for DRAM access completion. This is used before sending a command
+ * to the DRAM to assure no other command is in flight already, or while
+ * waiting for MRR command to complete.
*/
-static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd)
+static void dbsc5_wait_dbwait(struct udevice *dev)
{
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
u32 val;
int ret;
- /* dummy read */
- readl(regs_dbsc_d + DBSC_DBCMD);
-
ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000);
if (ret < 0) {
printf("%s DBWAIT bit 0 timeout\n", __func__);
@@ -1807,6 +1766,32 @@
printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__);
hang();
}
+}
+
+/**
+ * dbsc5_send_dbcmd2() - DRAM Command Write Access
+ * @dev: DBSC5 device
+ * @opcode DRAM controller opcode
+ * @channel DRAM controller channel (0..3)
+ * @rank DRAM controller rank (0..1)
+ * @arg Command and argument bits (command specific encoding)
+ *
+ * First, execute the dummy read to DBSC_DBCMD.
+ * Confirm that no DBSC command operation is in progress 0.
+ * Write the contents of the command to be sent to DRAM.
+ */
+static void dbsc5_send_dbcmd2(struct udevice *dev, const u8 opcode,
+ const u8 channel, const u8 rank,
+ const u16 arg)
+{
+ const u32 cmd = (opcode << 24) | (channel << 20) | (rank << 16) | arg;
+ struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
+ void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
+
+ /* dummy read */
+ readl(regs_dbsc_d + DBSC_DBCMD);
+
+ dbsc5_wait_dbwait(dev);
dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd);
}
@@ -2192,7 +2177,7 @@
if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3)
break;
- priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI);
+ priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI);
priv->RL = js1[priv->js1_ind].RLset1;
priv->WL = js1[priv->js1_ind].WLsetA;
@@ -2635,7 +2620,7 @@
*/
dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11),
priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] -
- js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]);
+ js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2);
/* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */
dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12),
@@ -2992,10 +2977,14 @@
writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch));
/* Dummy PDE */
- dbsc5_send_dbcmd2(dev, 0x8840000);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD,
+ DBSC_DBCMD_CMD_CHANNEL_ALL,
+ DBSC_DBCMD_CMD_RANK_ALL, 0);
/* PDX */
- dbsc5_send_dbcmd2(dev, 0x8840001);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD,
+ DBSC_DBCMD_CMD_CHANNEL_ALL,
+ DBSC_DBCMD_CMD_RANK_ALL, 1);
/* Wait init_complete */
for (retry = 0; retry < retry_max; retry++) {
@@ -3491,13 +3480,10 @@
{
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1;
- u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
- u32 slv_dly_center_cyc;
- u32 slv_dly_center_dly;
+ u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+ u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT];
u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT];
u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT];
- u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
- u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT];
u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT];
u32 phy_dcc_code_mid;
@@ -3521,18 +3507,9 @@
dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs);
r_foreach_vch(dev, ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
- slv_dly_center[ch][cs][slice] =
- dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY);
- slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180;
- slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F;
- slv_dly_min_tmp[ch][cs][slice] =
- slv_dly_center_cyc |
- (slv_dly_center_dly * ratio_min / ratio_min_div);
- slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc;
- if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div))
- slv_dly_max_tmp[ch][cs][slice] |= 0x7F;
- else
- slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div;
+ phy_slv_dly[ch][cs][slice] =
+ dbsc5_ddr_getval_slice(dev, ch, slice,
+ PHY_CLK_WRDQS_SLAVE_DELAY);
}
}
}
@@ -3540,22 +3517,22 @@
r_foreach_vch(dev, ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
if (rank == 0x2) {
- if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice])
- slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice];
- else
- slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
-
- if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice])
- slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
- else
- slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice];
+ /* Calculate average between ranks */
+ phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] +
+ phy_slv_dly[ch][1][slice]) / 2;
} else {
- slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
- slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
+ phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice];
}
+ /* Determine the search range */
+ slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div;
+ slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div;
+ if (slv_dly_max[ch][slice] > 0x7F)
+ slv_dly_max[ch][slice] = 0x7F;
}
}
+ dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1);
+
for (i = 0; i <= 0x7F; i++) {
r_foreach_vch(dev, ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3621,13 +3598,16 @@
for (slice = 0; slice < SLICE_CNT; slice++) {
dbsc5_ddr_setval_slice(dev, ch, slice,
PHY_CLK_WRDQS_SLAVE_DELAY,
- slv_dly_center[ch][cs][slice]);
+ phy_slv_dly[ch][cs][slice]);
dbsc5_ddr_setval_slice(dev, ch, slice,
SC_PHY_WCK_CALC, 0x1);
dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1);
}
}
}
+
+ dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0);
+
dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1);
r_foreach_vch(dev, ch) {
@@ -4136,25 +4116,27 @@
}
/**
- * dbsc5_ddr_register_set() - DDR mode register setting
+ * dbsc5_ddr_register_mr28_set() - DDR mode register MR28 set
* @dev: DBSC5 device
*
* Set the mode register 28 of the SDRAM.
* ZQ Mode: Command-Based ZQ Calibration
* ZQ interval: Background Cal Interval < 64ms
*/
-static void dbsc5_ddr_register_set(struct udevice *dev)
+static void dbsc5_ddr_register_mr28_set(struct udevice *dev)
{
- dbsc5_send_dbcmd2(dev, 0xE841C24);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRW,
+ DBSC_DBCMD_CMD_CHANNEL_ALL,
+ DBSC_DBCMD_CMD_RANK_ALL, (28 << 8) | 0x24);
}
/**
- * dbsc5_ddr_register_read() - DDR mode register read
+ * dbsc5_ddr_register_mr27_mr57_read() - DDR mode register MR27/MR57 read
* @dev: DBSC5 device
*
* Set the mode register 27 and 57 of the SDRAM.
*/
-static void dbsc5_ddr_register_read(struct udevice *dev)
+static void dbsc5_ddr_register_mr27_mr57_read(struct udevice *dev)
{
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
@@ -4162,17 +4144,21 @@
return;
/* MR27 rank0 */
- dbsc5_send_dbcmd2(dev, 0xF801B00);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+ DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 27 << 8);
/* MR57 rank0 */
- dbsc5_send_dbcmd2(dev, 0xF803900);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+ DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 57 << 8);
if (!priv->ch_have_this_cs[1])
return;
/* MR27 rank1 */
- dbsc5_send_dbcmd2(dev, 0xF811B00);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+ DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 27 << 8);
/* MR57 rank1 */
- dbsc5_send_dbcmd2(dev, 0xF813900);
+ dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+ DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 57 << 8);
}
/**
@@ -4251,8 +4237,8 @@
dbsc5_dbsc_regset(dev);
/* Frequency selection change (F1->F2) */
- dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1);
- dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0);
+ dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1);
+ dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0);
/* dfi_init_start (start ddrphy) & execute pi_training */
phytrainingok = dbsc5_pi_training(dev);
@@ -4329,10 +4315,10 @@
/* setup DDR mode registers */
/* MRS */
- dbsc5_ddr_register_set(dev);
+ dbsc5_ddr_register_mr28_set(dev);
/* MRR */
- dbsc5_ddr_register_read(dev);
+ dbsc5_ddr_register_mr27_mr57_read(dev);
/* training complete, setup DBSC */
dbsc5_dbsc_regset_post(dev);
@@ -4347,10 +4333,13 @@
/**
* dbsc5_get_board_data() - Obtain board specific DRAM configuration
+ * @dev: DBSC5 device
+ * @modemr0: MODEMR0 register content
*
* Return board specific DRAM configuration structure pointer.
*/
-__weak const struct renesas_dbsc5_board_config *dbsc5_get_board_data(void)
+__weak const struct renesas_dbsc5_board_config *
+dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
{
return &renesas_v4h_dbsc5_board_config;
}
@@ -4369,20 +4358,24 @@
{
#define RST_MODEMR0 0x0
#define RST_MODEMR1 0x4
+#define OTP_MONITOR17 0x1144
struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev);
ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node);
ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node);
+ ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node);
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET;
void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
phys_addr_t rregs = ofnode_get_addr(rnode);
const u32 modemr0 = readl(rregs + RST_MODEMR0);
const u32 modemr1 = readl(rregs + RST_MODEMR1);
- u32 breg, reg, md, sscg;
+ phys_addr_t oregs = ofnode_get_addr(onode);
+ const u32 otpmon17 = readl(oregs + OTP_MONITOR17);
+ u32 breg, reg, md, sscg, product;
u32 ch, cs;
/* Get board data */
- priv->dbsc5_board_config = dbsc5_get_board_data();
+ priv->dbsc5_board_config = dbsc5_get_board_data(dev, modemr0);
priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid);
priv->max_density = 0;
priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode);
@@ -4433,29 +4426,41 @@
/* Decode DDR operating frequency from MD[37:36,19,17] pins */
md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17);
+ product = otpmon17 & 0xff;
sscg = (modemr1 >> 4) & 0x03;
if (sscg == 2) {
printf("MD[37:36] setting 0x%x not supported!", sscg);
hang();
}
- if (md == 0) {
- if (sscg == 0) {
- priv->ddr_mbps = 6400;
- priv->ddr_mbpsdiv = 1;
- } else {
- priv->ddr_mbps = 19000;
- priv->ddr_mbpsdiv = 3;
- }
- } else if (md == 1) {
- priv->ddr_mbps = 6000;
- priv->ddr_mbpsdiv = 1;
- } else if (md == 1) {
- priv->ddr_mbps = 5500;
- priv->ddr_mbpsdiv = 1;
- } else if (md == 1) {
+ if (product == 0x2) { /* V4H-3 */
priv->ddr_mbps = 4800;
priv->ddr_mbpsdiv = 1;
+ } else if (product == 0x1) { /* V4H-5 */
+ if (md == 3)
+ priv->ddr_mbps = 4800;
+ else
+ priv->ddr_mbps = 5000;
+ priv->ddr_mbpsdiv = 1;
+ } else { /* V4H-7 */
+ if (md == 0) {
+ if (sscg == 0) {
+ priv->ddr_mbps = 6400;
+ priv->ddr_mbpsdiv = 1;
+ } else {
+ priv->ddr_mbps = 19000;
+ priv->ddr_mbpsdiv = 3;
+ }
+ } else if (md == 1) {
+ priv->ddr_mbps = 6000;
+ priv->ddr_mbpsdiv = 1;
+ } else if (md == 2) {
+ priv->ddr_mbps = 5500;
+ priv->ddr_mbpsdiv = 1;
+ } else if (md == 3) {
+ priv->ddr_mbps = 4800;
+ priv->ddr_mbpsdiv = 1;
+ }
}
priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2,
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ee923c1..a0d079c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -242,4 +242,20 @@
This enables the Reset Controller driver support for Microchip/Atmel
SoCs. Mainly used to expose assert/deassert methods to other drivers
that require it.
+
+config RESET_RZG2L_USBPHY_CTRL
+ bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control"
+ depends on DM_RESET
+ select REGULATOR_RZG2L_USBPHY
+ help
+ Enable support for controlling USB 2.0 PHY resets on the Renesas
+ RZ/G2L SoC. This is required for USB 2.0 functionality to work on this
+ SoC.
+
+config RESET_SPACEMIT_K1
+ bool "Support for SPACEMIT's K1 Reset driver"
+ depends on DM_RESET
+ help
+ Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert
+ is supported.
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 524fc06..b949439 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -34,3 +34,5 @@
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
obj-$(CONFIG_RESET_AT91) += reset-at91.o
obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o
+obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
+obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
new file mode 100644
index 0000000..622d7b9
--- /dev/null
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <renesas/rzg2l-usbphy.h>
+#include <reset-uclass.h>
+#include <reset.h>
+
+#define RESET 0x000
+
+#define RESET_SEL_PLLRESET BIT(12)
+#define RESET_PLLRESET BIT(8)
+
+#define RESET_SEL_P2RESET BIT(5)
+#define RESET_SEL_P1RESET BIT(4)
+#define RESET_PHYRST_2 BIT(1)
+#define RESET_PHYRST_1 BIT(0)
+
+#define PHY_RESET_MASK (RESET_PHYRST_1 | RESET_PHYRST_2)
+
+#define NUM_PORTS 2
+
+static int rzg2l_usbphy_ctrl_assert(struct reset_ctl *reset_ctl)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
+ u32 val;
+
+ val = readl(priv->regs + RESET);
+ val |= reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
+
+ /* If both ports are in reset, we can also place the PLL into reset. */
+ if ((val & PHY_RESET_MASK) == PHY_RESET_MASK)
+ val |= RESET_PLLRESET;
+
+ writel(val, priv->regs + RESET);
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_deassert(struct reset_ctl *reset_ctl)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
+ u32 val = reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
+
+ /* If either port is out of reset, the PLL must also be out of reset. */
+ val |= RESET_PLLRESET;
+
+ clrbits_le32(priv->regs + RESET, val);
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_of_xlate(struct reset_ctl *reset_ctl,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args[0] >= NUM_PORTS)
+ return -EINVAL;
+
+ reset_ctl->id = args->args[0];
+ return 0;
+}
+
+struct reset_ops rzg2l_usbphy_ctrl_ops = {
+ .rst_assert = rzg2l_usbphy_ctrl_assert,
+ .rst_deassert = rzg2l_usbphy_ctrl_deassert,
+ .of_xlate = rzg2l_usbphy_ctrl_of_xlate,
+};
+
+static int rzg2l_usbphy_ctrl_probe(struct udevice *dev)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev);
+ struct reset_ctl rst;
+ int ret;
+
+ priv->regs = dev_read_addr(dev);
+
+ ret = reset_get_by_index(dev, 0, &rst);
+ if (ret < 0) {
+ dev_err(dev, "failed to get reset line: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&rst);
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line: %d\n", ret);
+ return ret;
+ }
+
+ /* put pll and phy into reset state */
+ setbits_le32(priv->regs + RESET,
+ RESET_SEL_PLLRESET | RESET_PLLRESET |
+ RESET_SEL_P1RESET | RESET_PHYRST_1 |
+ RESET_SEL_P2RESET | RESET_PHYRST_2);
+
+ return 0;
+}
+
+static const struct udevice_id rzg2l_usbphy_ctrl_ids[] = {
+ { .compatible = "renesas,rzg2l-usbphy-ctrl", },
+ { /* sentinel */ }
+};
+
+static int rzg2l_usbphy_ctrl_bind(struct udevice *dev)
+{
+ struct driver *drv;
+ ofnode node;
+ int ret;
+
+ node = ofnode_find_subnode(dev_ofnode(dev), "regulator-vbus");
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "Failed to find vbus regulator devicetree node\n");
+ return -ENOENT;
+ }
+
+ drv = lists_driver_lookup_name("rzg2l_usbphy_regulator");
+ if (!drv) {
+ dev_err(dev, "Failed to find vbus regulator driver\n");
+ return -ENOENT;
+ }
+
+ ret = device_bind(dev, drv, dev->name, NULL, node, NULL);
+ if (ret) {
+ dev_err(dev, "Failed to bind vbus regulator: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rzg2l_usbphy_ctrl) = {
+ .name = "rzg2l_usbphy_ctrl",
+ .id = UCLASS_RESET,
+ .of_match = rzg2l_usbphy_ctrl_ids,
+ .bind = rzg2l_usbphy_ctrl_bind,
+ .probe = rzg2l_usbphy_ctrl_probe,
+ .ops = &rzg2l_usbphy_ctrl_ops,
+ .priv_auto = sizeof(struct rzg2l_usbphy_ctrl_priv),
+};
diff --git a/drivers/reset/reset-spacemit-k1.c b/drivers/reset/reset-spacemit-k1.c
new file mode 100644
index 0000000..613e002
--- /dev/null
+++ b/drivers/reset/reset-spacemit-k1.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/reset/spacemit-k1-reset.h>
+#include <linux/bitops.h>
+#include <reset-uclass.h>
+
+/* APBC register offset */
+#define APBC_UART1_CLK_RST 0x0
+#define APBC_UART2_CLK_RST 0x4
+#define APBC_GPIO_CLK_RST 0x8
+#define APBC_PWM0_CLK_RST 0xc
+#define APBC_PWM1_CLK_RST 0x10
+#define APBC_PWM2_CLK_RST 0x14
+#define APBC_PWM3_CLK_RST 0x18
+#define APBC_TWSI8_CLK_RST 0x20
+#define APBC_UART3_CLK_RST 0x24
+#define APBC_RTC_CLK_RST 0x28
+#define APBC_TWSI0_CLK_RST 0x2c
+#define APBC_TWSI1_CLK_RST 0x30
+#define APBC_TIMERS1_CLK_RST 0x34
+#define APBC_TWSI2_CLK_RST 0x38
+#define APBC_AIB_CLK_RST 0x3c
+#define APBC_TWSI4_CLK_RST 0x40
+#define APBC_TIMERS2_CLK_RST 0x44
+#define APBC_ONEWIRE_CLK_RST 0x48
+#define APBC_TWSI5_CLK_RST 0x4c
+#define APBC_DRO_CLK_RST 0x58
+#define APBC_IR_CLK_RST 0x5c
+#define APBC_TWSI6_CLK_RST 0x60
+#define APBC_TWSI7_CLK_RST 0x68
+#define APBC_TSEN_CLK_RST 0x6c
+
+#define APBC_UART4_CLK_RST 0x70
+#define APBC_UART5_CLK_RST 0x74
+#define APBC_UART6_CLK_RST 0x78
+#define APBC_SSP3_CLK_RST 0x7c
+
+#define APBC_SSPA0_CLK_RST 0x80
+#define APBC_SSPA1_CLK_RST 0x84
+
+#define APBC_IPC_AP2AUD_CLK_RST 0x90
+#define APBC_UART7_CLK_RST 0x94
+#define APBC_UART8_CLK_RST 0x98
+#define APBC_UART9_CLK_RST 0x9c
+
+#define APBC_CAN0_CLK_RST 0xa0
+#define APBC_PWM4_CLK_RST 0xa8
+#define APBC_PWM5_CLK_RST 0xac
+#define APBC_PWM6_CLK_RST 0xb0
+#define APBC_PWM7_CLK_RST 0xb4
+#define APBC_PWM8_CLK_RST 0xb8
+#define APBC_PWM9_CLK_RST 0xbc
+#define APBC_PWM10_CLK_RST 0xc0
+#define APBC_PWM11_CLK_RST 0xc4
+#define APBC_PWM12_CLK_RST 0xc8
+#define APBC_PWM13_CLK_RST 0xcc
+#define APBC_PWM14_CLK_RST 0xd0
+#define APBC_PWM15_CLK_RST 0xd4
+#define APBC_PWM16_CLK_RST 0xd8
+#define APBC_PWM17_CLK_RST 0xdc
+#define APBC_PWM18_CLK_RST 0xe0
+#define APBC_PWM19_CLK_RST 0xe4
+/* end of APBC register offset */
+
+/* MPMU register offset */
+#define MPMU_WDTPCR 0x200
+/* end of MPMU register offset */
+
+/* APMU register offset */
+#define APMU_JPG_CLK_RES_CTRL 0x20
+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x24
+#define APMU_ISP_CLK_RES_CTRL 0x38
+#define APMU_LCD_CLK_RES_CTRL1 0x44
+#define APMU_LCD_SPI_CLK_RES_CTRL 0x48
+#define APMU_LCD_CLK_RES_CTRL2 0x4c
+#define APMU_CCIC_CLK_RES_CTRL 0x50
+#define APMU_SDH0_CLK_RES_CTRL 0x54
+#define APMU_SDH1_CLK_RES_CTRL 0x58
+#define APMU_USB_CLK_RES_CTRL 0x5c
+#define APMU_QSPI_CLK_RES_CTRL 0x60
+#define APMU_USB_CLK_RES_CTRL 0x5c
+#define APMU_DMA_CLK_RES_CTRL 0x64
+#define APMU_AES_CLK_RES_CTRL 0x68
+#define APMU_VPU_CLK_RES_CTRL 0xa4
+#define APMU_GPU_CLK_RES_CTRL 0xcc
+#define APMU_SDH2_CLK_RES_CTRL 0xe0
+#define APMU_PMUA_MC_CTRL 0xe8
+#define APMU_PMU_CC2_AP 0x100
+#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
+
+#define APMU_AUDIO_CLK_RES_CTRL 0x14c
+#define APMU_HDMI_CLK_RES_CTRL 0x1B8
+
+#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
+#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
+#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
+
+#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
+#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
+/* end of APMU register offset */
+
+/* APBC2 register offset */
+#define APBC2_UART1_CLK_RST 0x00
+#define APBC2_SSP2_CLK_RST 0x04
+#define APBC2_TWSI3_CLK_RST 0x08
+#define APBC2_RTC_CLK_RST 0x0c
+#define APBC2_TIMERS0_CLK_RST 0x10
+#define APBC2_KPC_CLK_RST 0x14
+#define APBC2_GPIO_CLK_RST 0x1c
+/* end of APBC2 register offset */
+
+enum spacemit_reset_base_type {
+ RST_BASE_TYPE_MPMU = 0,
+ RST_BASE_TYPE_APMU = 1,
+ RST_BASE_TYPE_APBC = 2,
+ RST_BASE_TYPE_APBS = 3,
+ RST_BASE_TYPE_CIU = 4,
+ RST_BASE_TYPE_DCIU = 5,
+ RST_BASE_TYPE_DDRC = 6,
+ RST_BASE_TYPE_AUDC = 7,
+ RST_BASE_TYPE_APBC2 = 8,
+};
+
+struct spacemit_reset_signal {
+ u32 offset;
+ u32 mask;
+ u32 deassert_val;
+ u32 assert_val;
+ enum spacemit_reset_base_type type;
+};
+
+struct spacemit_reset_base {
+ void __iomem *mpmu_base;
+ void __iomem *apmu_base;
+ void __iomem *apbc_base;
+ void __iomem *apbs_base;
+ void __iomem *ciu_base;
+ void __iomem *dciu_base;
+ void __iomem *ddrc_base;
+ void __iomem *audio_ctrl_base;
+ void __iomem *apbc2_base;
+};
+
+struct spacemit_reset {
+ struct spacemit_reset_base io_base;
+ const struct spacemit_reset_signal *signals;
+};
+
+enum {
+ RESET_TWSI6_SPL = 0,
+ RESET_TWSI8_SPL,
+ RESET_SDH_AXI_SPL,
+ RESET_SDH0_SPL,
+ RESET_USB_AXI_SPL,
+ RESET_USBP1_AXI_SPL,
+ RESET_USB3_0_SPL,
+ RESET_QSPI_SPL,
+ RESET_QSPI_BUS_SPL,
+ RESET_AES_SPL,
+ RESET_SDH2_SPL,
+ RESET_NUMBER_SPL
+};
+
+static const struct spacemit_reset_signal
+ k1_reset_signals[RESET_NUMBER] = {
+ [RESET_UART1] = { APBC_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART2] = { APBC_UART2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_GPIO] = { APBC_GPIO_CLK_RST, BIT(2), 0,
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM0] = { APBC_PWM0_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM1] = { APBC_PWM1_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM2] = { APBC_PWM2_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM3] = { APBC_PWM3_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM4] = { APBC_PWM4_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM5] = { APBC_PWM5_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM6] = { APBC_PWM6_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM7] = { APBC_PWM7_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM8] = { APBC_PWM8_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM9] = { APBC_PWM9_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM10] = { APBC_PWM10_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM11] = { APBC_PWM11_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM12] = { APBC_PWM12_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM13] = { APBC_PWM13_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM14] = { APBC_PWM14_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM15] = { APBC_PWM15_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM16] = { APBC_PWM16_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM17] = { APBC_PWM17_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM18] = { APBC_PWM18_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_PWM19] = { APBC_PWM19_CLK_RST,
+ BIT(2) | BIT(0),
+ BIT(0),
+ BIT(2),
+ RST_BASE_TYPE_APBC },
+ [RESET_SSP3] = { APBC_SSP3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART3] = { APBC_UART3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_RTC] = { APBC_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI0] = { APBC_TWSI0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TIMERS1] = { APBC_TIMERS1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_AIB] = { APBC_AIB_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TIMERS2] = { APBC_TIMERS2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_ONEWIRE] = { APBC_ONEWIRE_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_SSPA0] = { APBC_SSPA0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_SSPA1] = { APBC_SSPA1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_DRO] = { APBC_DRO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_IR] = { APBC_IR_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI1] = { APBC_TWSI1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TSEN] = { APBC_TSEN_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI2] = { APBC_TWSI2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI4] = { APBC_TWSI4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI5] = { APBC_TWSI5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI6] = { APBC_TWSI6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI7] = { APBC_TWSI7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_TWSI8] = { APBC_TWSI8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_IPC_AP2AUD] = { APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART4] = { APBC_UART4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART5] = { APBC_UART5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART6] = { APBC_UART6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART7] = { APBC_UART7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART8] = { APBC_UART8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_UART9] = { APBC_UART9_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ [RESET_CAN0] = { APBC_CAN0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+ /* MPMU */
+ [RESET_WDT] = { MPMU_WDTPCR, BIT(2), 0, BIT(2), RST_BASE_TYPE_MPMU },
+ /* APMU */
+ [RESET_JPG] = { APMU_JPG_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_CSI] = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_CCIC2_PHY] = { APMU_CSI_CCIC2_CLK_RES_CTRL,
+ BIT(2),
+ BIT(2),
+ 0,
+ RST_BASE_TYPE_APMU },
+ [RESET_CCIC3_PHY] = { APMU_CSI_CCIC2_CLK_RES_CTRL,
+ BIT(29),
+ BIT(29),
+ 0,
+ RST_BASE_TYPE_APMU },
+ [RESET_ISP] = { APMU_ISP_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_ISP_AHB] = { APMU_ISP_CLK_RES_CTRL, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+ [RESET_ISP_CI] = { APMU_ISP_CLK_RES_CTRL, BIT(16), BIT(16), 0, RST_BASE_TYPE_APMU },
+ [RESET_ISP_CPP] = { APMU_ISP_CLK_RES_CTRL, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+ [RESET_LCD] = { APMU_LCD_CLK_RES_CTRL1, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+ [RESET_DSI_ESC] = { APMU_LCD_CLK_RES_CTRL1, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+ [RESET_V2D] = { APMU_LCD_CLK_RES_CTRL1, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+ [RESET_MIPI] = { APMU_LCD_CLK_RES_CTRL1, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU },
+ [RESET_LCD_SPI] = { APMU_LCD_SPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_LCD_SPI_BUS] = { APMU_LCD_SPI_CLK_RES_CTRL,
+ BIT(4),
+ BIT(4),
+ 0,
+ RST_BASE_TYPE_APMU },
+ [RESET_LCD_SPI_HBUS] = { APMU_LCD_SPI_CLK_RES_CTRL,
+ BIT(2),
+ BIT(2),
+ 0,
+ RST_BASE_TYPE_APMU },
+ [RESET_LCD_MCLK] = { APMU_LCD_CLK_RES_CTRL2, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+ [RESET_CCIC_4X] = { APMU_CCIC_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_CCIC1_PHY] = { APMU_CCIC_CLK_RES_CTRL, BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU },
+ [RESET_SDH_AXI] = { APMU_SDH0_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_SDH0] = { APMU_SDH0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_SDH1] = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_USB_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+ [RESET_USB3_0] = { APMU_USB_CLK_RES_CTRL,
+ BIT(9) | BIT(10) | BIT(11),
+ BIT(9) | BIT(10) | BIT(11),
+ 0,
+ RST_BASE_TYPE_APMU },
+ [RESET_QSPI] = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_QSPI_BUS] = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_DMA] = { APMU_DMA_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_AES] = { APMU_AES_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+ [RESET_VPU] = { APMU_VPU_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_GPU] = { APMU_GPU_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_SDH2] = { APMU_SDH2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_MC] = { APMU_PMUA_MC_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_EM_AXI] = { APMU_PMUA_EM_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+ [RESET_EM] = { APMU_PMUA_EM_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_AUDIO_SYS] = { APMU_AUDIO_CLK_RES_CTRL,
+ BIT(0) | BIT(2) | BIT(3),
+ BIT(0) | BIT(2) | BIT(3),
+ 0,
+ RST_BASE_TYPE_APMU },
+ [RESET_HDMI] = { APMU_HDMI_CLK_RES_CTRL, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+ [RESET_PCIE0] = { APMU_PCIE_CLK_RES_CTRL_0,
+ BIT(3) | BIT(4) | BIT(5) | BIT(8),
+ BIT(3) | BIT(4) | BIT(5),
+ BIT(8),
+ RST_BASE_TYPE_APMU },
+ [RESET_PCIE1] = { APMU_PCIE_CLK_RES_CTRL_1,
+ BIT(3) | BIT(4) | BIT(5) | BIT(8),
+ BIT(3) | BIT(4) | BIT(5),
+ BIT(8),
+ RST_BASE_TYPE_APMU },
+ [RESET_PCIE2] = { APMU_PCIE_CLK_RES_CTRL_2, 0x138, 0x38, 0x100, RST_BASE_TYPE_APMU },
+ [RESET_EMAC0] = { APMU_EMAC0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_EMAC1] = { APMU_EMAC1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+ [RESET_SEC_UART1] = { APBC2_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ [RESET_SEC_SSP2] = { APBC2_SSP2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ [RESET_SEC_TWSI3] = { APBC2_TWSI3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ [RESET_SEC_RTC] = { APBC2_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ [RESET_SEC_TIMERS0] = { APBC2_TIMERS0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ [RESET_SEC_KPC] = { APBC2_KPC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ [RESET_SEC_GPIO] = { APBC2_GPIO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+ };
+
+static u32 spacemit_reset_read(struct spacemit_reset *reset, u32 id)
+{
+ void __iomem *base;
+
+ switch (reset->signals[id].type) {
+ case RST_BASE_TYPE_APMU:
+ base = reset->io_base.apmu_base;
+ break;
+ case RST_BASE_TYPE_APBC:
+ base = reset->io_base.apbc_base;
+ break;
+ default:
+ base = reset->io_base.apbc_base;
+ break;
+ }
+
+ return readl(base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_write(struct spacemit_reset *reset, u32 value, u32 id)
+{
+ void __iomem *base;
+
+ switch (reset->signals[id].type) {
+ case RST_BASE_TYPE_APMU:
+ base = reset->io_base.apmu_base;
+ break;
+ case RST_BASE_TYPE_APBC:
+ base = reset->io_base.apbc_base;
+ break;
+ default:
+ base = reset->io_base.apbc_base;
+ break;
+ }
+
+ writel(value, base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_set(struct reset_ctl *rst, u32 id, bool assert)
+{
+ u32 value;
+ struct spacemit_reset *reset = dev_get_priv(rst->dev);
+
+ value = spacemit_reset_read(reset, id);
+
+ if (assert) {
+ value &= ~reset->signals[id].mask;
+ value |= reset->signals[id].assert_val;
+ } else {
+ value &= ~reset->signals[id].mask;
+ value |= reset->signals[id].deassert_val;
+ }
+
+ spacemit_reset_write(reset, value, id);
+}
+
+static int spacemit_reset_update(struct reset_ctl *rst, bool assert)
+{
+ if (rst->id < RESET_UART1 || rst->id >= RESET_NUMBER)
+ return 0;
+
+ /* can not write to twsi8 */
+ if (rst->id == RESET_TWSI8)
+ return 0;
+
+ spacemit_reset_set(rst, rst->id, assert);
+ return 0;
+}
+
+static int spacemit_reset_assert(struct reset_ctl *rst)
+{
+ return spacemit_reset_update(rst, true);
+}
+
+static int spacemit_reset_deassert(struct reset_ctl *rst)
+{
+ return spacemit_reset_update(rst, false);
+}
+
+static int spacemit_k1_reset_probe(struct udevice *dev)
+{
+ struct spacemit_reset *reset = dev_get_priv(dev);
+
+ reset->io_base.mpmu_base = (void *)dev_remap_addr_index(dev, 0);
+ if (!reset->io_base.mpmu_base) {
+ pr_err("failed to map mpmu registers\n");
+ goto out;
+ }
+
+ reset->io_base.apmu_base = (void *)dev_remap_addr_index(dev, 1);
+ if (!reset->io_base.apmu_base) {
+ pr_err("failed to map apmu registers\n");
+ goto out;
+ }
+
+ reset->io_base.apbc_base = (void *)dev_remap_addr_index(dev, 2);
+ if (!reset->io_base.apbc_base) {
+ pr_err("failed to map apbc registers\n");
+ goto out;
+ }
+
+ reset->io_base.apbs_base = (void *)dev_remap_addr_index(dev, 3);
+ if (!reset->io_base.apbs_base) {
+ pr_err("failed to map apbs registers\n");
+ goto out;
+ }
+
+ reset->io_base.ciu_base = (void *)dev_remap_addr_index(dev, 4);
+ if (!reset->io_base.ciu_base) {
+ pr_err("failed to map ciu registers\n");
+ goto out;
+ }
+
+ reset->io_base.dciu_base = (void *)dev_remap_addr_index(dev, 5);
+ if (!reset->io_base.dciu_base) {
+ pr_err("failed to map dragon ciu registers\n");
+ goto out;
+ }
+
+ reset->io_base.ddrc_base = (void *)dev_remap_addr_index(dev, 6);
+ if (!reset->io_base.ddrc_base) {
+ pr_err("failed to map ddrc registers\n");
+ goto out;
+ }
+
+ reset->io_base.apbc2_base = (void *)dev_remap_addr_index(dev, 7);
+ if (!reset->io_base.apbc2_base) {
+ pr_err("failed to map apbc2 registers\n");
+ goto out;
+ }
+
+ reset->signals = k1_reset_signals;
+
+out:
+ return 0;
+}
+
+const struct reset_ops k1_reset_ops = {
+ .rst_assert = spacemit_reset_assert,
+ .rst_deassert = spacemit_reset_deassert,
+};
+
+static const struct udevice_id k1_reset_ids[] = {
+ { .compatible = "spacemit,k1-reset", },
+ {},
+};
+
+U_BOOT_DRIVER(k1_reset) = {
+ .name = "spacemit,k1-reset",
+ .id = UCLASS_RESET,
+ .ops = &k1_reset_ops,
+ .of_match = k1_reset_ids,
+ .probe = spacemit_k1_reset_probe,
+ .priv_auto = sizeof(struct spacemit_reset),
+};
diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c
index f790d3b..aab602c 100644
--- a/drivers/rng/msm_rng.c
+++ b/drivers/rng/msm_rng.c
@@ -44,6 +44,11 @@
u32 *retdata = data;
size_t maxsize;
u32 val;
+ int ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret < 0)
+ return ret;
/* calculate max size bytes to transfer back to caller */
maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
@@ -66,6 +71,8 @@
break;
} while (currsize < maxsize);
+ clk_disable(&priv->clk);
+
return 0;
}
@@ -76,7 +83,7 @@
if (enable) {
/* Enable PRNG only if it is not already enabled */
val = readl_relaxed(priv->base + PRNG_CONFIG);
- if (val & PRNG_CONFIG_HW_ENABLE) {
+ if (!(val & PRNG_CONFIG_HW_ENABLE)) {
val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
val &= ~PRNG_LFSR_CFG_MASK;
val |= PRNG_LFSR_CFG_CLOCKS;
@@ -118,7 +125,9 @@
if (ret < 0)
return ret;
- return msm_rng_enable(priv, 1);
+ ret = msm_rng_enable(priv, 1);
+ clk_disable(&priv->clk);
+ return ret;
}
static int msm_rng_remove(struct udevice *dev)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c4f4a8d..8413052 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -789,6 +789,12 @@
default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS
select SYS_NS16550
+config TPL_SYS_NS16550_SERIAL
+ bool "NS16550 UART or compatible legacy driver in TPL"
+ depends on TPL && !TPL_DM_SERIAL
+ default y if SPL_SYS_NS16550_SERIAL
+ select SYS_NS16550
+
config SYS_NS16550
bool "NS16550 UART or compatible"
help
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index c5fd740..28f4435 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,6 +3,7 @@
* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
*/
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
@@ -312,7 +313,17 @@
static int mxc_serial_probe(struct udevice *dev)
{
struct mxc_serial_plat *plat = dev_get_plat(dev);
+#if CONFIG_IS_ENABLED(CLK_CCF)
+ int ret;
+ ret = clk_get_bulk(dev, &plat->clks);
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(&plat->clks);
+ if (ret)
+ return ret;
+#endif
_mxc_serial_init(plat->reg, plat->use_dte);
return 0;
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 121194e..475540f 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -242,7 +242,6 @@
config SYSRESET_QCOM_PSHOLD
bool "Support sysreset for Qualcomm SoCs via PSHOLD"
- depends on ARCH_IPQ40XX
help
Add support for the system reboot on Qualcomm SoCs via PSHOLD.
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index f7d8c40..91f6ad3 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -19,6 +19,7 @@
#include <malloc.h>
#include <hexdump.h>
#include <scsi.h>
+#include <ufs.h>
#include <asm/io.h>
#include <asm/dma-mapping.h>
#include <linux/bitops.h>
@@ -313,16 +314,12 @@
ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
&tx_lanes);
for (i = 0; i < tx_lanes; i++) {
+ unsigned int val = UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
+ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i));
if (!peer)
- err = ufshcd_dme_set(hba,
- UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
- UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
- 0);
+ err = ufshcd_dme_set(hba, val, 0);
else
- err = ufshcd_dme_peer_set(hba,
- UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
- UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
- 0);
+ err = ufshcd_dme_peer_set(hba, val, 0);
if (err) {
dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n",
__func__, peer, i, err);
@@ -1034,8 +1031,8 @@
/**
* ufshcd_query_flag() - API function for sending flag query requests
*/
-int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
- enum flag_idn idn, bool *flag_res)
+static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
+ enum flag_idn idn, bool *flag_res)
{
struct ufs_query_req *request = NULL;
struct ufs_query_res *response = NULL;
@@ -1170,9 +1167,9 @@
/**
* ufshcd_query_descriptor_retry - API function for sending descriptor requests
*/
-int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
- enum desc_idn idn, u8 index, u8 selector,
- u8 *desc_buf, int *buf_len)
+static int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
+ enum desc_idn idn, u8 index, u8 selector,
+ u8 *desc_buf, int *buf_len)
{
int err;
int retries;
@@ -1264,8 +1261,8 @@
* ufshcd_map_desc_id_to_length - map descriptor IDN to its length
*
*/
-int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
- int *desc_len)
+static int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
+ int *desc_len)
{
switch (desc_id) {
case QUERY_DESC_IDN_DEVICE:
@@ -1302,15 +1299,14 @@
}
return 0;
}
-EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
/**
* ufshcd_read_desc_param - read the specified descriptor parameter
*
*/
-int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
- int desc_index, u8 param_offset, u8 *param_read_buf,
- u8 param_size)
+static int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
+ int desc_index, u8 param_offset,
+ u8 *param_read_buf, u8 param_size)
{
int ret;
u8 *desc_buf;
@@ -1569,8 +1565,8 @@
* ufshcd_read_string_desc - read string descriptor
*
*/
-int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
- u8 *buf, u32 size, bool ascii)
+static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
+ u8 *buf, u32 size, bool ascii)
{
int err = 0;
@@ -1881,7 +1877,7 @@
hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
}
-int ufs_start(struct ufs_hba *hba)
+static int ufs_start(struct ufs_hba *hba)
{
struct ufs_dev_desc card = {0};
int ret;
@@ -1962,7 +1958,7 @@
ufshcd_ops_init(hba);
- /* Read capabilties registers */
+ /* Read capabilities registers */
hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
@@ -2001,7 +1997,7 @@
REG_INTERRUPT_STATUS);
ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
- mb();
+ mb(); /* flush previous writes */
/* Reset the attached device */
ufshcd_device_reset(hba);
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 00ecca3..53137fa 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -4,6 +4,7 @@
#include <linux/types.h>
#include <asm/io.h>
+#include "ufshci.h"
#include "unipro.h"
struct udevice;
@@ -14,11 +15,6 @@
#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
#define UFS_MAX_LUNS 0x7F
-enum {
- TASK_REQ_UPIU_SIZE_DWORDS = 8,
- TASK_RSP_UPIU_SIZE_DWORDS = 8,
- ALIGNED_UPIU_SIZE = 512,
-};
/* UFS device power modes */
enum ufs_dev_pwr_mode {
@@ -84,44 +80,6 @@
/* Offset of the response code in the UPIU header */
#define UPIU_RSP_CODE_OFFSET 8
-/* To accommodate UFS2.0 required Command type */
-enum {
- UTP_CMD_TYPE_UFS_STORAGE = 0x1,
-};
-
-enum {
- UTP_SCSI_COMMAND = 0x00000000,
- UTP_NATIVE_UFS_COMMAND = 0x10000000,
- UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
- UTP_REQ_DESC_INT_CMD = 0x01000000,
-};
-
-/* UTP Transfer Request Data Direction (DD) */
-enum {
- UTP_NO_DATA_TRANSFER = 0x00000000,
- UTP_HOST_TO_DEVICE = 0x02000000,
- UTP_DEVICE_TO_HOST = 0x04000000,
-};
-
-/* Overall command status values */
-enum {
- OCS_SUCCESS = 0x0,
- OCS_INVALID_CMD_TABLE_ATTR = 0x1,
- OCS_INVALID_PRDT_ATTR = 0x2,
- OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
- OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
- OCS_PEER_COMM_FAILURE = 0x5,
- OCS_ABORTED = 0x6,
- OCS_FATAL_ERROR = 0x7,
- OCS_INVALID_COMMAND_STATUS = 0x0F,
- MASK_OCS = 0x0F,
-};
-
-/* The maximum length of the data byte count field in the PRDT is 256KB */
-#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
-/* The granularity of the data byte count field in the PRDT is 32-bit */
-#define PRDT_DATA_BYTE_COUNT_PAD 4
-
#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
#define QUERY_DESC_MAX_SIZE 255
#define QUERY_DESC_MIN_SIZE 2
@@ -130,8 +88,8 @@
(sizeof(struct utp_upiu_header)))
#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
- cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
- (byte1 << 8) | (byte0))
+ cpu_to_be32(((byte3) << 24) | ((byte2) << 16) |\
+ ((byte1) << 8) | (byte0))
/*
* UFS Protocol Information Unit related definitions
*/
@@ -297,79 +255,6 @@
QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
};
-struct ufshcd_sg_entry {
- __le32 base_addr;
- __le32 upper_addr;
- __le32 reserved;
- __le32 size;
-};
-
-#define MAX_BUFF 128
-/**
- * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
- * @command_upiu: Command UPIU Frame address
- * @response_upiu: Response UPIU Frame address
- * @prd_table: Physical Region Descriptor
- */
-struct utp_transfer_cmd_desc {
- u8 command_upiu[ALIGNED_UPIU_SIZE];
- u8 response_upiu[ALIGNED_UPIU_SIZE];
- struct ufshcd_sg_entry prd_table[MAX_BUFF];
-};
-
-/**
- * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
- * @dword0: Descriptor Header DW0
- * @dword1: Descriptor Header DW1
- * @dword2: Descriptor Header DW2
- * @dword3: Descriptor Header DW3
- */
-struct request_desc_header {
- __le32 dword_0;
- __le32 dword_1;
- __le32 dword_2;
- __le32 dword_3;
-};
-
-/**
- * struct utp_transfer_req_desc - UTRD structure
- * @header: UTRD header DW-0 to DW-3
- * @command_desc_base_addr_lo: UCD base address low DW-4
- * @command_desc_base_addr_hi: UCD base address high DW-5
- * @response_upiu_length: response UPIU length DW-6
- * @response_upiu_offset: response UPIU offset DW-6
- * @prd_table_length: Physical region descriptor length DW-7
- * @prd_table_offset: Physical region descriptor offset DW-7
- */
-struct utp_transfer_req_desc {
- /* DW 0-3 */
- struct request_desc_header header;
-
- /* DW 4-5*/
- __le32 command_desc_base_addr_lo;
- __le32 command_desc_base_addr_hi;
-
- /* DW 6 */
- __le16 response_upiu_length;
- __le16 response_upiu_offset;
-
- /* DW 7 */
- __le16 prd_table_length;
- __le16 prd_table_offset;
-};
-
-/**
- * struct utp_upiu_header - UPIU header structure
- * @dword_0: UPIU header DW-0
- * @dword_1: UPIU header DW-1
- * @dword_2: UPIU header DW-2
- */
-struct utp_upiu_header {
- __be32 dword_0;
- __be32 dword_1;
- __be32 dword_2;
-};
-
/**
* struct utp_upiu_query - upiu request buffer structure for
* query request.
@@ -403,27 +288,6 @@
u8 cdb[UFS_CDB_SIZE];
};
-/*
- * UTMRD structure.
- */
-struct utp_task_req_desc {
- /* DW 0-3 */
- struct request_desc_header header;
-
- /* DW 4-11 - Task request UPIU structure */
- struct utp_upiu_header req_header;
- __be32 input_param1;
- __be32 input_param2;
- __be32 input_param3;
- __be32 __reserved1[2];
-
- /* DW 12-19 - Task Management Response UPIU structure */
- struct utp_upiu_header rsp_header;
- __be32 output_param1;
- __be32 output_param2;
- __be32 __reserved2[3];
-};
-
/**
* struct utp_upiu_req - general upiu request structure
* @header:UPIU header structure DW-0 to DW-2
@@ -551,63 +415,6 @@
int result;
};
-/* GenSelectorIndex calculation macros for M-PHY attributes */
-#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
-#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
-
-#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
- ((sel) & 0xFFFF))
-#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
-#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
-#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
-
-/* Link Status*/
-enum link_status {
- UFSHCD_LINK_IS_DOWN = 1,
- UFSHCD_LINK_IS_UP = 2,
-};
-
-#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
- ((sel) & 0xFFFF))
-#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
-#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
-#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
-
-/* UIC Commands */
-enum uic_cmd_dme {
- UIC_CMD_DME_GET = 0x01,
- UIC_CMD_DME_SET = 0x02,
- UIC_CMD_DME_PEER_GET = 0x03,
- UIC_CMD_DME_PEER_SET = 0x04,
- UIC_CMD_DME_POWERON = 0x10,
- UIC_CMD_DME_POWEROFF = 0x11,
- UIC_CMD_DME_ENABLE = 0x12,
- UIC_CMD_DME_RESET = 0x14,
- UIC_CMD_DME_END_PT_RST = 0x15,
- UIC_CMD_DME_LINK_STARTUP = 0x16,
- UIC_CMD_DME_HIBER_ENTER = 0x17,
- UIC_CMD_DME_HIBER_EXIT = 0x18,
- UIC_CMD_DME_TEST_MODE = 0x1A,
-};
-
-/* UIC Config result code / Generic error code */
-enum {
- UIC_CMD_RESULT_SUCCESS = 0x00,
- UIC_CMD_RESULT_INVALID_ATTR = 0x01,
- UIC_CMD_RESULT_FAILURE = 0x01,
- UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
- UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
- UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
- UIC_CMD_RESULT_BAD_INDEX = 0x05,
- UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
- UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
- UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
- UIC_CMD_RESULT_BUSY = 0x09,
- UIC_CMD_RESULT_DME_FAILURE = 0x0A,
-};
-
-#define MASK_UIC_COMMAND_RESULT 0xFF
-
/* Host <-> Device UniPro Link state */
enum uic_link_state {
UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
@@ -915,7 +722,7 @@
}
static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
- bool status)
+ bool status)
{
if (hba->ops && hba->ops->hce_enable_notify)
return hba->ops->hce_enable_notify(hba, status);
@@ -940,17 +747,6 @@
return 0;
}
-/* Controller UFSHCI version */
-enum {
- UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
- UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
- UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
- UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
- UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
- UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
- UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
-};
-
/* Interrupt disable masks */
enum {
/* Interrupt disable mask for UFSHCI v1.0 */
@@ -964,123 +760,6 @@
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
};
-/* UFSHCI Registers */
-enum {
- REG_CONTROLLER_CAPABILITIES = 0x00,
- REG_UFS_VERSION = 0x08,
- REG_CONTROLLER_DEV_ID = 0x10,
- REG_CONTROLLER_PROD_ID = 0x14,
- REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
- REG_INTERRUPT_STATUS = 0x20,
- REG_INTERRUPT_ENABLE = 0x24,
- REG_CONTROLLER_STATUS = 0x30,
- REG_CONTROLLER_ENABLE = 0x34,
- REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
- REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
- REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
- REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
- REG_UIC_ERROR_CODE_DME = 0x48,
- REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
- REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
- REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
- REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
- REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
- REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
- REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
- REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
- REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
- REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
- REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
- REG_UIC_COMMAND = 0x90,
- REG_UIC_COMMAND_ARG_1 = 0x94,
- REG_UIC_COMMAND_ARG_2 = 0x98,
- REG_UIC_COMMAND_ARG_3 = 0x9C,
-
- UFSHCI_REG_SPACE_SIZE = 0xA0,
-
- REG_UFS_CCAP = 0x100,
- REG_UFS_CRYPTOCAP = 0x104,
-
- UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
-};
-
-/* Controller capability masks */
-enum {
- MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
- MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
- MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
- MASK_64_ADDRESSING_SUPPORT = 0x01000000,
- MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
- MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
-};
-
-/* Interrupt Status 20h */
-#define UTP_TRANSFER_REQ_COMPL 0x1
-#define UIC_DME_END_PT_RESET 0x2
-#define UIC_ERROR 0x4
-#define UIC_TEST_MODE 0x8
-#define UIC_POWER_MODE 0x10
-#define UIC_HIBERNATE_EXIT 0x20
-#define UIC_HIBERNATE_ENTER 0x40
-#define UIC_LINK_LOST 0x80
-#define UIC_LINK_STARTUP 0x100
-#define UTP_TASK_REQ_COMPL 0x200
-#define UIC_COMMAND_COMPL 0x400
-#define DEVICE_FATAL_ERROR 0x800
-#define CONTROLLER_FATAL_ERROR 0x10000
-#define SYSTEM_BUS_FATAL_ERROR 0x20000
-
-#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
- UIC_HIBERNATE_EXIT |\
- UIC_POWER_MODE)
-
-#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
-
-#define UFSHCD_ERROR_MASK (UIC_ERROR |\
- DEVICE_FATAL_ERROR |\
- CONTROLLER_FATAL_ERROR |\
- SYSTEM_BUS_FATAL_ERROR)
-
-#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
- CONTROLLER_FATAL_ERROR |\
- SYSTEM_BUS_FATAL_ERROR)
-
-/* Host Controller Enable 0x34h */
-#define CONTROLLER_ENABLE 0x1
-#define CONTROLLER_DISABLE 0x0
-/* HCS - Host Controller Status 30h */
-#define DEVICE_PRESENT 0x1
-#define UTP_TRANSFER_REQ_LIST_READY 0x2
-#define UTP_TASK_REQ_LIST_READY 0x4
-#define UIC_COMMAND_READY 0x8
-#define HOST_ERROR_INDICATOR 0x10
-#define DEVICE_ERROR_INDICATOR 0x20
-#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
-
-#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
- UTP_TASK_REQ_LIST_READY |\
- UIC_COMMAND_READY)
-
-enum {
- PWR_OK = 0x0,
- PWR_LOCAL = 0x01,
- PWR_REMOTE = 0x02,
- PWR_BUSY = 0x03,
- PWR_ERROR_CAP = 0x04,
- PWR_FATAL_ERROR = 0x05,
-};
-
-/* UICCMD - UIC Command */
-#define COMMAND_OPCODE_MASK 0xFF
-#define GEN_SELECTOR_INDEX_MASK 0xFFFF
-
-#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
-#define RESET_LEVEL 0xFF
-
-#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
-#define CFG_RESULT_CODE_MASK 0xFF
-#define GENERIC_ERROR_CODE_MASK 0xFF
-
#define ufshcd_writel(hba, val, reg) \
writel((val), (hba)->mmio_base + (reg))
#define ufshcd_readl(hba, reg) \
@@ -1103,12 +782,6 @@
ufshcd_writel(hba, tmp, reg);
}
-/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
-#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
-
-/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
-#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
-
int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
#endif
diff --git a/drivers/ufs/ufshci.h b/drivers/ufs/ufshci.h
new file mode 100644
index 0000000..90cbf87
--- /dev/null
+++ b/drivers/ufs/ufshci.h
@@ -0,0 +1,469 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __UFSHCI_H
+#define __UFSHCI_H
+
+enum {
+ TASK_REQ_UPIU_SIZE_DWORDS = 8,
+ TASK_RSP_UPIU_SIZE_DWORDS = 8,
+ ALIGNED_UPIU_SIZE = 512,
+};
+
+/* UFSHCI Registers */
+enum {
+ REG_CONTROLLER_CAPABILITIES = 0x00,
+ REG_MCQCAP = 0x04,
+ REG_UFS_VERSION = 0x08,
+ REG_EXT_CONTROLLER_CAPABILITIES = 0x0C,
+ REG_CONTROLLER_PID = 0x10,
+ REG_CONTROLLER_MID = 0x14,
+ REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
+ REG_INTERRUPT_STATUS = 0x20,
+ REG_INTERRUPT_ENABLE = 0x24,
+ REG_CONTROLLER_STATUS = 0x30,
+ REG_CONTROLLER_ENABLE = 0x34,
+ REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
+ REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
+ REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
+ REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
+ REG_UIC_ERROR_CODE_DME = 0x48,
+ REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
+ REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
+ REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
+ REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
+ REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
+ REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
+ REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
+ REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
+ REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
+ REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
+ REG_UIC_COMMAND = 0x90,
+ REG_UIC_COMMAND_ARG_1 = 0x94,
+ REG_UIC_COMMAND_ARG_2 = 0x98,
+ REG_UIC_COMMAND_ARG_3 = 0x9C,
+
+ UFSHCI_REG_SPACE_SIZE = 0xA0,
+
+ REG_UFS_CCAP = 0x100,
+ REG_UFS_CRYPTOCAP = 0x104,
+
+ REG_UFS_MEM_CFG = 0x300,
+ REG_UFS_MCQ_CFG = 0x380,
+ REG_UFS_ESILBA = 0x384,
+ REG_UFS_ESIUBA = 0x388,
+ UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
+};
+
+/* Controller capability masks */
+enum {
+ MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F,
+ MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF,
+ MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00,
+ MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
+ MASK_EHSLUTRD_SUPPORTED = 0x00400000,
+ MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
+ MASK_64_ADDRESSING_SUPPORT = 0x01000000,
+ MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
+ MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
+ MASK_CRYPTO_SUPPORT = 0x10000000,
+ MASK_LSDB_SUPPORT = 0x20000000,
+ MASK_MCQ_SUPPORT = 0x40000000,
+};
+
+/* MCQ capability mask */
+enum {
+ MASK_EXT_IID_SUPPORT = 0x00000400,
+};
+
+enum {
+ REG_SQATTR = 0x0,
+ REG_SQLBA = 0x4,
+ REG_SQUBA = 0x8,
+ REG_SQDAO = 0xC,
+ REG_SQISAO = 0x10,
+
+ REG_CQATTR = 0x20,
+ REG_CQLBA = 0x24,
+ REG_CQUBA = 0x28,
+ REG_CQDAO = 0x2C,
+ REG_CQISAO = 0x30,
+};
+
+enum {
+ REG_SQHP = 0x0,
+ REG_SQTP = 0x4,
+ REG_SQRTC = 0x8,
+ REG_SQCTI = 0xC,
+ REG_SQRTS = 0x10,
+};
+
+enum {
+ REG_CQHP = 0x0,
+ REG_CQTP = 0x4,
+};
+
+enum {
+ REG_CQIS = 0x0,
+ REG_CQIE = 0x4,
+};
+
+enum {
+ SQ_START = 0x0,
+ SQ_STOP = 0x1,
+ SQ_ICU = 0x2,
+};
+
+enum {
+ SQ_STS = 0x1,
+ SQ_CUS = 0x2,
+};
+
+#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
+#define UFS_MASK(mask, offset) ((mask) << (offset))
+
+/* UFS Version 08h */
+#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
+#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
+
+/* Controller UFSHCI version */
+enum {
+ UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
+ UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
+ UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
+ UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
+ UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
+ UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
+ UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
+};
+
+/*
+ * IS - Interrupt Status - 20h
+ */
+#define UTP_TRANSFER_REQ_COMPL 0x1
+#define UIC_DME_END_PT_RESET 0x2
+#define UIC_ERROR 0x4
+#define UIC_TEST_MODE 0x8
+#define UIC_POWER_MODE 0x10
+#define UIC_HIBERNATE_EXIT 0x20
+#define UIC_HIBERNATE_ENTER 0x40
+#define UIC_LINK_LOST 0x80
+#define UIC_LINK_STARTUP 0x100
+#define UTP_TASK_REQ_COMPL 0x200
+#define UIC_COMMAND_COMPL 0x400
+#define DEVICE_FATAL_ERROR 0x800
+#define CONTROLLER_FATAL_ERROR 0x10000
+#define SYSTEM_BUS_FATAL_ERROR 0x20000
+#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
+#define MCQ_CQ_EVENT_STATUS 0x100000
+
+#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
+ UIC_HIBERNATE_EXIT)
+
+#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
+ UIC_POWER_MODE)
+
+#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
+
+#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
+
+#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
+ CONTROLLER_FATAL_ERROR |\
+ SYSTEM_BUS_FATAL_ERROR |\
+ CRYPTO_ENGINE_FATAL_ERROR |\
+ UIC_LINK_LOST)
+
+/* HCS - Host Controller Status 30h */
+#define DEVICE_PRESENT 0x1
+#define UTP_TRANSFER_REQ_LIST_READY 0x2
+#define UTP_TASK_REQ_LIST_READY 0x4
+#define UIC_COMMAND_READY 0x8
+#define HOST_ERROR_INDICATOR 0x10
+#define DEVICE_ERROR_INDICATOR 0x20
+#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
+
+#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
+ UTP_TASK_REQ_LIST_READY |\
+ UIC_COMMAND_READY)
+
+enum {
+ PWR_OK = 0x0,
+ PWR_LOCAL = 0x01,
+ PWR_REMOTE = 0x02,
+ PWR_BUSY = 0x03,
+ PWR_ERROR_CAP = 0x04,
+ PWR_FATAL_ERROR = 0x05,
+};
+
+/* HCE - Host Controller Enable 34h */
+#define CONTROLLER_ENABLE 0x1
+#define CONTROLLER_DISABLE 0x0
+#define CRYPTO_GENERAL_ENABLE 0x2
+
+/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
+#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
+#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
+#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
+#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
+
+/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
+#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
+#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
+#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
+#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
+#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
+#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
+#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
+#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
+#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
+
+/* UECN - Host UIC Error Code Network Layer 40h */
+#define UIC_NETWORK_LAYER_ERROR 0x80000000
+#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
+#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
+#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
+#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
+
+/* UECT - Host UIC Error Code Transport Layer 44h */
+#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
+#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
+#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
+#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
+#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
+#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
+#define UIC_TRANSPORT_BAD_TC 0x10
+#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
+#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
+
+/* UECDME - Host UIC Error Code DME 48h */
+#define UIC_DME_ERROR 0x80000000
+#define UIC_DME_ERROR_CODE_MASK 0x1
+
+/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
+#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
+#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
+#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
+#define INT_AGGR_STATUS_BIT 0x100000
+#define INT_AGGR_PARAM_WRITE 0x1000000
+#define INT_AGGR_ENABLE 0x80000000
+
+/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
+#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
+
+/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
+#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
+
+/* REG_UFS_MEM_CFG - Global Config Registers 300h */
+#define MCQ_MODE_SELECT BIT(0)
+
+/* CQISy - CQ y Interrupt Status Register */
+#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
+
+/* UICCMD - UIC Command */
+#define COMMAND_OPCODE_MASK 0xFF
+#define GEN_SELECTOR_INDEX_MASK 0xFFFF
+
+#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
+#define RESET_LEVEL 0xFF
+
+#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
+#define CFG_RESULT_CODE_MASK 0xFF
+#define GENERIC_ERROR_CODE_MASK 0xFF
+
+/* GenSelectorIndex calculation macros for M-PHY attributes */
+#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
+#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
+
+#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
+ ((sel) & 0xFFFF))
+#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
+#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
+#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
+
+/* Link Status*/
+enum link_status {
+ UFSHCD_LINK_IS_DOWN = 1,
+ UFSHCD_LINK_IS_UP = 2,
+};
+
+/* UIC Commands */
+enum uic_cmd_dme {
+ UIC_CMD_DME_GET = 0x01,
+ UIC_CMD_DME_SET = 0x02,
+ UIC_CMD_DME_PEER_GET = 0x03,
+ UIC_CMD_DME_PEER_SET = 0x04,
+ UIC_CMD_DME_POWERON = 0x10,
+ UIC_CMD_DME_POWEROFF = 0x11,
+ UIC_CMD_DME_ENABLE = 0x12,
+ UIC_CMD_DME_RESET = 0x14,
+ UIC_CMD_DME_END_PT_RST = 0x15,
+ UIC_CMD_DME_LINK_STARTUP = 0x16,
+ UIC_CMD_DME_HIBER_ENTER = 0x17,
+ UIC_CMD_DME_HIBER_EXIT = 0x18,
+ UIC_CMD_DME_TEST_MODE = 0x1A,
+};
+
+/* UIC Config result code / Generic error code */
+enum {
+ UIC_CMD_RESULT_SUCCESS = 0x00,
+ UIC_CMD_RESULT_INVALID_ATTR = 0x01,
+ UIC_CMD_RESULT_FAILURE = 0x01,
+ UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
+ UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
+ UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
+ UIC_CMD_RESULT_BAD_INDEX = 0x05,
+ UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
+ UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
+ UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
+ UIC_CMD_RESULT_BUSY = 0x09,
+ UIC_CMD_RESULT_DME_FAILURE = 0x0A,
+};
+
+#define MASK_UIC_COMMAND_RESULT 0xFF
+
+#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
+#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
+
+/*
+ * Request Descriptor Definitions
+ */
+
+/* To accommodate UFS2.0 required Command type */
+enum {
+ UTP_CMD_TYPE_UFS_STORAGE = 0x1,
+};
+
+enum {
+ UTP_SCSI_COMMAND = 0x00000000,
+ UTP_REQ_DESC_INT_CMD = 0x01000000,
+ UTP_NATIVE_UFS_COMMAND = 0x10000000,
+ UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
+};
+
+/* UTP Transfer Request Data Direction (DD) */
+enum utp_data_direction {
+ UTP_NO_DATA_TRANSFER = 0,
+ UTP_HOST_TO_DEVICE = 1,
+ UTP_DEVICE_TO_HOST = 2,
+};
+
+/* Overall command status values */
+enum utp_ocs {
+ OCS_SUCCESS = 0x0,
+ OCS_INVALID_CMD_TABLE_ATTR = 0x1,
+ OCS_INVALID_PRDT_ATTR = 0x2,
+ OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
+ OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
+ OCS_PEER_COMM_FAILURE = 0x5,
+ OCS_ABORTED = 0x6,
+ OCS_FATAL_ERROR = 0x7,
+ OCS_DEVICE_FATAL_ERROR = 0x8,
+ OCS_INVALID_CRYPTO_CONFIG = 0x9,
+ OCS_GENERAL_CRYPTO_ERROR = 0xA,
+ OCS_INVALID_COMMAND_STATUS = 0x0F,
+};
+
+enum {
+ MASK_OCS = 0x0F,
+};
+
+/* The maximum length of the data byte count field in the PRDT is 256KB */
+#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
+/* The granularity of the data byte count field in the PRDT is 32-bit */
+#define PRDT_DATA_BYTE_COUNT_PAD 4
+
+
+struct ufshcd_sg_entry {
+ __le32 base_addr;
+ __le32 upper_addr;
+ __le32 reserved;
+ __le32 size;
+};
+
+#define MAX_BUFF 128
+/**
+ * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
+ * @command_upiu: Command UPIU Frame address
+ * @response_upiu: Response UPIU Frame address
+ * @prd_table: Physical Region Descriptor
+ */
+struct utp_transfer_cmd_desc {
+ u8 command_upiu[ALIGNED_UPIU_SIZE];
+ u8 response_upiu[ALIGNED_UPIU_SIZE];
+ struct ufshcd_sg_entry prd_table[MAX_BUFF];
+};
+
+/**
+ * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
+ * @dword0: Descriptor Header DW0
+ * @dword1: Descriptor Header DW1
+ * @dword2: Descriptor Header DW2
+ * @dword3: Descriptor Header DW3
+ */
+struct request_desc_header {
+ __le32 dword_0;
+ __le32 dword_1;
+ __le32 dword_2;
+ __le32 dword_3;
+};
+
+/**
+ * struct utp_transfer_req_desc - UTRD structure
+ * @header: UTRD header DW-0 to DW-3
+ * @command_desc_base_addr_lo: UCD base address low DW-4
+ * @command_desc_base_addr_hi: UCD base address high DW-5
+ * @response_upiu_length: response UPIU length DW-6
+ * @response_upiu_offset: response UPIU offset DW-6
+ * @prd_table_length: Physical region descriptor length DW-7
+ * @prd_table_offset: Physical region descriptor offset DW-7
+ */
+struct utp_transfer_req_desc {
+ /* DW 0-3 */
+ struct request_desc_header header;
+
+ /* DW 4-5*/
+ __le32 command_desc_base_addr_lo;
+ __le32 command_desc_base_addr_hi;
+
+ /* DW 6 */
+ __le16 response_upiu_length;
+ __le16 response_upiu_offset;
+
+ /* DW 7 */
+ __le16 prd_table_length;
+ __le16 prd_table_offset;
+};
+
+/**
+ * struct utp_upiu_header - UPIU header structure
+ * @dword_0: UPIU header DW-0
+ * @dword_1: UPIU header DW-1
+ * @dword_2: UPIU header DW-2
+ */
+struct utp_upiu_header {
+ __be32 dword_0;
+ __be32 dword_1;
+ __be32 dword_2;
+};
+
+/*
+ * UTMRD structure.
+ */
+struct utp_task_req_desc {
+ /* DW 0-3 */
+ struct request_desc_header header;
+
+ /* DW 4-11 - Task request UPIU structure */
+ struct utp_upiu_header req_header;
+ __be32 input_param1;
+ __be32 input_param2;
+ __be32 input_param3;
+ __be32 __reserved1[2];
+
+ /* DW 12-19 - Task Management Response UPIU structure */
+ struct utp_upiu_header rsp_header;
+ __be32 output_param1;
+ __be32 output_param2;
+ __be32 __reserved2[3];
+};
+
+#endif
diff --git a/drivers/ufs/unipro.h b/drivers/ufs/unipro.h
index 6df953e..5683360 100644
--- a/drivers/ufs/unipro.h
+++ b/drivers/ufs/unipro.h
@@ -34,6 +34,18 @@
/*
* M-RX Configuration Attributes
*/
+#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
+#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
+#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
+#define RX_HIBERN8TIME_CAPABILITY 0x0092
+#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
+#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
+#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
+#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
+#define RX_ADV_GRANULARITY_CAP 0x0098
+#define RX_HIBERN8TIME_CAP 0x0092
+#define RX_ADV_HIBERN8TIME_CAP 0x0099
+#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
#define RX_MODE 0x00A1
#define RX_HSRATE_SERIES 0x00A2
#define RX_HSGEAR 0x00A3
@@ -42,24 +54,27 @@
#define RX_HS_UNTERMINATED_ENABLE 0x00A6
#define RX_ENTER_HIBERN8 0x00A7
#define RX_BYPASS_8B10B_ENABLE 0x00A8
-#define RX_TERMINATION_FORCE_ENABLE 0x0089
-#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
-#define RX_HIBERN8TIME_CAPABILITY 0x0092
+#define RX_TERMINATION_FORCE_ENABLE 0x00A9
+#define RXCALCTRL 0x00B4
+#define RXSQCTRL 0x00B5
+#define CFGRXCDR8 0x00BA
+#define CFGRXOVR8 0x00BD
+#define CFGRXOVR6 0x00BF
+#define RXDIRECTCTRL2 0x00C7
+#define CFGRXOVR4 0x00E9
#define RX_REFCLKFREQ 0x00EB
#define RX_CFGCLKFREQVAL 0x00EC
#define CFGWIDEINLN 0x00F0
-#define CFGRXCDR8 0x00BA
#define ENARXDIRECTCFG4 0x00F2
-#define CFGRXOVR8 0x00BD
-#define RXDIRECTCTRL2 0x00C7
#define ENARXDIRECTCFG3 0x00F3
-#define RXCALCTRL 0x00B4
#define ENARXDIRECTCFG2 0x00F4
-#define CFGRXOVR4 0x00E9
-#define RXSQCTRL 0x00B5
-#define CFGRXOVR6 0x00BF
-#define is_mphy_tx_attr(attr) (attr < RX_MODE)
+#define is_mphy_tx_attr(attr) ((attr) < RX_MODE)
+#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
+#define SYNC_LEN_FINE(x) ((x) & 0x3F)
+#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
+#define PREP_LEN(x) ((x) & 0xF)
+
#define RX_MIN_ACTIVATETIME_UNIT_US 100
#define HIBERN8TIME_UNIT_US 100
@@ -77,51 +92,54 @@
#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
-#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
+#define UNIPRO_CB_OFFSET(x) (0x8000 | (x))
/*
- * PHY Adpater attributes
+ * PHY Adapter attributes
*/
-#define PA_ACTIVETXDATALANES 0x1560
-#define PA_ACTIVERXDATALANES 0x1580
-#define PA_TXTRAILINGCLOCKS 0x1564
#define PA_PHY_TYPE 0x1500
#define PA_AVAILTXDATALANES 0x1520
-#define PA_AVAILRXDATALANES 0x1540
-#define PA_MINRXTRAILINGCLOCKS 0x1543
-#define PA_TXPWRSTATUS 0x1567
-#define PA_RXPWRSTATUS 0x1582
-#define PA_TXFORCECLOCK 0x1562
-#define PA_TXPWRMODE 0x1563
-#define PA_LEGACYDPHYESCDL 0x1570
#define PA_MAXTXSPEEDFAST 0x1521
#define PA_MAXTXSPEEDSLOW 0x1522
#define PA_MAXRXSPEEDFAST 0x1541
#define PA_MAXRXSPEEDSLOW 0x1542
#define PA_TXLINKSTARTUPHS 0x1544
+#define PA_AVAILRXDATALANES 0x1540
+#define PA_MINRXTRAILINGCLOCKS 0x1543
#define PA_LOCAL_TX_LCC_ENABLE 0x155E
+#define PA_ACTIVETXDATALANES 0x1560
+#define PA_CONNECTEDTXDATALANES 0x1561
+#define PA_TXFORCECLOCK 0x1562
+#define PA_TXPWRMODE 0x1563
+#define PA_TXTRAILINGCLOCKS 0x1564
#define PA_TXSPEEDFAST 0x1565
#define PA_TXSPEEDSLOW 0x1566
-#define PA_REMOTEVERINFO 0x15A0
+#define PA_TXPWRSTATUS 0x1567
#define PA_TXGEAR 0x1568
#define PA_TXTERMINATION 0x1569
#define PA_HSSERIES 0x156A
+#define PA_LEGACYDPHYESCDL 0x1570
#define PA_PWRMODE 0x1571
+#define PA_ACTIVERXDATALANES 0x1580
+#define PA_CONNECTEDRXDATALANES 0x1581
+#define PA_RXPWRSTATUS 0x1582
#define PA_RXGEAR 0x1583
#define PA_RXTERMINATION 0x1584
#define PA_MAXRXPWMGEAR 0x1586
#define PA_MAXRXHSGEAR 0x1587
-#define PA_RXHSUNTERMCAP 0x15A5
-#define PA_RXLSTERMCAP 0x15A6
-#define PA_GRANULARITY 0x15AA
#define PA_PACPREQTIMEOUT 0x1590
#define PA_PACPREQEOBTIMEOUT 0x1591
+#define PA_REMOTEVERINFO 0x15A0
+#define PA_LOGICALLANEMAP 0x15A1
+#define PA_SLEEPNOCONFIGTIME 0x15A2
+#define PA_STALLNOCONFIGTIME 0x15A3
+#define PA_SAVECONFIGTIME 0x15A4
+#define PA_RXHSUNTERMCAP 0x15A5
+#define PA_RXLSTERMCAP 0x15A6
#define PA_HIBERN8TIME 0x15A7
#define PA_LOCALVERINFO 0x15A9
+#define PA_GRANULARITY 0x15AA
#define PA_TACTIVATE 0x15A8
-#define PA_PACPFRAMECOUNT 0x15C0
-#define PA_PACPERRORCOUNT 0x15C1
-#define PA_PHYTESTCONTROL 0x15C2
#define PA_PWRMODEUSERDATA0 0x15B0
#define PA_PWRMODEUSERDATA1 0x15B1
#define PA_PWRMODEUSERDATA2 0x15B2
@@ -134,12 +152,9 @@
#define PA_PWRMODEUSERDATA9 0x15B9
#define PA_PWRMODEUSERDATA10 0x15BA
#define PA_PWRMODEUSERDATA11 0x15BB
-#define PA_CONNECTEDTXDATALANES 0x1561
-#define PA_CONNECTEDRXDATALANES 0x1581
-#define PA_LOGICALLANEMAP 0x15A1
-#define PA_SLEEPNOCONFIGTIME 0x15A2
-#define PA_STALLNOCONFIGTIME 0x15A3
-#define PA_SAVECONFIGTIME 0x15A4
+#define PA_PACPFRAMECOUNT 0x15C0
+#define PA_PACPERRORCOUNT 0x15C1
+#define PA_PHYTESTCONTROL 0x15C2
#define PA_TXHSADAPTTYPE 0x15D4
/* Adapt type for PA_TXHSADAPTTYPE attribute */
@@ -151,9 +166,9 @@
#define PA_HIBERN8_TIME_UNIT_US 100
/*Other attributes*/
+#define VS_POWERSTATE 0xD083
#define VS_MPHYCFGUPDT 0xD085
#define VS_DEBUGOMC 0xD09E
-#define VS_POWERSTATE 0xD083
#define VS_MPHYDISABLE 0xD0C1
#define PA_GRANULARITY_MIN_VAL 1
@@ -163,7 +178,7 @@
#define PA_MAXDATALANES 4
/* PA power modes */
-enum {
+enum ufs_pa_pwr_mode {
FAST_MODE = 1,
SLOW_MODE = 2,
FASTAUTO_MODE = 4,
@@ -171,8 +186,11 @@
UNCHANGED = 7,
};
+#define PWRMODE_MASK 0xF
+#define PWRMODE_RX_OFFSET 4
+
/* PA TX/RX Frequency Series */
-enum {
+enum ufs_hs_gear_rate {
PA_HS_MODE_A = 1,
PA_HS_MODE_B = 2,
};
@@ -193,14 +211,24 @@
UFS_HS_G1, /* HS Gear 1 (default for reset) */
UFS_HS_G2, /* HS Gear 2 */
UFS_HS_G3, /* HS Gear 3 */
+ UFS_HS_G4, /* HS Gear 4 */
+ UFS_HS_G5 /* HS Gear 5 */
+};
+
+enum ufs_lanes {
+ UFS_LANE_DONT_CHANGE, /* Don't change Lane */
+ UFS_LANE_1, /* Lane 1 (default for reset) */
+ UFS_LANE_2, /* Lane 2 */
};
enum ufs_unipro_ver {
UFS_UNIPRO_VER_RESERVED = 0,
UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
- UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
- UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */
+ UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
+ UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
+ UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
+ UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
/* UniPro version field mask in PA_LOCALVERINFO */
UFS_UNIPRO_VER_MASK = 0xF,
};
@@ -208,27 +236,27 @@
/*
* Data Link Layer Attributes
*/
+#define DL_TXPREEMPTIONCAP 0x2000
+#define DL_TC0TXMAXSDUSIZE 0x2001
+#define DL_TC0RXINITCREDITVAL 0x2002
+#define DL_TC1TXMAXSDUSIZE 0x2003
+#define DL_TC1RXINITCREDITVAL 0x2004
+#define DL_TC0TXBUFFERSIZE 0x2005
+#define DL_TC1TXBUFFERSIZE 0x2006
#define DL_TC0TXFCTHRESHOLD 0x2040
#define DL_FC0PROTTIMEOUTVAL 0x2041
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
#define DL_AFC0REQTIMEOUTVAL 0x2043
#define DL_AFC0CREDITTHRESHOLD 0x2044
#define DL_TC0OUTACKTHRESHOLD 0x2045
+#define DL_PEERTC0PRESENT 0x2046
+#define DL_PEERTC0RXINITCREVAL 0x2047
#define DL_TC1TXFCTHRESHOLD 0x2060
#define DL_FC1PROTTIMEOUTVAL 0x2061
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
#define DL_AFC1REQTIMEOUTVAL 0x2063
#define DL_AFC1CREDITTHRESHOLD 0x2064
#define DL_TC1OUTACKTHRESHOLD 0x2065
-#define DL_TXPREEMPTIONCAP 0x2000
-#define DL_TC0TXMAXSDUSIZE 0x2001
-#define DL_TC0RXINITCREDITVAL 0x2002
-#define DL_TC0TXBUFFERSIZE 0x2005
-#define DL_PEERTC0PRESENT 0x2046
-#define DL_PEERTC0RXINITCREVAL 0x2047
-#define DL_TC1TXMAXSDUSIZE 0x2003
-#define DL_TC1RXINITCREDITVAL 0x2004
-#define DL_TC1TXBUFFERSIZE 0x2006
#define DL_PEERTC1PRESENT 0x2066
#define DL_PEERTC1RXINITCREVAL 0x2067
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b6149..1d5e4af 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -49,6 +49,13 @@
Host controller is compliant with XHCI so it will use
standard XHCI driver.
+config USB_CDNS3_STARFIVE
+ tristate "Cadence USB3 support on Starfive platforms"
+ default y if STARFIVE_JH7110
+ help
+ Say 'Y' here if you are building for Starfive platforms
+ that contain Cadence USB3 controller core. E.g.: JH7110.
+
config USB_CDNS3_TI
tristate "Cadence USB3 support on TI platforms"
default USB_CDNS3
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index d604785..1f00f23 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -8,4 +8,5 @@
cdns3-$(CONFIG_$(XPL_)USB_CDNS3_HOST) += host.o
+obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 0000000..78ceb83
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/usb/otg.h>
+#include <malloc.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST BIT(19)
+#define USB_SUSPENDM_MASK BIT(19)
+
+#define USB_MISC_CFG_MASK GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS BIT(20)
+#define USB_PLL_EN BIT(22)
+#define USB_REFCLK_MODE BIT(23)
+
+struct cdns_starfive {
+ struct udevice *dev;
+ struct regmap *stg_syscon;
+ struct reset_ctl_bulk resets;
+ struct clk_bulk clks;
+ u32 stg_usb_mode;
+ enum usb_dr_mode mode;
+};
+
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+ unsigned int strap, suspendm;
+
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_MISC_CFG_MASK,
+ USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ strap = USB_STRAP_HOST;
+ suspendm = USB_SUSPENDM_HOST;
+ break;
+ case USB_DR_MODE_PERIPHERAL:
+ strap = USB_STRAP_DEVICE;
+ suspendm = 0;
+ break;
+ default:
+ return;
+ }
+
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_SUSPENDM_MASK | USB_STRAP_MASK,
+ strap | suspendm);
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+ reset_assert_bulk(&data->resets);
+ clk_disable_bulk(&data->clks);
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = clk_get_bulk(data->dev, &data->clks);
+ if (ret)
+ return ret;
+
+ ret = reset_get_bulk(data->dev, &data->resets);
+ if (ret)
+ goto err_clk;
+
+ ret = clk_enable_bulk(&data->clks);
+ if (ret) {
+ dev_err(data->dev, "clk enable failed: %d\n", ret);
+ goto err_en_clk;
+ }
+
+ ret = reset_deassert_bulk(&data->resets);
+ if (ret) {
+ dev_err(data->dev, "reset deassert failed: %d\n", ret);
+ goto err_reset;
+ }
+
+ return 0;
+
+err_reset:
+ clk_disable_bulk(&data->clks);
+err_en_clk:
+ reset_release_bulk(&data->resets);
+err_clk:
+ clk_release_bulk(&data->clks);
+
+ return ret;
+}
+
+static int cdns_starfive_get_syscon(struct cdns_starfive *data)
+{
+ struct ofnode_phandle_args phandle;
+ int ret;
+
+ ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0,
+ &phandle);
+ if (ret < 0) {
+ dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ data->stg_syscon = syscon_node_to_regmap(phandle.node);
+ if (IS_ERR(data->stg_syscon)) {
+ dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon));
+ return PTR_ERR(data->stg_syscon);
+ }
+
+ data->stg_usb_mode = phandle.args[0];
+
+ return 0;
+}
+
+static int cdns_starfive_probe(struct udevice *dev)
+{
+ struct cdns_starfive *data = dev_get_plat(dev);
+ enum usb_dr_mode dr_mode;
+ int ret;
+
+ data->dev = dev;
+
+ ret = cdns_starfive_get_syscon(data);
+ if (ret)
+ return ret;
+
+ dr_mode = usb_get_dr_mode(dev_ofnode(dev));
+
+ data->mode = dr_mode;
+ ret = cdns_clk_rst_init(data);
+ if (ret) {
+ dev_err(data->dev, "clk reset failed: %d\n", ret);
+ return ret;
+ }
+ cdns_mode_init(data, dr_mode);
+
+ return 0;
+}
+
+static int cdns_starfive_remove(struct udevice *dev)
+{
+ struct cdns_starfive *data = dev_get_plat(dev);
+
+ cdns_clk_rst_deinit(data);
+ return 0;
+}
+
+static const struct udevice_id cdns_starfive_of_match[] = {
+ { .compatible = "starfive,jh7110-usb", },
+ {},
+};
+
+U_BOOT_DRIVER(cdns_starfive) = {
+ .name = "cdns-starfive",
+ .id = UCLASS_NOP,
+ .of_match = cdns_starfive_of_match,
+ .bind = cdns3_bind,
+ .probe = cdns_starfive_probe,
+ .remove = cdns_starfive_remove,
+ .plat_auto = sizeof(struct cdns_starfive),
+ .flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index 4cfd38e..4434dc1 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -410,6 +410,9 @@
name = ofnode_get_name(node);
dr_mode = usb_get_dr_mode(node);
+ if (dr_mode == USB_DR_MODE_UNKNOWN)
+ dr_mode = usb_get_dr_mode(dev_ofnode(parent));
+
switch (dr_mode) {
#if defined(CONFIG_SPL_USB_HOST) || \
(!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
index 47874fe..cbb1334 100644
--- a/drivers/usb/cdns3/drd.c
+++ b/drivers/usb/cdns3/drd.c
@@ -217,15 +217,19 @@
int cdns3_drd_update_mode(struct cdns3 *cdns)
{
int ret = 0;
+ int mode;
switch (cdns->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
+ mode = PHY_MODE_USB_DEVICE;
ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
break;
case USB_DR_MODE_HOST:
+ mode = PHY_MODE_USB_HOST;
ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
break;
case USB_DR_MODE_OTG:
+ mode = PHY_MODE_USB_OTG;
ret = cdns3_init_otg_mode(cdns);
break;
default:
@@ -234,6 +238,16 @@
return -EINVAL;
}
+ ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
+ if (ret) {
+ dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
+ return ret;
+ }
+
+ ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
+ if (ret)
+ dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
+
return ret;
}
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index e5a3834..477ecd0 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1631,8 +1631,25 @@
return dwc3_find_ep(gadget, "ep1in");
if (usb_endpoint_is_bulk_out(desc))
return dwc3_find_ep(gadget, "ep2out");
- if (usb_endpoint_is_int_in(desc))
+ if (usb_endpoint_is_int_in(desc)) {
+ /*
+ * Special workaround for NXP UUU tool in SPL.
+ *
+ * The tool excepts the interrupt-in endpoint to be ep1in,
+ * otherwise it crashes. This is a result of the previous
+ * hard-coded EP setup in drivers/usb/gadget/epautoconf.c
+ * which did special-case EP allocation for SPL builds,
+ * and which was since converted to this callback, but
+ * without the special-case EP allocation in SPL part.
+ *
+ * This reinstates the SPL part in an isolated manner,
+ * only for NXP iMX SoCs, only for SPL builds, and only
+ * for the ep1in interrupt-in endpoint.
+ */
+ if (IS_ENABLED(CONFIG_MACH_IMX) && IS_ENABLED(CONFIG_XPL_BUILD))
+ return dwc3_find_ep(gadget, "ep1in");
return dwc3_find_ep(gadget, "ep3in");
+ }
return NULL;
}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b1ef73f..df60730 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -293,27 +293,6 @@
source "drivers/video/fonts/Kconfig"
-config VIDCONSOLE_AS_LCD
- bool "Use 'vidconsole' when CONFIG_VIDCONSOLE_AS_NAME string is seen in stdout"
- help
- This is a work-around for boards which have 'lcd' or 'vga' in their
- stdout environment variable, but have moved to use driver model for
- video. In this case the console will no-longer work. While it is
- possible to update the environment, the breakage may be confusing for
- users. This option will be removed around the end of 2020.
-
-config VIDCONSOLE_AS_NAME
- string "Use 'vidconsole' when string defined here is seen in stdout"
- depends on VIDCONSOLE_AS_LCD
- default "lcd" if LCD || TEGRA_COMMON
- default "vga" if !LCD
- help
- This is a work-around for boards which have 'lcd' or 'vga' in their
- stdout environment variable, but have moved to use driver model for
- video. In this case the console will no-longer work. While it is
- possible to update the environment, the breakage may be confusing for
- users. This option will be removed around the end of 2020.
-
config VIDEO_BOCHS
bool "Enable Bochs video emulation for QEMU"
help
@@ -721,6 +700,12 @@
help
This enables library for accessing EDID data from an LCD panel.
+config I2C_EDID_STANDARD
+ bool "Enable standard timings EDID library expansion"
+ depends on I2C_EDID
+ help
+ This enables standard timings expansion for EDID data from an LCD panel.
+
config DISPLAY
bool "Enable Display support"
depends on DM
diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig
index 21c5a04..be53034 100644
--- a/drivers/video/bridge/Kconfig
+++ b/drivers/video/bridge/Kconfig
@@ -9,7 +9,7 @@
config VIDEO_BRIDGE_PARADE_DP501
bool "Support Parade DP501 DP & DVI/HDMI dual mode transmitter"
- depends on PANEL && DM_GPIO
+ depends on VIDEO_BRIDGE && PANEL && DM_GPIO
select DM_I2C
help
The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It
@@ -46,14 +46,14 @@
config VIDEO_BRIDGE_SOLOMON_SSD2825
bool "Solomon SSD2825 bridge driver"
- depends on PANEL && DM_GPIO
+ depends on VIDEO_BRIDGE && PANEL && DM_GPIO
select VIDEO_MIPI_DSI
help
- Solomon SSD2824 SPI RGB-DSI bridge driver wrapped into panel uClass.
+ Solomon SSD2824 SPI RGB-DSI bridge driver.
config VIDEO_BRIDGE_TOSHIBA_TC358768
bool "Support Toshiba TC358768 MIPI DSI bridge"
- depends on PANEL && DM_GPIO
+ depends on VIDEO_BRIDGE && PANEL && DM_GPIO
select VIDEO_MIPI_DSI
select DM_I2C
help
diff --git a/drivers/video/bridge/dp501.c b/drivers/video/bridge/dp501.c
index 095e3e7..9937cfe 100644
--- a/drivers/video/bridge/dp501.c
+++ b/drivers/video/bridge/dp501.c
@@ -9,6 +9,7 @@
#include <log.h>
#include <backlight.h>
#include <panel.h>
+#include <video_bridge.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <power/regulator.h>
@@ -206,7 +207,6 @@
struct udevice *chip2;
struct udevice *vdd;
- struct gpio_desc reset_gpio;
struct gpio_desc enable_gpio;
};
@@ -484,16 +484,19 @@
return 0;
}
-static void dp501_hw_init(struct dp501_priv *priv)
+static void dp501_hw_init(struct udevice *dev)
{
- dm_gpio_set_value(&priv->reset_gpio, 1);
+ struct dp501_priv *priv = dev_get_priv(dev);
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ dm_gpio_set_value(&uc_priv->reset, 1);
regulator_set_enable_if_allowed(priv->vdd, 1);
dm_gpio_set_value(&priv->enable_gpio, 1);
udelay(100);
- dm_gpio_set_value(&priv->reset_gpio, 0);
+ dm_gpio_set_value(&uc_priv->reset, 0);
mdelay(80);
}
@@ -521,14 +524,6 @@
}
/* get gpios */
- ret = gpio_request_by_name(dev, "reset-gpios", 0,
- &priv->reset_gpio, GPIOD_IS_OUT);
- if (ret) {
- log_debug("%s: Could not decode reset-gpios (%d)\n",
- __func__, ret);
- return ret;
- }
-
ret = gpio_request_by_name(dev, "enable-gpios", 0,
&priv->enable_gpio, GPIOD_IS_OUT);
if (ret) {
@@ -544,7 +539,7 @@
return ret;
}
- dp501_hw_init(priv);
+ dp501_hw_init(dev);
/* get EDID */
return panel_get_display_timing(priv->panel, &priv->timing);
@@ -558,8 +553,8 @@
return dp501_setup(dev);
}
-struct panel_ops dp501_ops = {
- .enable_backlight = dp501_attach,
+static const struct video_bridge_ops dp501_ops = {
+ .attach = dp501_attach,
.set_backlight = dp501_set_backlight,
.get_display_timing = dp501_panel_timings,
};
@@ -571,7 +566,7 @@
U_BOOT_DRIVER(dp501) = {
.name = "dp501",
- .id = UCLASS_PANEL,
+ .id = UCLASS_VIDEO_BRIDGE,
.of_match = dp501_ids,
.ops = &dp501_ops,
.probe = dp501_probe,
diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c
index f978021..a307993 100644
--- a/drivers/video/bridge/ssd2825.c
+++ b/drivers/video/bridge/ssd2825.c
@@ -5,12 +5,15 @@
#include <clk.h>
#include <dm.h>
+#include <dm/ofnode_graph.h>
#include <log.h>
#include <misc.h>
#include <mipi_display.h>
#include <mipi_dsi.h>
#include <backlight.h>
+#include <video_bridge.h>
#include <panel.h>
+#include <power/regulator.h>
#include <spi.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -106,6 +109,10 @@
#define SSD2825_LP_MIN_CLK 5000 /* KHz */
#define SSD2825_REF_MIN_CLK 2000 /* KHz */
+static const char * const ssd2825_supplies[] = {
+ "dvdd-supply", "avdd-supply", "vddio-supply"
+};
+
struct ssd2825_bridge_priv {
struct mipi_dsi_host host;
struct mipi_dsi_device device;
@@ -113,12 +120,16 @@
struct udevice *panel;
struct display_timing timing;
+ struct udevice *supplies[ARRAY_SIZE(ssd2825_supplies)];
+
struct gpio_desc power_gpio;
- struct gpio_desc reset_gpio;
struct clk *tx_clk;
u32 pll_freq_kbps; /* PLL in kbps */
+
+ u32 hzd; /* HS Zero Delay in ns */
+ u32 hpd; /* HS Prepare Delay is ns */
};
static int ssd2825_spi_write(struct udevice *dev, int reg,
@@ -231,7 +242,6 @@
const struct mipi_dsi_msg *msg)
{
struct udevice *dev = (struct udevice *)host->dev;
- u8 buf = *(u8 *)msg->tx_buf;
u16 config;
int ret;
@@ -260,15 +270,6 @@
ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
ssd2825_write_dsi(dev, msg->tx_buf, msg->tx_len);
- if (buf == MIPI_DCS_SET_DISPLAY_ON) {
- ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG,
- SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN |
- SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD |
- SSD2825_CONF_REG_EOT);
- ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001);
- ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
- }
-
return 0;
}
@@ -312,9 +313,14 @@
struct mipi_dsi_device *device = &priv->device;
struct display_timing *dt = &priv->timing;
u16 pll_config, lp_div;
+ u32 nibble_delay, nibble_freq_khz;
u32 pclk_mult, tx_freq_khz, pd_lines;
+ u8 hzd, hpd;
tx_freq_khz = clk_get_rate(priv->tx_clk) / 1000;
+ if (!tx_freq_khz || tx_freq_khz < 0)
+ tx_freq_khz = SSD2825_REF_MIN_CLK;
+
pd_lines = mipi_dsi_pixel_format_to_bpp(device->format);
pclk_mult = pd_lines / device->lanes + 1;
@@ -324,12 +330,19 @@
lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8);
+ /* nibble_delay in nanoseconds */
+ nibble_freq_khz = priv->pll_freq_kbps / 4;
+ nibble_delay = 1000 * 1000 / nibble_freq_khz;
+
+ hzd = priv->hzd / nibble_delay;
+ hpd = (priv->hpd - 4 * nibble_delay) / nibble_delay;
+
/* Disable PLL */
ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0000);
ssd2825_write_register(dev, SSD2825_LINE_CTRL_REG, 0x0001);
/* Set delays */
- ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, 0x2103);
+ ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd);
/* Set PLL coeficients */
ssd2825_write_register(dev, SSD2825_PLL_CONFIGURATION_REG, pll_config);
@@ -343,11 +356,30 @@
ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
}
-static int ssd2825_bridge_enable_panel(struct udevice *dev)
+static int ssd2825_bridge_attach(struct udevice *dev)
{
struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
struct mipi_dsi_device *device = &priv->device;
struct display_timing *dt = &priv->timing;
+ u8 pixel_format;
+ int ret;
+
+ /* Set pixel format */
+ switch (device->format) {
+ case MIPI_DSI_FMT_RGB565:
+ pixel_format = 0x00;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ pixel_format = 0x01;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ pixel_format = 0x02;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ pixel_format = 0x03;
+ break;
+ }
/* Perform SW reset */
ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100);
@@ -367,7 +399,7 @@
ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_6,
SSD2825_HSYNC_HIGH | SSD2825_VSYNC_HIGH |
SSD2825_PCKL_HIGH | SSD2825_NON_BURST |
- (3 - device->format));
+ pixel_format);
ssd2825_write_register(dev, SSD2825_LANE_CONFIGURATION_REG,
device->lanes - 1);
ssd2825_write_register(dev, SSD2825_TEST_REG, 0x0004);
@@ -384,7 +416,18 @@
ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
/* Perform panel setup */
- return panel_enable_backlight(priv->panel);
+ ret = panel_enable_backlight(priv->panel);
+ if (ret)
+ return ret;
+
+ ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG,
+ SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN |
+ SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD |
+ SSD2825_CONF_REG_EOT);
+ ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001);
+ ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
+
+ return 0;
}
static int ssd2825_bridge_set_panel(struct udevice *dev, int percent)
@@ -407,7 +450,8 @@
static int ssd2825_bridge_hw_init(struct udevice *dev)
{
struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
- int ret;
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+ int i, ret;
ret = clk_prepare_enable(priv->tx_clk);
if (ret) {
@@ -416,25 +460,28 @@
return ret;
}
- ret = dm_gpio_set_value(&priv->power_gpio, 1);
- if (ret) {
- log_debug("%s: error changing power-gpios (%d)\n",
- __func__, ret);
- return ret;
+ /* enable supplies */
+ for (i = 0; i < ARRAY_SIZE(ssd2825_supplies); i++) {
+ ret = regulator_set_enable_if_allowed(priv->supplies[i], 1);
+ if (ret) {
+ log_debug("%s: cannot enable %s %d\n", __func__,
+ ssd2825_supplies[i], ret);
+ return ret;
+ }
}
mdelay(10);
- ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ ret = dm_gpio_set_value(&uc_priv->reset, 1);
if (ret) {
- log_debug("%s: error changing reset-gpios (%d)\n",
+ log_debug("%s: error entering reset (%d)\n",
__func__, ret);
return ret;
}
mdelay(10);
- ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ ret = dm_gpio_set_value(&uc_priv->reset, 0);
if (ret) {
- log_debug("%s: error changing reset-gpios (%d)\n",
+ log_debug("%s: error exiting reset (%d)\n",
__func__, ret);
return ret;
}
@@ -443,13 +490,33 @@
return 0;
}
+static int ssd2825_bridge_get_panel(struct udevice *dev)
+{
+ struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
+ int i, ret;
+
+ u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+ for (i = 0; i < num; i++) {
+ ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
+ &priv->panel);
+ if (!ret)
+ return 0;
+ }
+
+ /* If this point is reached, no panels were found */
+ return -ENODEV;
+}
+
static int ssd2825_bridge_probe(struct udevice *dev)
{
struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
struct spi_slave *slave = dev_get_parent_priv(dev);
struct mipi_dsi_device *device = &priv->device;
struct mipi_dsi_panel_plat *mipi_plat;
- int ret;
+ int i, ret;
ret = spi_claim_bus(slave);
if (ret) {
@@ -457,10 +524,9 @@
return ret;
}
- ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
- "panel", &priv->panel);
+ ret = ssd2825_bridge_get_panel(dev);
if (ret) {
- log_err("cannot get panel: ret=%d\n", ret);
+ log_debug("%s: panel not found, ret %d\n", __func__, ret);
return ret;
}
@@ -477,33 +543,33 @@
device->format = mipi_plat->format;
device->mode_flags = mipi_plat->mode_flags;
- /* get panel gpios */
- ret = gpio_request_by_name(dev, "power-gpios", 0,
- &priv->power_gpio, GPIOD_IS_OUT);
- if (ret) {
- log_err("could not decode power-gpios (%d)\n", ret);
- return ret;
+ /* get supplies */
+ for (i = 0; i < ARRAY_SIZE(ssd2825_supplies); i++) {
+ ret = device_get_supply_regulator(dev, ssd2825_supplies[i],
+ &priv->supplies[i]);
+ if (ret) {
+ log_debug("%s: cannot get %s %d\n", __func__,
+ ssd2825_supplies[i], ret);
+ if (ret != -ENOENT)
+ return log_ret(ret);
+ }
}
- ret = gpio_request_by_name(dev, "reset-gpios", 0,
- &priv->reset_gpio, GPIOD_IS_OUT);
- if (ret) {
- log_err("could not decode reset-gpios (%d)\n", ret);
- return ret;
- }
-
/* get clk */
- priv->tx_clk = devm_clk_get(dev, "tx_clk");
+ priv->tx_clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(priv->tx_clk)) {
log_err("cannot get tx_clk: %ld\n", PTR_ERR(priv->tx_clk));
return PTR_ERR(priv->tx_clk);
}
+ priv->hzd = dev_read_u32_default(dev, "solomon,hs-zero-delay-ns", 133);
+ priv->hpd = dev_read_u32_default(dev, "solomon,hs-prep-delay-ns", 40);
+
return ssd2825_bridge_hw_init(dev);
}
-static const struct panel_ops ssd2825_bridge_ops = {
- .enable_backlight = ssd2825_bridge_enable_panel,
+static const struct video_bridge_ops ssd2825_bridge_ops = {
+ .attach = ssd2825_bridge_attach,
.set_backlight = ssd2825_bridge_set_panel,
.get_display_timing = ssd2825_bridge_panel_timings,
};
@@ -515,9 +581,10 @@
U_BOOT_DRIVER(ssd2825) = {
.name = "ssd2825",
- .id = UCLASS_PANEL,
+ .id = UCLASS_VIDEO_BRIDGE,
.of_match = ssd2825_bridge_ids,
.ops = &ssd2825_bridge_ops,
+ .bind = dm_scan_fdt_dev,
.probe = ssd2825_bridge_probe,
.priv_auto = sizeof(struct ssd2825_bridge_priv),
};
diff --git a/drivers/video/bridge/tc358768.c b/drivers/video/bridge/tc358768.c
index 19b6ca2..358004f 100644
--- a/drivers/video/bridge/tc358768.c
+++ b/drivers/video/bridge/tc358768.c
@@ -6,12 +6,14 @@
#include <clk.h>
#include <dm.h>
+#include <dm/ofnode_graph.h>
#include <i2c.h>
#include <log.h>
#include <mipi_display.h>
#include <mipi_dsi.h>
#include <backlight.h>
#include <panel.h>
+#include <video_bridge.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/kernel.h>
@@ -122,6 +124,10 @@
#define NANO 1000000000UL
#define PICO 1000000000000ULL
+static const char * const tc358768_supplies[] = {
+ "vddc-supply", "vddmipi-supply", "vddio-supply"
+};
+
struct tc358768_priv {
struct mipi_dsi_host host;
struct mipi_dsi_device device;
@@ -129,9 +135,7 @@
struct udevice *panel;
struct display_timing timing;
- struct udevice *vddc;
- struct udevice *vddmipi;
- struct udevice *vddio;
+ struct udevice *supplies[ARRAY_SIZE(tc358768_supplies)];
struct clk *refclk;
@@ -265,25 +269,27 @@
tc358768_write(dev, TC358768_SYSCTL, 0);
}
-static void tc358768_hw_enable(struct tc358768_priv *priv)
+static void tc358768_hw_enable(struct udevice *dev)
{
+ struct tc358768_priv *priv = dev_get_priv(dev);
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
ret = clk_prepare_enable(priv->refclk);
if (ret)
log_debug("%s: error enabling refclk (%d)\n", __func__, ret);
- ret = regulator_set_enable_if_allowed(priv->vddc, true);
+ ret = regulator_set_enable_if_allowed(priv->supplies[0], true);
if (ret)
log_debug("%s: error enabling vddc (%d)\n", __func__, ret);
- ret = regulator_set_enable_if_allowed(priv->vddmipi, true);
+ ret = regulator_set_enable_if_allowed(priv->supplies[1], true);
if (ret)
log_debug("%s: error enabling vddmipi (%d)\n", __func__, ret);
mdelay(10);
- ret = regulator_set_enable_if_allowed(priv->vddio, true);
+ ret = regulator_set_enable_if_allowed(priv->supplies[2], true);
if (ret)
log_debug("%s: error enabling vddio (%d)\n", __func__, ret);
@@ -293,7 +299,7 @@
* The RESX is active low (GPIO_ACTIVE_LOW).
* DEASSERT (value = 0) the reset_gpio to enable the chip
*/
- ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ ret = dm_gpio_set_value(&uc_priv->reset, 0);
if (ret)
log_debug("%s: error changing reset-gpio (%d)\n", __func__, ret);
@@ -477,7 +483,7 @@
device->mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
}
- tc358768_hw_enable(priv);
+ tc358768_hw_enable(dev);
tc358768_sw_reset(dev);
tc358768_setup_pll(dev);
@@ -874,12 +880,33 @@
return 0;
}
+static int tc358768_get_panel(struct udevice *dev)
+{
+ struct tc358768_priv *priv = dev_get_priv(dev);
+ int i, ret;
+
+ u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+ for (i = 0; i < num; i++) {
+ ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
+ &priv->panel);
+ if (!ret)
+ return 0;
+ }
+
+ /* If this point is reached, no panels were found */
+ return -ENODEV;
+}
+
static int tc358768_setup(struct udevice *dev)
{
struct tc358768_priv *priv = dev_get_priv(dev);
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
struct mipi_dsi_device *device = &priv->device;
struct mipi_dsi_panel_plat *mipi_plat;
- int ret;
+ int i, ret;
/* The bridge uses 16 bit registers */
ret = i2c_set_chip_offset_len(dev, 2);
@@ -889,11 +916,10 @@
return ret;
}
- ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
- "panel", &priv->panel);
+ ret = tc358768_get_panel(dev);
if (ret) {
- log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret);
- return log_ret(ret);
+ log_debug("%s: panel not found, ret %d\n", __func__, ret);
+ return ret;
}
panel_get_display_timing(priv->panel, &priv->timing);
@@ -913,44 +939,26 @@
priv->dsi_lanes = device->lanes;
/* get regulators */
- ret = device_get_supply_regulator(dev, "vddc-supply", &priv->vddc);
- if (ret) {
- log_debug("%s: vddc regulator error: %d\n", __func__, ret);
- if (ret != -ENOENT)
- return log_ret(ret);
- }
-
- ret = device_get_supply_regulator(dev, "vddmipi-supply", &priv->vddmipi);
- if (ret) {
- log_debug("%s: vddmipi regulator error: %d\n", __func__, ret);
- if (ret != -ENOENT)
- return log_ret(ret);
- }
-
- ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
- if (ret) {
- log_debug("%s: vddio regulator error: %d\n", __func__, ret);
- if (ret != -ENOENT)
- return log_ret(ret);
+ for (i = 0; i < ARRAY_SIZE(tc358768_supplies); i++) {
+ ret = device_get_supply_regulator(dev, tc358768_supplies[i],
+ &priv->supplies[i]);
+ if (ret) {
+ log_debug("%s: cannot get %s %d\n", __func__,
+ tc358768_supplies[i], ret);
+ if (ret != -ENOENT)
+ return log_ret(ret);
+ }
}
/* get clk */
- priv->refclk = devm_clk_get(dev, "refclk");
+ priv->refclk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->refclk)) {
log_debug("%s: Could not get refclk: %ld\n",
__func__, PTR_ERR(priv->refclk));
return PTR_ERR(priv->refclk);
}
- /* get gpios */
- ret = gpio_request_by_name(dev, "reset-gpios", 0,
- &priv->reset_gpio, GPIOD_IS_OUT);
- if (ret) {
- log_debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret);
- return ret;
- }
-
- dm_gpio_set_value(&priv->reset_gpio, 1);
+ dm_gpio_set_value(&uc_priv->reset, 1);
return 0;
}
@@ -963,8 +971,8 @@
return tc358768_setup(dev);
}
-struct panel_ops tc358768_ops = {
- .enable_backlight = tc358768_attach,
+static const struct video_bridge_ops tc358768_ops = {
+ .attach = tc358768_attach,
.set_backlight = tc358768_set_backlight,
.get_display_timing = tc358768_panel_timings,
};
@@ -977,9 +985,10 @@
U_BOOT_DRIVER(tc358768) = {
.name = "tc358768",
- .id = UCLASS_PANEL,
+ .id = UCLASS_VIDEO_BRIDGE,
.of_match = tc358768_ids,
.ops = &tc358768_ops,
+ .bind = dm_scan_fdt_dev,
.probe = tc358768_probe,
.priv_auto = sizeof(struct tc358768_priv),
};
diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c
index d4ba4d8..9950ff8 100644
--- a/drivers/video/endeavoru-panel.c
+++ b/drivers/video/endeavoru-panel.c
@@ -117,6 +117,18 @@
struct endeavoru_panel_priv *priv = dev_get_priv(dev);
int ret;
+ /*
+ * Due to the use of the Tegra DC backlight feature, backlight
+ * requests MUST NOT be made during probe or earlier. This is
+ * because it creates a loop, as the backlight is a DC child.
+ */
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &priv->backlight);
+ if (ret) {
+ log_err("cannot get backlight: ret = %d\n", ret);
+ return ret;
+ }
+
ret = backlight_enable(priv->backlight);
if (ret)
return ret;
@@ -136,13 +148,6 @@
struct endeavoru_panel_priv *priv = dev_get_priv(dev);
int ret;
- ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
- "backlight", &priv->backlight);
- if (ret) {
- log_err("cannot get backlight: ret = %d\n", ret);
- return ret;
- }
-
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"vdd-supply", &priv->vdd);
if (ret) {
@@ -231,7 +236,7 @@
/* fill characteristics of DSI data link */
plat->lanes = 2;
plat->format = MIPI_DSI_FMT_RGB888;
- plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
return endeavoru_panel_hw_init(dev);
}
diff --git a/drivers/video/lg-ld070wx3.c b/drivers/video/lg-ld070wx3.c
index 610a06f..3676e45 100644
--- a/drivers/video/lg-ld070wx3.c
+++ b/drivers/video/lg-ld070wx3.c
@@ -158,7 +158,7 @@
/* fill characteristics of DSI data link */
plat->lanes = 4;
plat->format = MIPI_DSI_FMT_RGB888;
- plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
return lg_ld070wx3_hw_init(dev);
}
diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c
index 6b51fa0..7b87b6b 100644
--- a/drivers/video/lm3533_backlight.c
+++ b/drivers/video/lm3533_backlight.c
@@ -7,6 +7,7 @@
#include <backlight.h>
#include <dm.h>
+#include <dm/ofnode.h>
#include <i2c.h>
#include <log.h>
#include <linux/delay.h>
@@ -17,56 +18,79 @@
#define LM3533_BL_MAX_BRIGHTNESS 0xFF
#define LM3533_SINK_OUTPUT_CONFIG_1 0x10
-#define LM3533_CONTROL_BANK_A_PWM 0x14
+#define LM3533_CONTROL_PWM_BASE 0x14
+#define PWM_MAX GENMASK(5, 0)
#define LM3533_CONTROL_BANK_AB_BRIGHTNESS 0x1A
-#define LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT 0x1F
+#define LM3533_CONTROL_FULLSCALE_CURRENT_BASE 0x1F
+#define MAX_CURRENT_MIN 5000
+#define MAX_CURRENT_MAX 29800
+#define MAX_CURRENT_STEP 800
#define LM3533_CONTROL_BANK_ENABLE 0x27
#define LM3533_OVP_FREQUENCY_PWM_POLARITY 0x2C
+#define BOOST_OVP_MASK GENMASK(2, 1)
+#define BOOST_OVP_SHIFT 1
+#define BOOST_FREQ_MASK BIT(0)
+#define BOOST_FREQ_SHIFT 0
#define LM3533_BRIGHTNESS_REGISTER_A 0x40
+#define LM3533_BOOST_OVP_16V 16000000UL
+#define LM3533_BOOST_FREQ_500KHZ 500000UL
+
struct lm3533_backlight_priv {
struct gpio_desc enable_gpio;
u32 def_bl_lvl;
+
+ /* Core */
+ u32 boost_ovp;
+ u32 boost_freq;
+
+ /* Backlight */
+ u32 reg;
+ u16 max_current; /* 5000 - 29800 uA (800 uA step) */
+ u8 pwm; /* 0 - 0x3f */
+ bool linear;
+ bool hvled;
};
static int lm3533_backlight_enable(struct udevice *dev)
{
struct lm3533_backlight_priv *priv = dev_get_priv(dev);
+ u8 val, id = priv->reg;
int ret;
- dm_gpio_set_value(&priv->enable_gpio, 1);
- mdelay(5);
+ if (priv->linear) {
+ ret = dm_i2c_reg_clrset(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS,
+ BIT(2 * id + 1), BIT(2 * id + 1));
+ if (ret)
+ return ret;
+ }
- /* HVLED 1 & 2 are controlled by Bank A */
- ret = dm_i2c_reg_write(dev, LM3533_SINK_OUTPUT_CONFIG_1, 0x00);
- if (ret)
- return ret;
+ if (priv->hvled) {
+ ret = dm_i2c_reg_clrset(dev, LM3533_SINK_OUTPUT_CONFIG_1,
+ BIT(0) | BIT(1), id | id << 1);
+ if (ret)
+ return ret;
+ }
- /* PWM input is disabled for CABC */
- ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_PWM, 0x00);
- if (ret)
- return ret;
+ /* Set current */
+ if (priv->max_current < MAX_CURRENT_MIN || priv->max_current > MAX_CURRENT_MAX)
+ return -EINVAL;
- /* Linear & Control Bank A is configured for register Current control */
- ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS, 0x02);
+ val = (priv->max_current - MAX_CURRENT_MIN) / MAX_CURRENT_STEP;
+ ret = dm_i2c_reg_write(dev, LM3533_CONTROL_FULLSCALE_CURRENT_BASE + id, val);
if (ret)
return ret;
- /* Full-Scale Current (20.2mA) */
- ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT, 0x13);
- if (ret)
- return ret;
+ /* Set PWM mask */
+ if (priv->pwm > PWM_MAX)
+ return -EINVAL;
- /* Control Bank A is enable */
- ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_ENABLE, 0x01);
+ ret = dm_i2c_reg_write(dev, LM3533_CONTROL_PWM_BASE + id, priv->pwm);
if (ret)
return ret;
- ret = dm_i2c_reg_write(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY, 0x0A);
- if (ret)
- return ret;
-
- return 0;
+ /* Enable Control Bank */
+ return dm_i2c_reg_clrset(dev, LM3533_CONTROL_BANK_ENABLE, BIT(id), BIT(id));
}
static int lm3533_backlight_set_brightness(struct udevice *dev, int percent)
@@ -88,6 +112,56 @@
percent);
if (ret)
return ret;
+
+ return 0;
+}
+
+static int lm3533_backlight_of_to_plat(struct udevice *dev)
+{
+ struct lm3533_backlight_priv *priv = dev_get_priv(dev);
+ ofnode child;
+ int ret;
+
+ ret = gpio_request_by_name(dev, "enable-gpios", 0,
+ &priv->enable_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_err("Could not decode enable-gpios (%d)\n", ret);
+ return ret;
+ }
+
+ priv->boost_ovp = dev_read_u32_default(dev, "ti,boost-ovp-microvolt",
+ LM3533_BOOST_OVP_16V);
+
+ /* boost_ovp is defined in microvolts, convert to enum value */
+ priv->boost_ovp = priv->boost_ovp / (8 * 1000 * 1000) - 2;
+
+ priv->boost_freq = dev_read_u32_default(dev, "ti,boost-freq-hz",
+ LM3533_BOOST_FREQ_500KHZ);
+
+ /* boost_freq is defined in Hz, convert to enum value */
+ priv->boost_freq = priv->boost_freq / (500 * 1000) - 1;
+
+ /* Backlight is one of children but has no dedicated driver */
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (ofnode_device_is_compatible(child, "ti,lm3533-backlight")) {
+ const char *node_name = ofnode_get_name(child);
+
+ if (!strcmp(&node_name[10], "1"))
+ priv->reg = 1;
+ else
+ priv->reg = 0;
+
+ priv->max_current = ofnode_read_u32_default(child, "ti,max-current-microamp",
+ 5000);
+ priv->pwm = ofnode_read_u32_default(child, "ti,pwm-config-mask", 0);
+
+ priv->def_bl_lvl = ofnode_read_u32_default(child, "default-brightness",
+ LM3533_BL_MAX_BRIGHTNESS);
+
+ priv->linear = ofnode_read_bool(child, "ti,linear-mapping-mode");
+ priv->hvled = ofnode_read_bool(child, "ti,hardware-controlled");
+ }
+ }
return 0;
}
@@ -100,15 +174,22 @@
if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
return -EPROTONOSUPPORT;
- ret = gpio_request_by_name(dev, "enable-gpios", 0,
- &priv->enable_gpio, GPIOD_IS_OUT);
+ dm_gpio_set_value(&priv->enable_gpio, 1);
+ mdelay(5);
+
+ ret = dm_i2c_reg_clrset(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY,
+ BOOST_FREQ_MASK, priv->boost_freq << BOOST_FREQ_SHIFT);
if (ret) {
- log_err("Could not decode enable-gpios (%d)\n", ret);
+ log_debug("%s: freq config failed %d\n", __func__, ret);
return ret;
}
- priv->def_bl_lvl = dev_read_u32_default(dev, "default-brightness-level",
- LM3533_BL_MAX_BRIGHTNESS);
+ ret = dm_i2c_reg_clrset(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY,
+ BOOST_OVP_MASK, priv->boost_ovp << BOOST_OVP_SHIFT);
+ if (ret) {
+ log_debug("%s: ovp config failed %d\n", __func__, ret);
+ return ret;
+ }
return 0;
}
@@ -127,6 +208,7 @@
.name = "lm3533_backlight",
.id = UCLASS_PANEL_BACKLIGHT,
.of_match = lm3533_backlight_ids,
+ .of_to_plat = lm3533_backlight_of_to_plat,
.probe = lm3533_backlight_probe,
.ops = &lm3533_backlight_ops,
.priv_auto = sizeof(struct lm3533_backlight_priv),
diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c
index a3697bc..ef6fab1 100644
--- a/drivers/video/renesas-r61307.c
+++ b/drivers/video/renesas-r61307.c
@@ -254,17 +254,17 @@
return ret;
}
- ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ ret = dm_gpio_set_value(&priv->reset_gpio, 1);
if (ret) {
- log_debug("%s: changing reset-gpio failed (%d)\n",
+ log_debug("%s: entering reset failed (%d)\n",
__func__, ret);
return ret;
}
mdelay(5);
- ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
if (ret) {
- log_debug("%s: changing reset-gpio failed (%d)\n",
+ log_debug("%s: exiting reset failed (%d)\n",
__func__, ret);
return ret;
}
@@ -281,7 +281,8 @@
/* fill characteristics of DSI data link */
plat->lanes = 4;
plat->format = MIPI_DSI_FMT_RGB888;
- plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;
return renesas_r61307_hw_init(dev);
}
@@ -294,7 +295,7 @@
static const struct udevice_id renesas_r61307_ids[] = {
{ .compatible = "koe,tx13d100vm0eaa" },
- { .compatible = "hitachi,tx13d100vm0eaa" },
+ { .compatible = "hit,tx13d100vm0eaa" },
{ }
};
diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c
index 9861c3f..0954b04 100644
--- a/drivers/video/renesas-r69328.c
+++ b/drivers/video/renesas-r69328.c
@@ -32,9 +32,11 @@
#define R69328_POWER_SET 0xD1
struct renesas_r69328_priv {
+ struct udevice *vdd;
+ struct udevice *vddio;
+
struct udevice *backlight;
- struct gpio_desc enable_gpio;
struct gpio_desc reset_gpio;
};
@@ -159,13 +161,18 @@
return ret;
}
- ret = gpio_request_by_name(dev, "enable-gpios", 0,
- &priv->enable_gpio, GPIOD_IS_OUT);
+ ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd);
if (ret) {
- log_err("could not decode enable-gpios (%d)\n", ret);
+ log_err("Cannot get vdd-supply: ret = %d\n", ret);
return ret;
}
+ ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
+ if (ret) {
+ log_err("Cannot get vddio-supply: ret = %d\n", ret);
+ return ret;
+ }
+
ret = gpio_request_by_name(dev, "reset-gpios", 0,
&priv->reset_gpio, GPIOD_IS_OUT);
if (ret) {
@@ -181,28 +188,35 @@
struct renesas_r69328_priv *priv = dev_get_priv(dev);
int ret;
- ret = dm_gpio_set_value(&priv->enable_gpio, 1);
+ ret = regulator_set_enable_if_allowed(priv->vddio, 1);
if (ret) {
- log_debug("%s: error changing enable-gpios (%d)\n",
+ log_debug("%s: enabling vddio-supply failed (%d)\n",
__func__, ret);
return ret;
}
mdelay(5);
- ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ ret = regulator_set_enable_if_allowed(priv->vdd, 1);
if (ret) {
- log_debug("%s: error changing reset-gpios (%d)\n",
+ log_debug("%s: enabling vdd-supply failed (%d)\n",
__func__, ret);
return ret;
}
- mdelay(5);
ret = dm_gpio_set_value(&priv->reset_gpio, 1);
if (ret) {
- log_debug("%s: error changing reset-gpios (%d)\n",
+ log_debug("%s: error entering reset (%d)\n",
__func__, ret);
return ret;
}
+ mdelay(5);
+
+ ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+ if (ret) {
+ log_debug("%s: error exiting reset (%d)\n",
+ __func__, ret);
+ return ret;
+ }
mdelay(5);
@@ -216,7 +230,8 @@
/* fill characteristics of DSI data link */
plat->lanes = 4;
plat->format = MIPI_DSI_FMT_RGB888;
- plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;
return renesas_r69328_hw_init(dev);
}
diff --git a/drivers/video/samsung-ltl106hl02.c b/drivers/video/samsung-ltl106hl02.c
index 5e6c11c..1efc9fc 100644
--- a/drivers/video/samsung-ltl106hl02.c
+++ b/drivers/video/samsung-ltl106hl02.c
@@ -129,7 +129,7 @@
/* fill characteristics of DSI data link */
plat->lanes = 4;
plat->format = MIPI_DSI_FMT_RGB888;
- plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+ plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
return samsung_ltl106hl02_hw_init(dev);
}
diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c
index 5d8453f..4fdf0da 100644
--- a/drivers/video/sharp-lq101r1sx01.c
+++ b/drivers/video/sharp-lq101r1sx01.c
@@ -255,6 +255,7 @@
/* fill characteristics of DSI data link */
plat->lanes = 4;
plat->format = MIPI_DSI_FMT_RGB888;
+ plat->mode_flags = MIPI_DSI_MODE_LPM;
return sharp_lq101r1sx01_hw_init(dev);
}
diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig
index f5c4843..598f9ea 100644
--- a/drivers/video/tegra20/Kconfig
+++ b/drivers/video/tegra20/Kconfig
@@ -1,6 +1,11 @@
+config HOST1X_TEGRA
+ bool "NVIDIA Tegra host1x BUS support"
+ depends on SIMPLE_BUS
+
config VIDEO_TEGRA20
bool "Enable Display Controller support on Tegra20 and Tegra 30"
depends on OF_CONTROL
+ select HOST1X_TEGRA
help
T20/T30 support video output to an attached LCD panel as well as
other options such as HDMI. Only the LCD is supported in U-Boot.
@@ -9,13 +14,22 @@
config VIDEO_DSI_TEGRA30
bool "Enable Tegra 30 DSI support"
- depends on PANEL && DM_GPIO
+ depends on VIDEO_BRIDGE && PANEL && DM_GPIO
select VIDEO_TEGRA20
select VIDEO_MIPI_DSI
help
T30 has native support for DSI panels. This option enables support
for such panels which can be used on endeavoru and tf600t.
+config VIDEO_HDMI_TEGRA
+ bool "Enable Tegra HDMI support"
+ depends on VIDEO_BRIDGE && DM_I2C
+ select I2C_EDID
+ select VIDEO_TEGRA20
+ help
+ Tegra has native support for HDMI. This option enables support
+ for such connection and can be used for any supported device.
+
config TEGRA_BACKLIGHT_PWM
bool "Enable Tegra DC PWM backlight support"
depends on BACKLIGHT
diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
index a75aea2..7852140 100644
--- a/drivers/video/tegra20/Makefile
+++ b/drivers/video/tegra20/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o
+obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o
obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 16a2b52..1f43153 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -1,16 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
*/
#include <backlight.h>
#include <cpu_func.h>
#include <clk.h>
#include <dm.h>
+#include <dm/ofnode_graph.h>
#include <fdtdec.h>
#include <log.h>
#include <panel.h>
#include <video.h>
+#include <video_bridge.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@@ -31,7 +34,8 @@
int height; /* height in pixels */
enum video_log2_bpp log2_bpp; /* colour depth */
struct display_timing timing;
- struct udevice *panel;
+ struct udevice *panel; /* Panels attached to RGB */
+ struct udevice *bridge; /* Bridge linked with DC */
struct dc_ctlr *dc; /* Display controller regmap */
const struct tegra_dc_soc_info *soc;
fdt_addr_t frame_buffer; /* Address of frame buffer */
@@ -319,11 +323,6 @@
/ priv->pixel_clock) - 2;
log_debug("Display clock %lu, divider %lu\n", rate, priv->scdiv);
- /*
- * HOST1X is init by default at 150MHz with PLLC as parent
- */
- clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL,
- 150 * 1000000);
clock_start_periph_pll(priv->clk->id, priv->clk_parent->id,
rate);
@@ -378,11 +377,12 @@
}
/* Get shift clock divider from Tegra DSI if used */
- if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
- !strcmp(priv->panel->name, TEGRA_DSI_B)) {
- struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
+ if (priv->bridge) {
+ if (!strcmp(priv->bridge->driver->name, "tegra_dsi")) {
+ struct tegra_dc_plat *dc_plat = dev_get_plat(priv->bridge);
- priv->scdiv = dc_plat->scdiv;
+ priv->scdiv = dc_plat->scdiv;
+ }
}
/* Clean the framebuffer area */
@@ -395,12 +395,22 @@
return ret;
}
- ret = panel_enable_backlight(priv->panel);
- if (ret) {
- log_debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
- return ret;
+ if (priv->panel) {
+ ret = panel_enable_backlight(priv->panel);
+ if (ret) {
+ log_debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
+ return ret;
+ }
}
+ if (priv->bridge) {
+ ret = video_bridge_attach(priv->bridge);
+ if (ret) {
+ log_debug("%s: Cannot attach bridge, ret=%d\n", __func__, ret);
+ return ret;
+ }
+ }
+
mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
DCACHE_WRITETHROUGH);
@@ -413,17 +423,129 @@
log_debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
plat->size);
+ if (priv->panel) {
+ ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+ if (ret)
+ return ret;
+ }
+
- return panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+ if (priv->bridge) {
+ ret = video_bridge_set_backlight(priv->bridge, BACKLIGHT_DEFAULT);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
+static int tegra_lcd_configure_rgb(struct udevice *dev, ofnode rgb)
+{
+ struct tegra_lcd_priv *priv = dev_get_priv(dev);
+ ofnode remote;
+ int ret;
+
+ /* DC can have only 1 port */
+ remote = ofnode_graph_get_remote_node(rgb, -1, -1);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+ if (!ret)
+ return 0;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &priv->bridge);
+ if (!ret)
+ return 0;
+
+ /* Try legacy method if graph did not work */
+ remote = ofnode_parse_phandle(rgb, "nvidia,panel", 0);
+ if (!ofnode_valid(remote))
+ return -EINVAL;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+ if (ret) {
+ log_debug("%s: Cannot find panel for '%s' (ret=%d)\n",
+ __func__, dev->name, ret);
+
+ ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote,
+ &priv->bridge);
+ if (ret) {
+ log_err("%s: Cannot find panel or bridge for '%s' (ret=%d)\n",
+ __func__, dev->name, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int tegra_lcd_configure_internal(struct udevice *dev)
+{
+ struct tegra_lcd_priv *priv = dev_get_priv(dev);
+ struct tegra_dc_plat *dc_plat;
+ ofnode host1x = ofnode_get_parent(dev_ofnode(dev));
+ ofnode node;
+ int ret;
+
+ switch (priv->pipe) {
+ case 0: /* DC0 is usually used for DSI */
+ /* Check for ganged DSI configuration */
+ ofnode_for_each_subnode(node, host1x)
+ if (ofnode_name_eq(node, "dsi") && ofnode_is_enabled(node) &&
+ ofnode_read_bool(node, "nvidia,ganged-mode"))
+ goto exit;
+
+ /* If no master DSI found loop for any active DSI */
+ ofnode_for_each_subnode(node, host1x)
+ if (ofnode_name_eq(node, "dsi") && ofnode_is_enabled(node))
+ goto exit;
+
+ log_err("%s: failed to find DSI device for '%s'\n",
+ __func__, dev->name);
+
+ return -ENODEV;
+ case 1: /* DC1 is usually used for HDMI */
+ ofnode_for_each_subnode(node, host1x)
+ if (ofnode_name_eq(node, "hdmi"))
+ goto exit;
+
+ log_err("%s: failed to find HDMI device for '%s'\n",
+ __func__, dev->name);
+
+ return -ENODEV;
+ default:
+ log_debug("Unsupported DC selection\n");
+ return -EINVAL;
+ }
+
+exit:
+ ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, node, &priv->bridge);
+ if (ret) {
+ log_err("%s: failed to get DSI/HDMI device for '%s' (ret %d)\n",
+ __func__, dev->name, ret);
+ return ret;
+ }
+
+ priv->clk_parent = devm_clk_get(priv->bridge, "parent");
+ if (IS_ERR(priv->clk_parent)) {
+ log_debug("%s: Could not get DC clock parent from DSI/HDMI: %ld\n",
+ __func__, PTR_ERR(priv->clk_parent));
+ return PTR_ERR(priv->clk_parent);
+ }
+
+ dc_plat = dev_get_plat(priv->bridge);
+
+ /* Fill the platform data for internal devices */
+ dc_plat->dev = dev;
+ dc_plat->dc = priv->dc;
+ dc_plat->pipe = priv->pipe;
+
+ return 0;
+}
+
static int tegra_lcd_of_to_plat(struct udevice *dev)
{
struct tegra_lcd_priv *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
struct display_timing *timing;
- int node = dev_of_offset(dev);
- int panel_node;
- int rgb;
+ ofnode rgb;
int ret;
priv->dc = (struct dc_ctlr *)dev_read_addr_ptr(dev);
@@ -451,44 +573,42 @@
priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
priv->pipe = dev_read_u32_default(dev, "nvidia,head", 0);
- rgb = fdt_subnode_offset(blob, node, "rgb");
- if (rgb < 0) {
- log_debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
- __func__, dev->name, rgb);
- return -EINVAL;
- }
-
/*
- * Sadly the panel phandle is in an rgb subnode so we cannot use
- * uclass_get_device_by_phandle().
+ * Usual logic of Tegra video routing should be next:
+ * 1. Check rgb subnode for RGB/LVDS panels or bridges
+ * 2. If none found, then iterate through bridges bound,
+ * looking for DSIA or DSIB for DC0 and HDMI for DC1.
+ * If none of above is valid, then configuration is not
+ * valid.
*/
- panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
- if (panel_node < 0) {
- log_debug("%s: Cannot find panel information\n", __func__);
- return -EINVAL;
- }
- ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
- &priv->panel);
- if (ret) {
- log_debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
- dev->name, ret);
- return ret;
+ rgb = dev_read_subnode(dev, "rgb");
+ if (ofnode_valid(rgb) && ofnode_is_enabled(rgb)) {
+ /* RGB is available, use it */
+ ret = tegra_lcd_configure_rgb(dev, rgb);
+ if (ret)
+ return ret;
+ } else {
+ /* RGB is not available, check for internal devices */
+ ret = tegra_lcd_configure_internal(dev);
+ if (ret)
+ return ret;
}
- /* Fill the platform data for internal devices */
- if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
- !strcmp(priv->panel->name, TEGRA_DSI_B)) {
- struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
-
- dc_plat->dev = dev;
- dc_plat->dc = priv->dc;
- dc_plat->pipe = priv->pipe;
+ if (priv->panel) {
+ ret = panel_get_display_timing(priv->panel, &priv->timing);
+ if (ret) {
+ ret = ofnode_decode_display_timing(rgb, 0, &priv->timing);
+ if (ret) {
+ log_debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+ __func__, dev->name, ret);
+ return -EINVAL;
+ }
+ }
}
- ret = panel_get_display_timing(priv->panel, &priv->timing);
- if (ret) {
- ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+ if (priv->bridge) {
+ ret = video_bridge_get_display_timing(priv->bridge, &priv->timing);
if (ret) {
log_debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
__func__, dev->name, ret);
@@ -508,23 +628,13 @@
static int tegra_lcd_bind(struct udevice *dev)
{
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
- int rgb;
-
- rgb = fdt_subnode_offset(blob, node, "rgb");
- if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
- return -ENODEV;
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
- return 0;
+ return dm_scan_fdt_dev(dev);
}
-static const struct video_ops tegra_lcd_ops = {
-};
-
static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
.has_timer = true,
.has_rgb = true,
@@ -565,7 +675,6 @@
.name = "tegra_lcd",
.id = UCLASS_VIDEO,
.of_match = tegra_lcd_ids,
- .ops = &tegra_lcd_ops,
.bind = tegra_lcd_bind,
.probe = tegra_lcd_probe,
.of_to_plat = tegra_lcd_of_to_plat,
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h
index 7d0c189..2a4013b 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra20/tegra-dc.h
@@ -14,9 +14,6 @@
/* arch-tegra/dc exists only because T124 uses it */
#include <asm/arch-tegra/dc.h>
-#define TEGRA_DSI_A "dsi@54300000"
-#define TEGRA_DSI_B "dsi@54400000"
-
struct tegra_dc_plat {
struct udevice *dev; /* Display controller device */
struct dc_ctlr *dc; /* Display controller regmap */
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 9f39ac7..a2a22fa 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -11,6 +11,7 @@
#include <mipi_display.h>
#include <mipi_dsi.h>
#include <backlight.h>
+#include <video_bridge.h>
#include <panel.h>
#include <reset.h>
#include <linux/delay.h>
@@ -250,6 +251,9 @@
value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
+ if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
+ value |= DSI_HOST_CONTROL_HS;
+
/*
* The host FIFO has a maximum of 64 words, so larger transmissions
* need to use the video FIFO.
@@ -991,7 +995,7 @@
struct tegra_dsi_priv *mpriv = dev_get_priv(dev);
struct udevice *gangster;
- uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+ uclass_get_device_by_phandle(UCLASS_VIDEO_BRIDGE, dev,
"nvidia,ganged-mode", &gangster);
if (gangster) {
/* Ganged mode is set */
@@ -1118,8 +1122,8 @@
return 0;
}
-static const struct panel_ops tegra_dsi_bridge_ops = {
- .enable_backlight = tegra_dsi_encoder_enable,
+static const struct video_bridge_ops tegra_dsi_bridge_ops = {
+ .attach = tegra_dsi_encoder_enable,
.set_backlight = tegra_dsi_bridge_set_panel,
.get_display_timing = tegra_dsi_panel_timings,
};
@@ -1133,7 +1137,7 @@
U_BOOT_DRIVER(tegra_dsi) = {
.name = "tegra_dsi",
- .id = UCLASS_PANEL,
+ .id = UCLASS_VIDEO_BRIDGE,
.of_match = tegra_dsi_bridge_ids,
.ops = &tegra_dsi_bridge_ops,
.bind = dm_scan_fdt_dev,
diff --git a/drivers/video/tegra20/tegra-hdmi.c b/drivers/video/tegra20/tegra-hdmi.c
new file mode 100644
index 0000000..bda6991
--- /dev/null
+++ b/drivers/video/tegra20/tegra-hdmi.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <edid.h>
+#include <i2c.h>
+#include <log.h>
+#include <misc.h>
+#include <panel.h>
+#include <reset.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/time.h>
+#include <power/regulator.h>
+#include <video_bridge.h>
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#include "tegra-dc.h"
+#include "tegra-hdmi.h"
+
+#define DDCCI_ENTRY_ADDR 0x37
+#define DDCCI_SOURSE_ADDR 0x51
+#define DDCCI_COMMAND_WRITE 0x03
+#define DDCCI_CTRL_BRIGHTNESS 0x10
+
+#define HDMI_EDID_I2C_ADDR 0x50
+#define HDMI_REKEY_DEFAULT 56
+
+static const char * const hdmi_supplies[] = {
+ "hdmi-supply", "pll-supply", "vdd-supply"
+};
+
+struct tmds_config {
+ unsigned int pclk;
+ u32 pll0;
+ u32 pll1;
+ u32 pe_current;
+ u32 drive_current;
+ u32 peak_current;
+};
+
+struct tegra_hdmi_config {
+ const struct tmds_config *tmds;
+ unsigned int num_tmds;
+ unsigned int max_pclk;
+
+ /* to be filled */
+};
+
+struct tegra_hdmi_priv {
+ struct hdmi_ctlr *hdmi_regmap;
+
+ struct udevice *supplies[ARRAY_SIZE(hdmi_supplies)];
+ struct udevice *hdmi_ddc;
+
+ struct gpio_desc hpd; /* hotplug detection gpio */
+ struct display_timing timing;
+
+ struct clk *clk;
+ struct clk *clk_parent;
+
+ int panel_bits_per_colourp;
+ const struct tegra_hdmi_config *config;
+};
+
+/* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
+static struct display_timing default_720p_timing = {
+ .pixelclock.typ = 74250000,
+ .hactive.typ = 1280,
+ .hfront_porch.typ = 110,
+ .hback_porch.typ = 220,
+ .hsync_len.typ = 40,
+ .vactive.typ = 720,
+ .vfront_porch.typ = 5,
+ .vback_porch.typ = 20,
+ .vsync_len.typ = 5,
+ .flags = DISPLAY_FLAGS_HSYNC_HIGH |
+ DISPLAY_FLAGS_VSYNC_HIGH,
+};
+
+static const struct tmds_config tegra20_tmds_config[] = {
+ { /* slow pixel clock modes */
+ .pclk = 27000000,
+ .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+ SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+ SOR_PLL_TX_REG_LOAD(3),
+ .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+ .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+ PE_CURRENT1(PE_CURRENT_0_0_mA) |
+ PE_CURRENT2(PE_CURRENT_0_0_mA) |
+ PE_CURRENT3(PE_CURRENT_0_0_mA),
+ .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+ DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+ DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+ DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+ },
+ { /* high pixel clock modes */
+ .pclk = UINT_MAX,
+ .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+ SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+ SOR_PLL_TX_REG_LOAD(3),
+ .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+ .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+ PE_CURRENT1(PE_CURRENT_6_0_mA) |
+ PE_CURRENT2(PE_CURRENT_6_0_mA) |
+ PE_CURRENT3(PE_CURRENT_6_0_mA),
+ .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+ DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+ DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+ DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+ },
+};
+
+static const struct tmds_config tegra30_tmds_config[] = {
+ { /* 480p modes */
+ .pclk = 27000000,
+ .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+ SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+ SOR_PLL_TX_REG_LOAD(0),
+ .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+ .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+ PE_CURRENT1(PE_CURRENT_0_0_mA) |
+ PE_CURRENT2(PE_CURRENT_0_0_mA) |
+ PE_CURRENT3(PE_CURRENT_0_0_mA),
+ .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+ }, { /* 720p modes */
+ .pclk = 74250000,
+ .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+ SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+ SOR_PLL_TX_REG_LOAD(0),
+ .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+ .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+ PE_CURRENT1(PE_CURRENT_5_0_mA) |
+ PE_CURRENT2(PE_CURRENT_5_0_mA) |
+ PE_CURRENT3(PE_CURRENT_5_0_mA),
+ .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+ }, { /* 1080p modes */
+ .pclk = UINT_MAX,
+ .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+ SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
+ SOR_PLL_TX_REG_LOAD(0),
+ .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+ .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+ PE_CURRENT1(PE_CURRENT_5_0_mA) |
+ PE_CURRENT2(PE_CURRENT_5_0_mA) |
+ PE_CURRENT3(PE_CURRENT_5_0_mA),
+ .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+ DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+ },
+};
+
+static void tegra_dc_enable_controller(struct udevice *dev)
+{
+ struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+ struct dc_ctlr *dc = dc_plat->dc;
+ u32 value;
+
+ value = readl(&dc->disp.disp_win_opt);
+ value |= HDMI_ENABLE;
+ writel(value, &dc->disp.disp_win_opt);
+
+ writel(GENERAL_UPDATE, &dc->cmd.state_ctrl);
+ writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl);
+}
+
+static void tegra_hdmi_setup_tmds(struct tegra_hdmi_priv *priv,
+ const struct tmds_config *tmds)
+{
+ struct hdmi_ctlr *hdmi = priv->hdmi_regmap;
+ u32 value;
+
+ writel(tmds->pll0, &hdmi->nv_pdisp_sor_pll0);
+ writel(tmds->pll1, &hdmi->nv_pdisp_sor_pll1);
+ writel(tmds->pe_current, &hdmi->nv_pdisp_pe_current);
+
+ writel(tmds->drive_current, &hdmi->nv_pdisp_sor_lane_drive_current);
+
+ value = readl(&hdmi->nv_pdisp_sor_lane_drive_current);
+ value |= BIT(31);
+ writel(value, &hdmi->nv_pdisp_sor_lane_drive_current);
+}
+
+static int tegra_hdmi_encoder_enable(struct udevice *dev)
+{
+ struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+ struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+ struct dc_ctlr *dc = dc_plat->dc;
+ struct display_timing *dt = &priv->timing;
+ struct hdmi_ctlr *hdmi = priv->hdmi_regmap;
+ unsigned long rate, div82;
+ unsigned int pulse_start, rekey;
+ int retries = 1000;
+ u32 value;
+ int i;
+
+ /* power up sequence */
+ value = readl(&hdmi->nv_pdisp_sor_pll0);
+ value &= ~SOR_PLL_PDBG;
+ writel(value, &hdmi->nv_pdisp_sor_pll0);
+
+ udelay(20);
+
+ value = readl(&hdmi->nv_pdisp_sor_pll0);
+ value &= ~SOR_PLL_PWR;
+ writel(value, &hdmi->nv_pdisp_sor_pll0);
+
+ writel(VSYNC_H_POSITION(1), &dc->disp.disp_timing_opt);
+ writel(DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
+ &dc->disp.disp_color_ctrl);
+
+ /* video_preamble uses h_pulse2 */
+ pulse_start = 1 + dt->hsync_len.typ + dt->hback_porch.typ - 10;
+
+ writel(H_PULSE2_ENABLE, &dc->disp.disp_signal_opt0);
+
+ value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH |
+ PULSE_QUAL_VACTIVE | PULSE_LAST_END_A;
+ writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_ctrl);
+
+ value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
+ writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_pos[H_PULSE0_POSITION_A]);
+
+ value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
+ VSYNC_WINDOW_ENABLE;
+ writel(value, &hdmi->nv_pdisp_hdmi_vsync_window);
+
+ if (dc_plat->pipe)
+ value = HDMI_SRC_DISPLAYB;
+ else
+ value = HDMI_SRC_DISPLAYA;
+
+ if (dt->hactive.typ == 720 && (dt->vactive.typ == 480 ||
+ dt->vactive.typ == 576))
+ writel(value | ARM_VIDEO_RANGE_FULL,
+ &hdmi->nv_pdisp_input_control);
+ else
+ writel(value | ARM_VIDEO_RANGE_LIMITED,
+ &hdmi->nv_pdisp_input_control);
+
+ rate = clock_get_periph_rate(priv->clk->id, priv->clk_parent->id);
+ div82 = rate / USEC_PER_SEC * 4;
+ value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
+ writel(value, &hdmi->nv_pdisp_sor_refclk);
+
+ rekey = HDMI_REKEY_DEFAULT;
+ value = HDMI_CTRL_REKEY(rekey);
+ value |= HDMI_CTRL_MAX_AC_PACKET((dt->hsync_len.typ + dt->hback_porch.typ +
+ dt->hfront_porch.typ - rekey - 18) / 32);
+ writel(value, &hdmi->nv_pdisp_hdmi_ctrl);
+
+ /* TMDS CONFIG */
+ for (i = 0; i < priv->config->num_tmds; i++) {
+ if (dt->pixelclock.typ <= priv->config->tmds[i].pclk) {
+ tegra_hdmi_setup_tmds(priv, &priv->config->tmds[i]);
+ break;
+ }
+ }
+
+ writel(SOR_SEQ_PU_PC(0) | SOR_SEQ_PU_PC_ALT(0) | SOR_SEQ_PD_PC(8) |
+ SOR_SEQ_PD_PC_ALT(8), &hdmi->nv_pdisp_sor_seq_ctl);
+
+ value = SOR_SEQ_INST_WAIT_TIME(1) | SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+ SOR_SEQ_INST_HALT | SOR_SEQ_INST_PIN_A_LOW |
+ SOR_SEQ_INST_PIN_B_LOW | SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
+
+ writel(value, &hdmi->nv_pdisp_sor_seq_inst0);
+ writel(value, &hdmi->nv_pdisp_sor_seq_inst8);
+
+ value = readl(&hdmi->nv_pdisp_sor_cstm);
+
+ value &= ~SOR_CSTM_ROTCLK(~0);
+ value |= SOR_CSTM_ROTCLK(2);
+ value |= SOR_CSTM_PLLDIV;
+ value &= ~SOR_CSTM_LVDS_ENABLE;
+ value &= ~SOR_CSTM_MODE_MASK;
+ value |= SOR_CSTM_MODE_TMDS;
+
+ writel(value, &hdmi->nv_pdisp_sor_cstm);
+
+ /* start SOR */
+ writel(SOR_PWR_NORMAL_STATE_PU | SOR_PWR_NORMAL_START_NORMAL |
+ SOR_PWR_SAFE_STATE_PD | SOR_PWR_SETTING_NEW_TRIGGER,
+ &hdmi->nv_pdisp_sor_pwr);
+ writel(SOR_PWR_NORMAL_STATE_PU | SOR_PWR_NORMAL_START_NORMAL |
+ SOR_PWR_SAFE_STATE_PD | SOR_PWR_SETTING_NEW_DONE,
+ &hdmi->nv_pdisp_sor_pwr);
+
+ do {
+ if (--retries < 0)
+ return -ETIME;
+ value = readl(&hdmi->nv_pdisp_sor_pwr);
+ } while (value & SOR_PWR_SETTING_NEW_PENDING);
+
+ value = SOR_STATE_ASY_CRCMODE_COMPLETE |
+ SOR_STATE_ASY_OWNER_HEAD0 |
+ SOR_STATE_ASY_SUBOWNER_BOTH |
+ SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
+ SOR_STATE_ASY_DEPOL_POS;
+
+ /* setup sync polarities */
+ if (dt->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+ value |= SOR_STATE_ASY_HSYNCPOL_POS;
+
+ if (dt->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ value |= SOR_STATE_ASY_HSYNCPOL_NEG;
+
+ if (dt->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+ value |= SOR_STATE_ASY_VSYNCPOL_POS;
+
+ if (dt->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ value |= SOR_STATE_ASY_VSYNCPOL_NEG;
+
+ writel(value, &hdmi->nv_pdisp_sor_state2);
+
+ value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
+ writel(value, &hdmi->nv_pdisp_sor_state1);
+
+ writel(0, &hdmi->nv_pdisp_sor_state0);
+ writel(SOR_STATE_UPDATE, &hdmi->nv_pdisp_sor_state0);
+ writel(value | SOR_STATE_ATTACHED,
+ &hdmi->nv_pdisp_sor_state1);
+ writel(0, &hdmi->nv_pdisp_sor_state0);
+
+ tegra_dc_enable_controller(dev);
+
+ return 0;
+}
+
+/* DDC/CI backlight control */
+static int tegra_hdmi_set_connector(struct udevice *dev, int percent)
+{
+ struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+ struct udevice *ddc_entry;
+ struct i2c_msg msg[1];
+ u8 checksum = DDCCI_ENTRY_ADDR << 1;
+ int i, ret;
+
+ ret = dm_i2c_probe(priv->hdmi_ddc, DDCCI_ENTRY_ADDR, 0, &ddc_entry);
+ if (ret) {
+ log_debug("%s: cannot probe DDC/CI entry: error %d\n",
+ __func__, ret);
+ return 0;
+ }
+
+ /*
+ * payload[1] is length: hithest bit OR last 4 bits indicate
+ * the number of following bytes (excluding checksum)
+ */
+ u8 payload[7] = { DDCCI_SOURSE_ADDR, BIT(7) | (sizeof(payload) - 3),
+ DDCCI_COMMAND_WRITE, DDCCI_CTRL_BRIGHTNESS,
+ (u8)(percent & 0xff), (u8)(percent & 0xff), 0 };
+
+ /* DDC/CI checksum is a simple XOR of all preceding bytes */
+ for (i = 0; i < (sizeof(payload) - 1); i++)
+ checksum ^= payload[i];
+
+ payload[6] = checksum;
+
+ msg->addr = DDCCI_ENTRY_ADDR;
+ msg->flags = 0;
+ msg->len = sizeof(payload);
+ msg->buf = payload;
+
+ dm_i2c_xfer(ddc_entry, msg, 1);
+
+ return 0;
+}
+
+static int tegra_hdmi_timings(struct udevice *dev,
+ struct display_timing *timing)
+{
+ struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+
+ memcpy(timing, &priv->timing, sizeof(*timing));
+
+ return 0;
+}
+
+static void tegra_hdmi_init_clocks(struct udevice *dev)
+{
+ struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+ u32 n = priv->timing.pixelclock.typ * 2 / USEC_PER_SEC;
+
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
+ clock_set_rate(priv->clk_parent->id, n, 12, 0, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(priv->clk_parent->id, n, 26, 0, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
+ clock_set_rate(priv->clk_parent->id, n, 13, 0, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_19_2:
+ case CLOCK_OSC_FREQ_38_4:
+ default:
+ /*
+ * These are not supported.
+ */
+ break;
+ }
+
+ clock_start_periph_pll(priv->clk->id, priv->clk_parent->id,
+ priv->timing.pixelclock.typ);
+}
+
+static bool tegra_hdmi_mode_valid(void *hdmi_priv, const struct display_timing *timing)
+{
+ struct tegra_hdmi_priv *priv = hdmi_priv;
+
+ if (timing->pixelclock.typ > priv->config->max_pclk)
+ return false;
+
+ return true;
+}
+
+static int tegra_hdmi_decode_edid(struct udevice *dev)
+{
+ struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+ struct udevice *hdmi_edid;
+ uchar edid_buf[EDID_SIZE] = { 0 };
+ int i, ret;
+
+ /* Poll for 1 sec in case EDID is not ready right after hpd */
+ for (i = 0; i < 10; i++) {
+ ret = dm_i2c_probe(priv->hdmi_ddc, HDMI_EDID_I2C_ADDR, 0,
+ &hdmi_edid);
+ if (!ret)
+ break;
+
+ mdelay(100);
+ }
+ if (ret) {
+ log_debug("%s: cannot probe EDID: error %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = dm_i2c_read(hdmi_edid, 0, edid_buf, sizeof(edid_buf));
+ if (ret) {
+ log_debug("%s: cannot dump EDID buffer: error %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = edid_get_timing_validate(edid_buf, sizeof(edid_buf), &priv->timing,
+ &priv->panel_bits_per_colourp,
+ tegra_hdmi_mode_valid, priv);
+ if (ret) {
+ log_debug("%s: cannot decode EDID info: error %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tegra_hdmi_wait_hpd(struct tegra_hdmi_priv *priv)
+{
+ int i;
+
+ /* Poll 1 second for HPD signal */
+ for (i = 0; i < 10; i++) {
+ if (dm_gpio_get_value(&priv->hpd))
+ return 0;
+
+ mdelay(100);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int tegra_hdmi_probe(struct udevice *dev)
+{
+ struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+ struct reset_ctl reset_ctl;
+ int i, ret;
+
+ priv->hdmi_regmap = (struct hdmi_ctlr *)dev_read_addr_ptr(dev);
+ if (!priv->hdmi_regmap) {
+ log_debug("%s: no display controller address\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->config = (struct tegra_hdmi_config *)dev_get_driver_data(dev);
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ log_debug("%s: Could not get HDMI clock: %ld\n",
+ __func__, PTR_ERR(priv->clk));
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->clk_parent = devm_clk_get(dev, "parent");
+ if (IS_ERR(priv->clk_parent)) {
+ log_debug("%s: Could not get HDMI clock parent: %ld\n",
+ __func__, PTR_ERR(priv->clk_parent));
+ return PTR_ERR(priv->clk_parent);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(hdmi_supplies); i++) {
+ ret = device_get_supply_regulator(dev, hdmi_supplies[i],
+ &priv->supplies[i]);
+ if (ret) {
+ log_debug("%s: cannot get %s %d\n", __func__,
+ hdmi_supplies[i], ret);
+ if (ret != -ENOENT)
+ return log_ret(ret);
+ }
+
+ ret = regulator_set_enable_if_allowed(priv->supplies[i], true);
+ if (ret && ret != -ENOSYS) {
+ log_debug("%s: cannot enable %s: error %d\n",
+ __func__, hdmi_supplies[i], ret);
+ return ret;
+ }
+ }
+
+ ret = reset_get_by_name(dev, "hdmi", &reset_ctl);
+ if (ret) {
+ log_debug("%s: reset_get_by_name() failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_phandle(UCLASS_I2C, dev,
+ "nvidia,ddc-i2c-bus",
+ &priv->hdmi_ddc);
+ if (ret) {
+ log_debug("%s: cannot get hdmi ddc i2c bus: error %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "nvidia,hpd-gpio", 0,
+ &priv->hpd, GPIOD_IS_IN);
+ if (ret) {
+ log_debug("%s: Could not decode hpd-gpios (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* wait for connector */
+ ret = tegra_hdmi_wait_hpd(priv);
+ if (ret) {
+ /* HPD failed, use default timings */
+ memcpy(&priv->timing, &default_720p_timing,
+ sizeof(default_720p_timing));
+ } else {
+ ret = tegra_hdmi_decode_edid(dev);
+ if (ret)
+ memcpy(&priv->timing, &default_720p_timing,
+ sizeof(default_720p_timing));
+ }
+
+ reset_assert(&reset_ctl);
+ tegra_hdmi_init_clocks(dev);
+
+ mdelay(2);
+ reset_deassert(&reset_ctl);
+
+ return 0;
+}
+
+static const struct tegra_hdmi_config tegra20_hdmi_config = {
+ .tmds = tegra20_tmds_config,
+ .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
+ .max_pclk = 148500000, /* 1080p */
+};
+
+static const struct tegra_hdmi_config tegra30_hdmi_config = {
+ .tmds = tegra30_tmds_config,
+ .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
+ .max_pclk = 148500000, /* 1080p */
+};
+
+static const struct video_bridge_ops tegra_hdmi_ops = {
+ .attach = tegra_hdmi_encoder_enable,
+ .set_backlight = tegra_hdmi_set_connector,
+ .get_display_timing = tegra_hdmi_timings,
+};
+
+static const struct udevice_id tegra_hdmi_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-hdmi",
+ .data = (ulong)&tegra20_hdmi_config
+ }, {
+ .compatible = "nvidia,tegra30-hdmi",
+ .data = (ulong)&tegra30_hdmi_config
+ }, {
+ /* sentinel */
+ }
+};
+
+U_BOOT_DRIVER(tegra_hdmi) = {
+ .name = "tegra_hdmi",
+ .id = UCLASS_VIDEO_BRIDGE,
+ .of_match = tegra_hdmi_ids,
+ .ops = &tegra_hdmi_ops,
+ .probe = tegra_hdmi_probe,
+ .plat_auto = sizeof(struct tegra_dc_plat),
+ .priv_auto = sizeof(struct tegra_hdmi_priv),
+};
diff --git a/drivers/video/tegra20/tegra-hdmi.h b/drivers/video/tegra20/tegra-hdmi.h
new file mode 100644
index 0000000..d176559
--- /dev/null
+++ b/drivers/video/tegra20/tegra-hdmi.h
@@ -0,0 +1,648 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_HDMI_H
+#define _TEGRA_HDMI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+/* Register definitions for the Tegra high-definition multimedia interface */
+
+/* High-Definition Multimedia Interface (HDMI_) regs */
+struct hdmi_ctlr {
+ /* Address 0x000 ~ 0x0d2 */
+ uint ctxsw; /* _CTXSW */ /* 0x00 */
+
+ uint nv_pdisp_sor_state0; /* _NV_PDISP_SOR_STATE0 */
+ uint nv_pdisp_sor_state1; /* _NV_PDISP_SOR_STATE1 */
+ uint nv_pdisp_sor_state2; /* _NV_PDISP_SOR_STATE2 */
+
+ uint nv_pdisp_rg_hdcp_an_msb; /* _NV_PDISP_RG_HDCP_AN_MSB */
+ uint nv_pdisp_rg_hdcp_an_lsb; /* _NV_PDISP_RG_HDCP_AN_LSB */
+ uint nv_pdisp_rg_hdcp_cn_msb; /* _NV_PDISP_RG_HDCP_CN_MSB */
+ uint nv_pdisp_rg_hdcp_cn_lsb; /* _NV_PDISP_RG_HDCP_CN_LSB */
+ uint nv_pdisp_rg_hdcp_aksv_msb; /* _NV_PDISP_RG_HDCP_AKSV_MSB */
+ uint nv_pdisp_rg_hdcp_aksv_lsb; /* _NV_PDISP_RG_HDCP_AKSV_LSB */
+ uint nv_pdisp_rg_hdcp_bksv_msb; /* _NV_PDISP_RG_HDCP_BKSV_MSB */
+ uint nv_pdisp_rg_hdcp_bksv_lsb; /* _NV_PDISP_RG_HDCP_BKSV_LSB */
+ uint nv_pdisp_rg_hdcp_cksv_msb; /* _NV_PDISP_RG_HDCP_CKSV_MSB */
+ uint nv_pdisp_rg_hdcp_cksv_lsb; /* _NV_PDISP_RG_HDCP_CKSV_LSB */
+ uint nv_pdisp_rg_hdcp_dksv_msb; /* _NV_PDISP_RG_HDCP_DKSV_MSB */
+ uint nv_pdisp_rg_hdcp_dksv_lsb; /* _NV_PDISP_RG_HDCP_DKSV_LSB */
+ uint nv_pdisp_rg_hdcp_ctrl; /* _NV_PDISP_RG_HDCP_CTRL */ /* 0x10 */
+ uint nv_pdisp_rg_hdcp_cmode; /* _NV_PDISP_RG_HDCP_CMODE */
+ uint nv_pdisp_rg_hdcp_mprime_msb; /* _NV_PDISP_RG_HDCP_MPRIME_MSB */
+ uint nv_pdisp_rg_hdcp_mprime_lsb; /* _NV_PDISP_RG_HDCP_MPRIME_LSB */
+ uint nv_pdisp_rg_hdcp_sprime_msb; /* _NV_PDISP_RG_HDCP_SPRIME_MSB */
+ uint nv_pdisp_rg_hdcp_sprime_lsb2; /* _NV_PDISP_RG_HDCP_SPRIME_LSB2 */
+ uint nv_pdisp_rg_hdcp_sprime_lsb1; /* _NV_PDISP_RG_HDCP_SPRIME_LSB1 */
+ uint nv_pdisp_rg_hdcp_ri; /* _NV_PDISP_RG_HDCP_RI */
+ uint nv_pdisp_rg_hdcp_cs_msb; /* _NV_PDISP_RG_HDCP_CS_MSB */
+ uint nv_pdisp_rg_hdcp_cs_lsb; /* _NV_PDISP_RG_HDCP_CS_LSB */
+
+ uint nv_pdisp_hdmi_audio_emu0; /* _NV_PDISP_HDMI_AUDIO_EMU0 */
+ uint nv_pdisp_hdmi_audio_emu_rdata0; /* _NV_PDISP_HDMI_AUDIO_EMU_RDATA0 */
+ uint nv_pdisp_hdmi_audio_emu1; /* _NV_PDISP_HDMI_AUDIO_EMU1 */
+ uint nv_pdisp_hdmi_audio_emu2; /* _NV_PDISP_HDMI_AUDIO_EMU2 */
+ uint nv_pdisp_hdmi_audio_infoframe_ctrl; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL */
+ uint nv_pdisp_hdmi_audio_infoframe_status; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS */
+ uint nv_pdisp_hdmi_audio_infoframe_header; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER */ /* 0x20 */
+ uint nv_pdisp_hdmi_audio_infoframe_subpack0_low; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW */
+ uint nv_pdisp_hdmi_audio_infoframe_subpack0_high; /* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH */
+
+ uint nv_pdisp_hdmi_avi_infoframe_ctrl; /* _NV_PDISP_HDMI_AVI_INFOFRAME_CTRL */
+ uint nv_pdisp_hdmi_avi_infoframe_status; /* _NV_PDISP_HDMI_AVI_INFOFRAME_STATUS */
+ uint nv_pdisp_hdmi_avi_infoframe_header; /* _NV_PDISP_HDMI_AVI_INFOFRAME_HEADER */
+ uint nv_pdisp_hdmi_avi_infoframe_subpack0_low; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW */
+ uint nv_pdisp_hdmi_avi_infoframe_subpack0_high; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH */
+ uint nv_pdisp_hdmi_avi_infoframe_subpack1_low; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW */
+ uint nv_pdisp_hdmi_avi_infoframe_subpack1_high; /* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH */
+
+ uint nv_pdisp_hdmi_generic_ctrl; /* _NV_PDISP_HDMI_GENERIC_CTRL */
+ uint nv_pdisp_hdmi_generic_status; /* _NV_PDISP_HDMI_GENERIC_STATUS */
+ uint nv_pdisp_hdmi_generic_header; /* _NV_PDISP_HDMI_GENERIC_HEADER */
+ uint nv_pdisp_hdmi_generic_subpack0_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW */
+ uint nv_pdisp_hdmi_generic_subpack0_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH */
+ uint nv_pdisp_hdmi_generic_subpack1_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW */
+ uint nv_pdisp_hdmi_generic_subpack1_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH */
+ uint nv_pdisp_hdmi_generic_subpack2_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW */
+ uint nv_pdisp_hdmi_generic_subpack2_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH */
+ uint nv_pdisp_hdmi_generic_subpack3_low; /* _NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW */
+ uint nv_pdisp_hdmi_generic_subpack3_high; /* _NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH */
+
+ uint nv_pdisp_hdmi_acr_ctrl; /* _NV_PDISP_HDMI_ACR_CTRL */
+ uint nv_pdisp_hdmi_acr_0320_subpack_low; /* _NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_0320_subpack_high; /* _NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH */
+ uint nv_pdisp_hdmi_acr_0441_subpack_low; /* _NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_0441_subpack_high; /* _NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH */
+ uint nv_pdisp_hdmi_acr_0882_subpack_low; /* _NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_0882_subpack_high; /* _NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH */
+ uint nv_pdisp_hdmi_acr_1764_subpack_low; /* _NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_1764_subpack_high; /* _NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH */
+ uint nv_pdisp_hdmi_acr_0480_subpack_low; /* _NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_0480_subpack_high; /* _NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH */
+ uint nv_pdisp_hdmi_acr_0960_subpack_low; /* _NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_0960_subpack_high; /* _NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH */
+ uint nv_pdisp_hdmi_acr_1920_subpack_low; /* _NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW */
+ uint nv_pdisp_hdmi_acr_1920_subpack_high; /* _NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH */
+
+ uint nv_pdisp_hdmi_ctrl; /* _NV_PDISP_HDMI_CTRL */
+ uint nv_pdisp_hdmi_vsync_keepout; /* _NV_PDISP_HDMI_VSYNC_KEEPOUT */
+ uint nv_pdisp_hdmi_vsync_window; /* _NV_PDISP_HDMI_VSYNC_WINDOW */
+ uint nv_pdisp_hdmi_gcp_ctrl; /* _NV_PDISP_HDMI_GCP_CTRL */
+ uint nv_pdisp_hdmi_gcp_status; /* _NV_PDISP_HDMI_GCP_STATUS */
+ uint nv_pdisp_hdmi_gcp_subpack; /* _NV_PDISP_HDMI_GCP_SUBPACK */
+ uint nv_pdisp_hdmi_channel_status1; /* _NV_PDISP_HDMI_CHANNEL_STATUS1 */
+ uint nv_pdisp_hdmi_channel_status2; /* _NV_PDISP_HDMI_CHANNEL_STATUS2 */
+ uint nv_pdisp_hdmi_emu0; /* _NV_PDISP_HDMI_EMU0 */
+ uint nv_pdisp_hdmi_emu1; /* _NV_PDISP_HDMI_EMU1 */
+ uint nv_pdisp_hdmi_emu1_rdata; /* _NV_PDISP_HDMI_EMU1_RDATA */
+ uint nv_pdisp_hdmi_spare; /* _NV_PDISP_HDMI_SPARE */
+ uint nv_pdisp_hdmi_spdif_chn_status1; /* _NV_PDISP_HDMI_SPDIF_CHN_STATUS1 */
+ uint nv_pdisp_hdmi_spdif_chn_status2; /* _NV_PDISP_HDMI_SPDIF_CHN_STATUS2 */
+
+ uint nv_pdisp_hdcprif_rom_ctrl; /* _NV_PDISP_HDCPRIF_ROM_CTRL */
+
+ uint unused;
+
+ uint nv_pdisp_sor_cap; /* _NV_PDISP_SOR_CAP */
+ uint nv_pdisp_sor_pwr; /* _NV_PDISP_SOR_PWR */
+ uint nv_pdisp_sor_test; /* _NV_PDISP_SOR_TEST */
+ uint nv_pdisp_sor_pll0; /* _NV_PDISP_SOR_PLL0 */
+ uint nv_pdisp_sor_pll1; /* _NV_PDISP_SOR_PLL1 */
+ uint nv_pdisp_sor_pll2; /* _NV_PDISP_SOR_PLL2 */
+ uint nv_pdisp_sor_cstm; /* _NV_PDISP_SOR_CSTM */
+ uint nv_pdisp_sor_lvds; /* _NV_PDISP_SOR_LVDS */
+ uint nv_pdisp_sor_crca; /* _NV_PDISP_SOR_CRCA */
+ uint nv_pdisp_sor_crcb; /* _NV_PDISP_SOR_CRCB */
+ uint nv_pdisp_sor_blank; /* _NV_PDISP_SOR_BLANK */
+
+ uint nv_pdisp_sor_seq_ctl; /* _NV_PDISP_SOR_SEQ_CTL */
+ uint nv_pdisp_sor_seq_inst0; /* _NV_PDISP_SOR_SEQ_INST0 */
+ uint nv_pdisp_sor_seq_inst1; /* _NV_PDISP_SOR_SEQ_INST1 */
+ uint nv_pdisp_sor_seq_inst2; /* _NV_PDISP_SOR_SEQ_INST2 */
+ uint nv_pdisp_sor_seq_inst3; /* _NV_PDISP_SOR_SEQ_INST3 */
+ uint nv_pdisp_sor_seq_inst4; /* _NV_PDISP_SOR_SEQ_INST4 */
+ uint nv_pdisp_sor_seq_inst5; /* _NV_PDISP_SOR_SEQ_INST5 */
+ uint nv_pdisp_sor_seq_inst6; /* _NV_PDISP_SOR_SEQ_INST6 */
+ uint nv_pdisp_sor_seq_inst7; /* _NV_PDISP_SOR_SEQ_INST7 */
+ uint nv_pdisp_sor_seq_inst8; /* _NV_PDISP_SOR_SEQ_INST8 */
+ uint nv_pdisp_sor_seq_inst9; /* _NV_PDISP_SOR_SEQ_INST9 */
+ uint nv_pdisp_sor_seq_insta; /* _NV_PDISP_SOR_SEQ_INSTA */
+ uint nv_pdisp_sor_seq_instb; /* _NV_PDISP_SOR_SEQ_INSTB */
+ uint nv_pdisp_sor_seq_instc; /* _NV_PDISP_SOR_SEQ_INSTC */
+ uint nv_pdisp_sor_seq_instd; /* _NV_PDISP_SOR_SEQ_INSTD */
+ uint nv_pdisp_sor_seq_inste; /* _NV_PDISP_SOR_SEQ_INSTE */
+ uint nv_pdisp_sor_seq_instf; /* _NV_PDISP_SOR_SEQ_INSTF */
+
+ uint unused1[2];
+
+ uint nv_pdisp_sor_vcrca0; /* _NV_PDISP_SOR_VCRCA0 */
+ uint nv_pdisp_sor_vcrca1; /* _NV_PDISP_SOR_VCRCA1 */
+ uint nv_pdisp_sor_ccrca0; /* _NV_PDISP_SOR_CCRCA0 */
+ uint nv_pdisp_sor_ccrca1; /* _NV_PDISP_SOR_CCRCA1 */
+
+ uint nv_pdisp_sor_edataa0; /* _NV_PDISP_SOR_EDATAA0 */
+ uint nv_pdisp_sor_edataa1; /* _NV_PDISP_SOR_EDATAA1 */
+
+ uint nv_pdisp_sor_counta0; /* _NV_PDISP_SOR_COUNTA0 */
+ uint nv_pdisp_sor_counta1; /* _NV_PDISP_SOR_COUNTA1 */
+
+ uint nv_pdisp_sor_debuga0; /* _NV_PDISP_SOR_DEBUGA0 */
+ uint nv_pdisp_sor_debuga1; /* _NV_PDISP_SOR_DEBUGA1 */
+
+ uint nv_pdisp_sor_trig; /* _NV_PDISP_SOR_TRIG */
+ uint nv_pdisp_sor_mscheck; /* _NV_PDISP_SOR_MSCHECK */
+ uint nv_pdisp_sor_lane_drive_current; /* _NV_PDISP_SOR_LANE_DRIVE_CURRENT */
+
+ uint nv_pdisp_audio_debug0; /* _NV_PDISP_AUDIO_DEBUG0 0x7f */
+ uint nv_pdisp_audio_debug1; /* _NV_PDISP_AUDIO_DEBUG1 0x80 */
+ uint nv_pdisp_audio_debug2; /* _NV_PDISP_AUDIO_DEBUG2 0x81 */
+
+ uint nv_pdisp_audio_fs1; /* _NV_PDISP_AUDIO_FS1 0x82 */
+ uint nv_pdisp_audio_fs2; /* _NV_PDISP_AUDIO_FS2 */
+ uint nv_pdisp_audio_fs3; /* _NV_PDISP_AUDIO_FS3 */
+ uint nv_pdisp_audio_fs4; /* _NV_PDISP_AUDIO_FS4 */
+ uint nv_pdisp_audio_fs5; /* _NV_PDISP_AUDIO_FS5 */
+ uint nv_pdisp_audio_fs6; /* _NV_PDISP_AUDIO_FS6 */
+ uint nv_pdisp_audio_fs7; /* _NV_PDISP_AUDIO_FS7 0x88 */
+
+ uint nv_pdisp_audio_pulse_width; /* _NV_PDISP_AUDIO_PULSE_WIDTH */
+ uint nv_pdisp_audio_threshold; /* _NV_PDISP_AUDIO_THRESHOLD */
+ uint nv_pdisp_audio_cntrl0; /* _NV_PDISP_AUDIO_CNTRL0 */
+ uint nv_pdisp_audio_n; /* _NV_PDISP_AUDIO_N */
+ uint nv_pdisp_audio_nval[7]; /* _NV_PDISP_AUDIO_NVAL */
+
+ uint nv_pdisp_hdcprif_rom_timing; /* _NV_PDISP_HDCPRIF_ROM_TIMING */
+ uint nv_pdisp_sor_refclk; /* _NV_PDISP_SOR_REFCLK */
+ uint nv_pdisp_crc_control; /* _NV_PDISP_CRC_CONTROL */
+ uint nv_pdisp_input_control; /* _NV_PDISP_INPUT_CONTROL */
+ uint nv_pdisp_scratch; /* _NV_PDISP_SCRATCH */
+ uint nv_pdisp_pe_current; /* _NV_PDISP_PE_CURRENT */
+
+ uint nv_pdisp_key_ctrl; /* _NV_PDISP_KEY_CTRL */
+ uint nv_pdisp_key_debug0; /* _NV_PDISP_KEY_DEBUG0 */
+ uint nv_pdisp_key_debug1; /* _NV_PDISP_KEY_DEBUG1 */
+ uint nv_pdisp_key_debug2; /* _NV_PDISP_KEY_DEBUG2 */
+ uint nv_pdisp_key_hdcp_key_0; /* _NV_PDISP_KEY_HDCP_KEY_0 */
+ uint nv_pdisp_key_hdcp_key_1; /* _NV_PDISP_KEY_HDCP_KEY_1 */
+ uint nv_pdisp_key_hdcp_key_2; /* _NV_PDISP_KEY_HDCP_KEY_2 */
+ uint nv_pdisp_key_hdcp_key_3; /* _NV_PDISP_KEY_HDCP_KEY_3 */
+ uint nv_pdisp_key_hdcp_key_trig; /* _NV_PDISP_KEY_HDCP_KEY_3 */
+ uint nv_pdisp_key_skey_index; /* _NV_PDISP_KEY_HDCP_KEY_3 */ /* 0xa3 */
+
+ uint unused2[8];
+
+ uint nv_pdisp_sor_audio_cntrl0; /* _NV_PDISP_SOR_AUDIO_CNTRL0 */ /* 0xac */
+ uint nv_pdisp_sor_audio_debug; /* _NV_PDISP_SOR_AUDIO_DEBUG */
+ uint nv_pdisp_sor_audio_spare0; /* _NV_PDISP_SOR_AUDIO_SPARE0 */
+ uint nv_pdisp_sor_audio_nval[7]; /* _NV_PDISP_SOR_AUDIO_NVAL 0xaf ~ 0xb5 */
+ uint nv_pdisp_sor_audio_hda_scratch[4]; /* _NV_PDISP_SOR_AUDIO_HDA_SCRATCH 0xb6 ~ 0xb9 */
+ uint nv_pdisp_sor_audio_hda_codec_scratch[2]; /* _NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH 0xba ~ 0xbb */
+
+ uint nv_pdisp_sor_audio_hda_eld_bufwr; /* _NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR */
+ uint nv_pdisp_sor_audio_hda_presense; /* _NV_PDISP_SOR_AUDIO_HDA_PRESENSE */
+ uint nv_pdisp_sor_audio_hda_cp; /* _NV_PDISP_SOR_AUDIO_HDA_CP */
+ uint nv_pdisp_sor_audio_aval[8]; /* _NV_PDISP_SOR_AUDIO_AVAL */
+ uint nv_pdisp_sor_audio_gen_ctrl; /* _NV_PDISP_SOR_AUDIO_GEN_CTRL */
+
+ uint unused3[4];
+
+ uint nv_pdisp_int_status; /* _NV_PDISP_INT_STATUS */
+ uint nv_pdisp_int_mask; /* _NV_PDISP_INT_MASK */
+ uint nv_pdisp_int_enable; /* _NV_PDISP_INT_ENABLE */
+
+ uint unused4[2];
+
+ uint nv_pdisp_sor_io_peak_current; /* _NV_PDISP_SOR_IO_PEAK_CURRENT */
+ uint nv_pdisp_sor_pad_ctls0; /* _NV_PDISP_SOR_PAD_CTLS0 */
+};
+
+/* HDMI_NV_PDISP_SOR_STATE0 0x01 */
+#define SOR_STATE_UPDATE BIT(0)
+
+/* HDMI_NV_PDISP_SOR_STATE1 0x02 */
+#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE BIT(1)
+#define SOR_STATE_ASY_ORMODE_NORMAL BIT(2)
+#define SOR_STATE_ATTACHED BIT(3)
+
+/* HDMI_NV_PDISP_SOR_STATE2 0x03 */
+#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
+#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
+#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
+#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
+#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
+#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
+#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
+#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
+#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
+#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
+#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
+#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
+#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
+#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
+#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
+#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
+#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
+
+#define INFOFRAME_CTRL_ENABLE BIT(0)
+#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
+#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
+#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
+
+/* HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a */
+#define GENERIC_CTRL_ENABLE BIT(0)
+#define GENERIC_CTRL_OTHER BIT(4)
+#define GENERIC_CTRL_SINGLE BIT(8)
+#define GENERIC_CTRL_HBLANK BIT(12)
+#define GENERIC_CTRL_AUDIO BIT(16)
+
+/* HDMI_NV_PDISP_HDMI_ACR_* */
+#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
+#define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
+#define ACR_ENABLE BIT(31)
+
+/* HDMI_NV_PDISP_HDMI_CTRL 0x44 */
+#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
+#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
+#define HDMI_CTRL_ENABLE BIT(30)
+
+/* HDMI_NV_PDISP_HDMI_VSYNC_* */
+#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
+#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
+#define VSYNC_WINDOW_ENABLE BIT(31)
+
+/* HDMI_NV_PDISP_HDMI_SPARE 0x4f */
+#define SPARE_HW_CTS BIT(0)
+#define SPARE_FORCE_SW_CTS BIT(1)
+#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
+
+/* HDMI_NV_PDISP_SOR_PWR 0x55 */
+#define SOR_PWR_NORMAL_STATE_PD (0 << 0)
+#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
+#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
+#define SOR_PWR_NORMAL_START_ALT (1 << 1)
+#define SOR_PWR_SAFE_STATE_PD (0 << 16)
+#define SOR_PWR_SAFE_STATE_PU (1 << 16)
+#define SOR_PWR_SETTING_NEW_DONE (0 << 31)
+#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
+#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
+
+/* HDMI_NV_PDISP_SOR_PLL0 0x57 */
+#define SOR_PLL_PWR BIT(0)
+#define SOR_PLL_PDBG BIT(1)
+#define SOR_PLL_VCAPD BIT(2)
+#define SOR_PLL_PDPORT BIT(3)
+#define SOR_PLL_RESISTORSEL BIT(4)
+#define SOR_PLL_PULLDOWN BIT(5)
+#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
+#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
+#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
+#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
+#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
+
+/* HDMI_NV_PDISP_SOR_PLL1 0x58 */
+#define SOR_PLL_TMDS_TERM_ENABLE BIT(8)
+#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
+#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
+#define SOR_PLL_PE_EN BIT(28)
+#define SOR_PLL_HALF_FULL_PE BIT(29)
+#define SOR_PLL_S_D_PIN_PE BIT(30)
+
+/* HDMI_NV_PDISP_SOR_CSTM 0x5a */
+#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
+#define SOR_CSTM_PLLDIV BIT(21)
+#define SOR_CSTM_LVDS_ENABLE BIT(16)
+#define SOR_CSTM_MODE_LVDS (0 << 12)
+#define SOR_CSTM_MODE_TMDS (1 << 12)
+#define SOR_CSTM_MODE_MASK (3 << 12)
+
+/* HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f */
+#define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
+#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
+#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
+#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
+#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
+#define SOR_SEQ_STATUS BIT(28)
+#define SOR_SEQ_SWITCH BIT(30)
+
+/* HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x)) */
+#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
+#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
+#define SOR_SEQ_INST_HALT (1 << 15)
+#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
+#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
+#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
+#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
+#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
+
+/* HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e */
+#define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
+#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
+#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
+#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
+#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)
+#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)
+#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
+#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
+
+/* Drive current list */
+enum {
+ DRIVE_CURRENT_1_500_mA,
+ DRIVE_CURRENT_1_875_mA,
+ DRIVE_CURRENT_2_250_mA,
+ DRIVE_CURRENT_2_625_mA,
+ DRIVE_CURRENT_3_000_mA,
+ DRIVE_CURRENT_3_375_mA,
+ DRIVE_CURRENT_3_750_mA,
+ DRIVE_CURRENT_4_125_mA,
+ DRIVE_CURRENT_4_500_mA,
+ DRIVE_CURRENT_4_875_mA,
+ DRIVE_CURRENT_5_250_mA,
+ DRIVE_CURRENT_5_625_mA,
+ DRIVE_CURRENT_6_000_mA,
+ DRIVE_CURRENT_6_375_mA,
+ DRIVE_CURRENT_6_750_mA,
+ DRIVE_CURRENT_7_125_mA,
+ DRIVE_CURRENT_7_500_mA,
+ DRIVE_CURRENT_7_875_mA,
+ DRIVE_CURRENT_8_250_mA,
+ DRIVE_CURRENT_8_625_mA,
+ DRIVE_CURRENT_9_000_mA,
+ DRIVE_CURRENT_9_375_mA,
+ DRIVE_CURRENT_9_750_mA,
+ DRIVE_CURRENT_10_125_mA,
+ DRIVE_CURRENT_10_500_mA,
+ DRIVE_CURRENT_10_875_mA,
+ DRIVE_CURRENT_11_250_mA,
+ DRIVE_CURRENT_11_625_mA,
+ DRIVE_CURRENT_12_000_mA,
+ DRIVE_CURRENT_12_375_mA,
+ DRIVE_CURRENT_12_750_mA,
+ DRIVE_CURRENT_13_125_mA,
+ DRIVE_CURRENT_13_500_mA,
+ DRIVE_CURRENT_13_875_mA,
+ DRIVE_CURRENT_14_250_mA,
+ DRIVE_CURRENT_14_625_mA,
+ DRIVE_CURRENT_15_000_mA,
+ DRIVE_CURRENT_15_375_mA,
+ DRIVE_CURRENT_15_750_mA,
+ DRIVE_CURRENT_16_125_mA,
+ DRIVE_CURRENT_16_500_mA,
+ DRIVE_CURRENT_16_875_mA,
+ DRIVE_CURRENT_17_250_mA,
+ DRIVE_CURRENT_17_625_mA,
+ DRIVE_CURRENT_18_000_mA,
+ DRIVE_CURRENT_18_375_mA,
+ DRIVE_CURRENT_18_750_mA,
+ DRIVE_CURRENT_19_125_mA,
+ DRIVE_CURRENT_19_500_mA,
+ DRIVE_CURRENT_19_875_mA,
+ DRIVE_CURRENT_20_250_mA,
+ DRIVE_CURRENT_20_625_mA,
+ DRIVE_CURRENT_21_000_mA,
+ DRIVE_CURRENT_21_375_mA,
+ DRIVE_CURRENT_21_750_mA,
+ DRIVE_CURRENT_22_125_mA,
+ DRIVE_CURRENT_22_500_mA,
+ DRIVE_CURRENT_22_875_mA,
+ DRIVE_CURRENT_23_250_mA,
+ DRIVE_CURRENT_23_625_mA,
+ DRIVE_CURRENT_24_000_mA,
+ DRIVE_CURRENT_24_375_mA,
+ DRIVE_CURRENT_24_750_mA,
+};
+
+/* Drive current list for T114 */
+enum {
+ DRIVE_CURRENT_0_000_mA_T114,
+ DRIVE_CURRENT_0_400_mA_T114,
+ DRIVE_CURRENT_0_800_mA_T114,
+ DRIVE_CURRENT_1_200_mA_T114,
+ DRIVE_CURRENT_1_600_mA_T114,
+ DRIVE_CURRENT_2_000_mA_T114,
+ DRIVE_CURRENT_2_400_mA_T114,
+ DRIVE_CURRENT_2_800_mA_T114,
+ DRIVE_CURRENT_3_200_mA_T114,
+ DRIVE_CURRENT_3_600_mA_T114,
+ DRIVE_CURRENT_4_000_mA_T114,
+ DRIVE_CURRENT_4_400_mA_T114,
+ DRIVE_CURRENT_4_800_mA_T114,
+ DRIVE_CURRENT_5_200_mA_T114,
+ DRIVE_CURRENT_5_600_mA_T114,
+ DRIVE_CURRENT_6_000_mA_T114,
+ DRIVE_CURRENT_6_400_mA_T114,
+ DRIVE_CURRENT_6_800_mA_T114,
+ DRIVE_CURRENT_7_200_mA_T114,
+ DRIVE_CURRENT_7_600_mA_T114,
+ DRIVE_CURRENT_8_000_mA_T114,
+ DRIVE_CURRENT_8_400_mA_T114,
+ DRIVE_CURRENT_8_800_mA_T114,
+ DRIVE_CURRENT_9_200_mA_T114,
+ DRIVE_CURRENT_9_600_mA_T114,
+ DRIVE_CURRENT_10_000_mA_T114,
+ DRIVE_CURRENT_10_400_mA_T114,
+ DRIVE_CURRENT_10_800_mA_T114,
+ DRIVE_CURRENT_11_200_mA_T114,
+ DRIVE_CURRENT_11_600_mA_T114,
+ DRIVE_CURRENT_12_000_mA_T114,
+ DRIVE_CURRENT_12_400_mA_T114,
+ DRIVE_CURRENT_12_800_mA_T114,
+ DRIVE_CURRENT_13_200_mA_T114,
+ DRIVE_CURRENT_13_600_mA_T114,
+ DRIVE_CURRENT_14_000_mA_T114,
+ DRIVE_CURRENT_14_400_mA_T114,
+ DRIVE_CURRENT_14_800_mA_T114,
+ DRIVE_CURRENT_15_200_mA_T114,
+ DRIVE_CURRENT_15_600_mA_T114,
+ DRIVE_CURRENT_16_000_mA_T114,
+ DRIVE_CURRENT_16_400_mA_T114,
+ DRIVE_CURRENT_16_800_mA_T114,
+ DRIVE_CURRENT_17_200_mA_T114,
+ DRIVE_CURRENT_17_600_mA_T114,
+ DRIVE_CURRENT_18_000_mA_T114,
+ DRIVE_CURRENT_18_400_mA_T114,
+ DRIVE_CURRENT_18_800_mA_T114,
+ DRIVE_CURRENT_19_200_mA_T114,
+ DRIVE_CURRENT_19_600_mA_T114,
+ DRIVE_CURRENT_20_000_mA_T114,
+ DRIVE_CURRENT_20_400_mA_T114,
+ DRIVE_CURRENT_20_800_mA_T114,
+ DRIVE_CURRENT_21_200_mA_T114,
+ DRIVE_CURRENT_21_600_mA_T114,
+ DRIVE_CURRENT_22_000_mA_T114,
+ DRIVE_CURRENT_22_400_mA_T114,
+ DRIVE_CURRENT_22_800_mA_T114,
+ DRIVE_CURRENT_23_200_mA_T114,
+ DRIVE_CURRENT_23_600_mA_T114,
+ DRIVE_CURRENT_24_000_mA_T114,
+ DRIVE_CURRENT_24_400_mA_T114,
+ DRIVE_CURRENT_24_800_mA_T114,
+ DRIVE_CURRENT_25_200_mA_T114,
+ DRIVE_CURRENT_25_400_mA_T114,
+ DRIVE_CURRENT_25_800_mA_T114,
+ DRIVE_CURRENT_26_200_mA_T114,
+ DRIVE_CURRENT_26_600_mA_T114,
+ DRIVE_CURRENT_27_000_mA_T114,
+ DRIVE_CURRENT_27_400_mA_T114,
+ DRIVE_CURRENT_27_800_mA_T114,
+ DRIVE_CURRENT_28_200_mA_T114,
+};
+
+/* HDMI_NV_PDISP_AUDIO_FS */
+#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
+#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
+
+/* HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b */
+#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
+#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
+#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
+#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
+#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
+
+/* HDMI_NV_PDISP_AUDIO_N 0x8c */
+#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
+#define AUDIO_N_RESETF (1 << 20)
+#define AUDIO_N_GENERATE_NORMAL (0 << 24)
+#define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
+
+/* HDMI_NV_PDISP_SOR_REFCLK 0x95 */
+#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
+#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
+
+/* HDMI_NV_PDISP_INPUT_CONTROL 0x97 */
+#define HDMI_SRC_DISPLAYA (0 << 0)
+#define HDMI_SRC_DISPLAYB (1 << 0)
+#define ARM_VIDEO_RANGE_FULL (0 << 1)
+#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
+
+/* HDMI_NV_PDISP_PE_CURRENT 0x99 */
+#define PE_CURRENT0(x) (((x) & 0xf) << 0)
+#define PE_CURRENT1(x) (((x) & 0xf) << 8)
+#define PE_CURRENT2(x) (((x) & 0xf) << 16)
+#define PE_CURRENT3(x) (((x) & 0xf) << 24)
+
+enum {
+ PE_CURRENT_0_0_mA,
+ PE_CURRENT_0_5_mA,
+ PE_CURRENT_1_0_mA,
+ PE_CURRENT_1_5_mA,
+ PE_CURRENT_2_0_mA,
+ PE_CURRENT_2_5_mA,
+ PE_CURRENT_3_0_mA,
+ PE_CURRENT_3_5_mA,
+ PE_CURRENT_4_0_mA,
+ PE_CURRENT_4_5_mA,
+ PE_CURRENT_5_0_mA,
+ PE_CURRENT_5_5_mA,
+ PE_CURRENT_6_0_mA,
+ PE_CURRENT_6_5_mA,
+ PE_CURRENT_7_0_mA,
+ PE_CURRENT_7_5_mA,
+};
+
+enum {
+ PE_CURRENT_0_mA_T114,
+ PE_CURRENT_1_mA_T114,
+ PE_CURRENT_2_mA_T114,
+ PE_CURRENT_3_mA_T114,
+ PE_CURRENT_4_mA_T114,
+ PE_CURRENT_5_mA_T114,
+ PE_CURRENT_6_mA_T114,
+ PE_CURRENT_7_mA_T114,
+ PE_CURRENT_8_mA_T114,
+ PE_CURRENT_9_mA_T114,
+ PE_CURRENT_10_mA_T114,
+ PE_CURRENT_11_mA_T114,
+ PE_CURRENT_12_mA_T114,
+ PE_CURRENT_13_mA_T114,
+ PE_CURRENT_14_mA_T114,
+ PE_CURRENT_15_mA_T114,
+};
+
+/* HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac */
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
+#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
+
+/* HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0xae */
+#define SOR_AUDIO_SPARE0_HBR_ENABLE BIT(27)
+
+/* HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0xba */
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID BIT(30)
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
+
+/* HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd */
+#define SOR_AUDIO_HDA_PRESENSE_VALID BIT(1)
+#define SOR_AUDIO_HDA_PRESENSE_PRESENT BIT(0)
+
+/* HDMI_NV_PDISP_INT_STATUS 0xcc */
+#define INT_SCRATCH BIT(3)
+#define INT_CP_REQUEST BIT(2)
+#define INT_CODEC_SCRATCH1 BIT(1)
+#define INT_CODEC_SCRATCH0 BIT(0)
+
+/* HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1 */
+#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
+#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)
+#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
+#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
+
+enum {
+ PEAK_CURRENT_0_000_mA,
+ PEAK_CURRENT_0_200_mA,
+ PEAK_CURRENT_0_400_mA,
+ PEAK_CURRENT_0_600_mA,
+ PEAK_CURRENT_0_800_mA,
+ PEAK_CURRENT_1_000_mA,
+ PEAK_CURRENT_1_200_mA,
+ PEAK_CURRENT_1_400_mA,
+ PEAK_CURRENT_1_600_mA,
+ PEAK_CURRENT_1_800_mA,
+ PEAK_CURRENT_2_000_mA,
+ PEAK_CURRENT_2_200_mA,
+ PEAK_CURRENT_2_400_mA,
+ PEAK_CURRENT_2_600_mA,
+ PEAK_CURRENT_2_800_mA,
+ PEAK_CURRENT_3_000_mA,
+ PEAK_CURRENT_3_200_mA,
+ PEAK_CURRENT_3_400_mA,
+ PEAK_CURRENT_3_600_mA,
+ PEAK_CURRENT_3_800_mA,
+ PEAK_CURRENT_4_000_mA,
+ PEAK_CURRENT_4_200_mA,
+ PEAK_CURRENT_4_400_mA,
+ PEAK_CURRENT_4_600_mA,
+ PEAK_CURRENT_4_800_mA,
+ PEAK_CURRENT_5_000_mA,
+ PEAK_CURRENT_5_200_mA,
+ PEAK_CURRENT_5_400_mA,
+ PEAK_CURRENT_5_600_mA,
+ PEAK_CURRENT_5_800_mA,
+ PEAK_CURRENT_6_000_mA,
+ PEAK_CURRENT_6_200_mA,
+ PEAK_CURRENT_6_400_mA,
+ PEAK_CURRENT_6_600_mA,
+ PEAK_CURRENT_6_800_mA,
+ PEAK_CURRENT_7_000_mA,
+ PEAK_CURRENT_7_200_mA,
+ PEAK_CURRENT_7_400_mA,
+ PEAK_CURRENT_7_600_mA,
+ PEAK_CURRENT_7_800_mA,
+ PEAK_CURRENT_8_000_mA,
+ PEAK_CURRENT_8_200_mA,
+ PEAK_CURRENT_8_400_mA,
+ PEAK_CURRENT_8_600_mA,
+ PEAK_CURRENT_8_800_mA,
+ PEAK_CURRENT_9_000_mA,
+ PEAK_CURRENT_9_200_mA,
+ PEAK_CURRENT_9_400_mA,
+};
+
+#endif /* _TEGRA_HDMI_H */
diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra20/tegra-host1x.c
new file mode 100644
index 0000000..58ab871
--- /dev/null
+++ b/drivers/video/tegra20/tegra-host1x.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <log.h>
+#include <reset.h>
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+struct tegra_host1x_info {
+ u32 clk_parent;
+ u32 rate;
+};
+
+static int tegra_host1x_probe(struct udevice *dev)
+{
+ struct clk *clk;
+ struct reset_ctl reset_ctl;
+ const struct tegra_host1x_info *info;
+ int ret;
+
+ clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(clk)) {
+ log_debug("%s: cannot get HOST1X clock: %ld\n",
+ __func__, PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+
+ ret = reset_get_by_name(dev, "host1x", &reset_ctl);
+ if (ret) {
+ log_debug("%s: cannot get HOST1X reset: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ info = (struct tegra_host1x_info *)dev_get_driver_data(dev);
+
+ reset_assert(&reset_ctl);
+ clock_start_periph_pll(clk->id, info->clk_parent, info->rate);
+
+ mdelay(2);
+ reset_deassert(&reset_ctl);
+
+ return 0;
+}
+
+static const struct tegra_host1x_info tegra20_host1x_info = {
+ .clk_parent = CLOCK_ID_CGENERAL,
+ .rate = 150000000, /* 150 MHz */
+};
+
+static const struct tegra_host1x_info tegra114_host1x_info = {
+ .clk_parent = CLOCK_ID_PERIPH,
+ .rate = 136000000, /* 136 MHz */
+};
+
+static const struct udevice_id tegra_host1x_ids[] = {
+ {
+ .compatible = "nvidia,tegra20-host1x",
+ .data = (ulong)&tegra20_host1x_info
+ }, {
+ .compatible = "nvidia,tegra30-host1x",
+ .data = (ulong)&tegra20_host1x_info
+ }, {
+ .compatible = "nvidia,tegra114-host1x",
+ .data = (ulong)&tegra114_host1x_info
+ }, {
+ .compatible = "nvidia,tegra124-host1x",
+ .data = (ulong)&tegra114_host1x_info
+ }, {
+ /* sentinel */
+ }
+};
+
+U_BOOT_DRIVER(tegra_host1x) = {
+ .name = "tegra_host1x",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = tegra_host1x_ids,
+ .probe = tegra_host1x_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c
index 79d8a02..998f0df 100644
--- a/drivers/video/tegra20/tegra-pwm-backlight.c
+++ b/drivers/video/tegra20/tegra-pwm-backlight.c
@@ -17,9 +17,6 @@
#include "tegra-dc.h"
-#define TEGRA_DISPLAY_A_BASE 0x54200000
-#define TEGRA_DISPLAY_B_BASE 0x54240000
-
#define TEGRA_PWM_BL_MIN_BRIGHTNESS 0x10
#define TEGRA_PWM_BL_MAX_BRIGHTNESS 0xFF
@@ -106,14 +103,11 @@
static int tegra_pwm_backlight_probe(struct udevice *dev)
{
struct tegra_pwm_backlight_priv *priv = dev_get_priv(dev);
+ ofnode dc = ofnode_get_parent(dev_ofnode(dev));
- if (dev_read_bool(dev, "nvidia,display-b-base"))
- priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_B_BASE;
- else
- priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_A_BASE;
-
+ priv->dc = (struct dc_ctlr *)ofnode_get_addr(dc);
if (!priv->dc) {
- log_err("no display controller address\n");
+ log_err("%s: failed to get DC controller\n", __func__);
return -EINVAL;
}
diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c
index 493e2f1..340c792 100644
--- a/drivers/video/ti/tilcdc.c
+++ b/drivers/video/ti/tilcdc.c
@@ -234,7 +234,7 @@
return -EINVAL;
}
- err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev);
+ err = uclass_get_device_by_name(UCLASS_CLK, "clock-lcd-gclk@534", &clk_dev);
if (err) {
dev_err(dev, "failed to get lcd_gclk device\n");
return err;
@@ -252,7 +252,7 @@
return rate;
}
- err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4",
+ err = uclass_get_device_by_name(UCLASS_CLK, "clock-dpll-disp-m2@4a4",
&clk_dev);
if (err) {
dev_err(dev, "failed to get dpll_disp_m2 clock device\n");
diff --git a/drivers/watchdog/da9063-wdt.c b/drivers/watchdog/da9063-wdt.c
index b7216b5..ec9bc03 100644
--- a/drivers/watchdog/da9063-wdt.c
+++ b/drivers/watchdog/da9063-wdt.c
@@ -145,5 +145,4 @@
.id = UCLASS_WDT,
.of_match = da9063_wdt_ids,
.ops = &da9063_wdt_ops,
- .flags = DM_FLAG_PROBE_AFTER_BIND,
};
diff --git a/fs/fs.c b/fs/fs.c
index 30a8e50..cda85a2 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -574,7 +574,7 @@
lmb_dump_all();
- if (lmb_alloc_addr(addr, read_len, LMB_NONE) == addr)
+ if (!lmb_alloc_addr(addr, read_len, LMB_NONE))
return 0;
log_err("** Reading file would overwrite reserved memory **\n");
diff --git a/include/blkmap.h b/include/blkmap.h
index d530954..57555fd 100644
--- a/include/blkmap.h
+++ b/include/blkmap.h
@@ -7,6 +7,7 @@
#ifndef _BLKMAP_H
#define _BLKMAP_H
+#include <blk.h>
#include <dm/lists.h>
/**
@@ -60,10 +61,12 @@
* @blknr: Start block number of the mapping
* @blkcnt: Number of blocks to map
* @paddr: The target physical memory address of the mapping
+ * @preserve: Mapping intended to be preserved for subsequent stages,
+ * like the OS (e.g. ISO installer)
* Returns: 0 on success, negative error code on failure
*/
int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
- phys_addr_t paddr);
+ phys_addr_t paddr, bool preserve);
/**
* blkmap_from_label() - Find blkmap from label
@@ -102,4 +105,32 @@
int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
struct udevice **devp);
+/**
+ * blkmap_get_preserved_pmem_slices() - Look for memory mapped preserved slices
+ * @cb: Callback function to call for the blkmap slice
+ * @ctx: Argument to be passed to the callback function
+ *
+ * The function is used to iterate through all the blkmap slices, looking
+ * specifically for memory mapped blkmap mapping which has been
+ * created with the preserve attribute. The function looks for such slices
+ * with the relevant attributes and then calls the callback function which
+ * then does additional configuration as needed. The callback function is
+ * invoked for all the discovered slices, unless there is an error returned
+ * by the callback, in which case the function returns that error.
+ *
+ * The callback function has the following arguments
+ * @ctx: Argument to be passed to the callback function
+ * @addr: Start address of the memory mapped slice
+ * @size: Size of the memory mapped slice
+ *
+ * Typically, the callback will perform some configuration needed for the
+ * information passed on to it. An example of this would be setting up the
+ * pmem node in a device-tree(passed through the ctx argument) with the
+ * parameters passed on to the callback.
+ *
+ * Return: 0 on success, negative error on failure
+ */
+int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr,
+ u64 size), void *ctx);
+
#endif /* _BLKMAP_H */
diff --git a/include/bootm.h b/include/bootm.h
index 6116070..465577a 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -44,6 +44,21 @@
* @argc: Number of arguments to the command (excluding the actual command).
* This is 0 if there are no arguments
* @argv: NULL-terminated list of arguments, or NULL if there are no arguments
+ *
+ * For zboot:
+ * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already
+ * been loaded and does not exist (as a cohesive whole) in memory
+ * @bzimage_size: Size of the bzImage, or 0 to detect this
+ * @initrd_addr: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @load_address: Address where the bzImage is moved before booting, either
+ * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * This is set up when loading the zimage
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ * This is set up when loading the zimage
+ * @cmdline: Environment variable containing the 'override' command line, or
+ * NULL to use the one in the setup block
*/
struct bootm_info {
const char *addr_img;
@@ -54,11 +69,39 @@
const char *cmd_name;
int argc;
char *const *argv;
+
+ /* zboot items */
+#ifdef CONFIG_X86
+ ulong bzimage_addr;
+ ulong bzimage_size;
+ ulong initrd_addr;
+ ulong initrd_size;
+ ulong load_address;
+ struct boot_params *base_ptr;
+ const char *cmdline;
+#endif
};
+/* macro to allow setting fields in generic code */
+#ifdef CONFIG_X86
+#define bootm_x86_set(_bmi, _field, _val) (_bmi)->_field = (_val)
+#else
+#define bootm_x86_set(_bmi, _field, _val)
+#endif
+
+static inline ulong bootm_len(void)
+{
+#ifdef CONFIG_SYS_BOOTM_LEN
+ return CONFIG_SYS_BOOTM_LEN;
+#endif
+ return 0;
+}
+
/**
* bootm_init() - Set up a bootm_info struct with useful defaults
*
+ * @bmi: Bootm information
+ *
* Set up the struct with default values for all members:
* @boot_progress is set to true and @images is set to the global images
* variable. Everything else is set to NULL except @argc which is 0
@@ -74,7 +117,7 @@
* - disabled interrupts.
*
* @flag: Flags indicating what to do (BOOTM_STATE_...)
- * bmi: Bootm information
+ * @bmi: Bootm information
* Return: 1 on error. On success the OS boots so this function does
* not return.
*/
@@ -275,6 +318,15 @@
/**
* zboot_run() - Run through the various steps to boot a zimage
*
+ * @bmi: Bootm information, with bzimage_size, initrd_addr, initrd_size and
+ * cmdline set up. If base_ptr is 0, then bzimage_addr must be set to the start
+ * of the bzImage. Otherwise base_ptr and load_address must be provided.
+ */
+int zboot_run(struct bootm_info *bmi);
+
+/**
+ * zboot_run_args() - Run through the various steps to boot a zimage
+ *
* Boot a zimage, given the component parts
*
* @addr: Address where the bzImage is moved before booting, either
@@ -289,8 +341,8 @@
* to use for booting
* Return: -EFAULT on error (normally it does not return)
*/
-int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size,
- ulong base, char *cmdline);
+int zboot_run_args(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+ ulong base, char *cmdline);
/*
* zimage_get_kernel_version() - Get the version string from a kernel
@@ -307,11 +359,10 @@
*
* This shows all available information in a zimage that has been loaded.
*
- * @base_ptr: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
+ * @bmi: Bootm information, with valid base_ptr
* @show_cmdline: true to show the full command line
*/
-void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
+void zimage_dump(struct bootm_info *bmi, bool show_cmdline);
/*
* bootm_boot_start() - Boot an image at the given address
diff --git a/include/cadence-nand.h b/include/cadence-nand.h
new file mode 100644
index 0000000..27ed217
--- /dev/null
+++ b/include/cadence-nand.h
@@ -0,0 +1,529 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cadence NAND flash controller driver
+ *
+ * Copyright (C) 2019 Cadence
+ *
+ * Author: Piotr Sroka <piotrs@cadence.com>
+ *
+ */
+
+#ifndef _CADENCE_NAND_H_
+#define _CADENCE_NAND_H_
+#include <clk.h>
+#include <reset.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+
+/*
+ * HPNFC can work in 3 modes:
+ * - PIO - can work in master or slave DMA
+ * - CDMA - needs Master DMA for accessing command descriptors.
+ * - Generic mode - can use only slave DMA.
+ * CDMA and PIO modes can be used to execute only base commands.
+ * CDMA and PIO modes can be used to execute only base commands.
+ * Generic mode can be used to execute any command
+ * on NAND flash memory. Driver uses CDMA mode for
+ * block erasing, page reading, page programing.
+ * Generic mode is used for executing rest of commands.
+ */
+
+#define DMA_DATA_SIZE_ALIGN 8
+
+/* Register definition. */
+/*
+ * Command register 0.
+ * Writing data to this register will initiate a new transaction
+ * of the NF controller.
+ */
+#define CMD_REG0 0x0000
+/* Command type field mask. */
+#define CMD_REG0_CT GENMASK(31, 30)
+/* Command type CDMA. */
+#define CMD_REG0_CT_CDMA 0uL
+/* Command type generic. */
+#define CMD_REG0_CT_GEN 3uL
+/* Command thread number field mask. */
+#define CMD_REG0_TN GENMASK(27, 24)
+
+/* Command register 2. */
+#define CMD_REG2 0x0008
+/* Command register 3. */
+#define CMD_REG3 0x000C
+/* Pointer register to select which thread status will be selected. */
+#define CMD_STATUS_PTR 0x0010
+/* Command status register for selected thread. */
+#define CMD_STATUS 0x0014
+
+/* Interrupt status register. */
+#define INTR_STATUS 0x0110
+#define INTR_STATUS_SDMA_ERR BIT(22)
+#define INTR_STATUS_SDMA_TRIGG BIT(21)
+#define INTR_STATUS_UNSUPP_CMD BIT(19)
+#define INTR_STATUS_DDMA_TERR BIT(18)
+#define INTR_STATUS_CDMA_TERR BIT(17)
+#define INTR_STATUS_CDMA_IDL BIT(16)
+
+/* Interrupt enable register. */
+#define INTR_ENABLE 0x0114
+#define INTR_ENABLE_INTR_EN BIT(31)
+
+/* Controller internal state. */
+#define CTRL_STATUS 0x0118
+#define CTRL_STATUS_INIT_COMP BIT(9)
+#define CTRL_STATUS_CTRL_BUSY BIT(8)
+
+/* Command Engine threads state. */
+#define TRD_STATUS 0x0120
+
+/* Command Engine interrupt thread error status. */
+#define TRD_ERR_INT_STATUS 0x0128
+/* Command Engine interrupt thread error enable. */
+#define TRD_ERR_INT_STATUS_EN 0x0130
+/* Command Engine interrupt thread complete status. */
+#define TRD_COMP_INT_STATUS 0x0138
+
+/*
+ * Transfer config 0 register.
+ * Configures data transfer parameters.
+ */
+#define TRAN_CFG_0 0x0400
+/* Offset value from the beginning of the page. */
+#define TRAN_CFG_0_OFFSET GENMASK(31, 16)
+/* Numbers of sectors to transfer within singlNF device's page. */
+#define TRAN_CFG_0_SEC_CNT GENMASK(7, 0)
+
+/*
+ * Transfer config 1 register.
+ * Configures data transfer parameters.
+ */
+#define TRAN_CFG_1 0x0404
+/* Size of last data sector. */
+#define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16)
+/* Size of not-last data sector. */
+#define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0)
+
+/* ECC engine configuration register 0. */
+#define ECC_CONFIG_0 0x0428
+/* Correction strength. */
+#define ECC_CONFIG_0_CORR_STR GENMASK(10, 8)
+/* Enable erased pages detection mechanism. */
+#define ECC_CONFIG_0_ERASE_DET_EN BIT(1)
+/* Enable controller ECC check bits generation and correction. */
+#define ECC_CONFIG_0_ECC_EN BIT(0)
+
+/* ECC engine configuration register 1. */
+#define ECC_CONFIG_1 0x042C
+
+/* Multiplane settings register. */
+#define MULTIPLANE_CFG 0x0434
+/* Cache operation settings. */
+#define CACHE_CFG 0x0438
+
+/* Transferred data block size for the slave DMA module. */
+#define SDMA_SIZE 0x0440
+
+/* Thread number associated with transferred data block
+ * for the slave DMA module.
+ */
+#define SDMA_TRD_NUM 0x0444
+/* Thread number mask. */
+#define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0)
+
+#define CONTROL_DATA_CTRL 0x0494
+/* Thread number mask. */
+#define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0)
+
+#define CTRL_VERSION 0x800
+#define CTRL_VERSION_REV GENMASK(7, 0)
+
+/* Available hardware features of the controller. */
+#define CTRL_FEATURES 0x804
+/* Support for NV-DDR2/3 work mode. */
+#define CTRL_FEATURES_NVDDR_2_3 BIT(28)
+/* Support for NV-DDR work mode. */
+#define CTRL_FEATURES_NVDDR BIT(27)
+/* Support for asynchronous work mode. */
+#define CTRL_FEATURES_ASYNC BIT(26)
+/* Support for asynchronous work mode. */
+#define CTRL_FEATURES_N_BANKS GENMASK(25, 24)
+/* Slave and Master DMA data width. */
+#define CTRL_FEATURES_DMA_DWITH64 BIT(21)
+/* Availability of Control Data feature.*/
+#define CTRL_FEATURES_CONTROL_DATA BIT(10)
+
+/* BCH Engine identification register 0 - correction strengths. */
+#define BCH_CFG_0 0x838
+#define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0)
+#define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8)
+#define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16)
+#define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24)
+
+/* BCH Engine identification register 1 - correction strengths. */
+#define BCH_CFG_1 0x83C
+#define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0)
+#define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8)
+#define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16)
+#define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24)
+
+/* BCH Engine identification register 2 - sector sizes. */
+#define BCH_CFG_2 0x840
+#define BCH_CFG_2_SECT_0 GENMASK(15, 0)
+#define BCH_CFG_2_SECT_1 GENMASK(31, 16)
+
+/* BCH Engine identification register 3. */
+#define BCH_CFG_3 0x844
+#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
+
+/* Ready/Busy# line status. */
+#define RBN_SETINGS 0x1004
+
+/* Common settings. */
+#define COMMON_SET 0x1008
+/* 16 bit device connected to the NAND Flash interface. */
+#define COMMON_SET_DEVICE_16BIT BIT(8)
+
+/* Skip_bytes registers. */
+#define SKIP_BYTES_CONF 0x100C
+#define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16)
+#define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0)
+
+#define SKIP_BYTES_OFFSET 0x1010
+#define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0)
+
+/* Timings configuration. */
+#define ASYNC_TOGGLE_TIMINGS 0x101c
+#define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24)
+#define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16)
+#define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8)
+#define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0)
+
+#define TIMINGS0 0x1024
+#define TIMINGS0_TADL GENMASK(31, 24)
+#define TIMINGS0_TCCS GENMASK(23, 16)
+#define TIMINGS0_TWHR GENMASK(15, 8)
+#define TIMINGS0_TRHW GENMASK(7, 0)
+
+#define TIMINGS1 0x1028
+#define TIMINGS1_TRHZ GENMASK(31, 24)
+#define TIMINGS1_TWB GENMASK(23, 16)
+#define TIMINGS1_TVDLY GENMASK(7, 0)
+
+#define TIMINGS2 0x102c
+#define TIMINGS2_TFEAT GENMASK(25, 16)
+#define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8)
+#define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0)
+
+/* Configuration of the resynchronization of slave DLL of PHY. */
+#define DLL_PHY_CTRL 0x1034
+#define DLL_PHY_CTRL_DLL_RST_N BIT(24)
+#define DLL_PHY_CTRL_EXTENDED_WR_MODE BIT(17)
+#define DLL_PHY_CTRL_EXTENDED_RD_MODE BIT(16)
+#define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8)
+#define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0)
+
+/* TODO: - Identify better way to handle PHY address */
+#define PHY_OFFSET 0x10000
+
+/* Register controlling DQ related timing. */
+#define PHY_DQ_TIMING PHY_OFFSET + 0x2000
+/* Register controlling DSQ related timing. */
+#define PHY_DQS_TIMING PHY_OFFSET + 0x2004
+#define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0)
+#define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16)
+#define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20)
+
+/* Register controlling the gate and loopback control related timing. */
+#define PHY_GATE_LPBK_CTRL PHY_OFFSET + 0x2008
+#define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19)
+
+/* Register holds the control for the master DLL logic. */
+#define PHY_DLL_MASTER_CTRL PHY_OFFSET + 0x200C
+#define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23)
+
+/* Register holds the control for the slave DLL logic. */
+#define PHY_DLL_SLAVE_CTRL PHY_OFFSET + 0x2010
+
+/* This register handles the global control settings for the PHY. */
+#define PHY_CTRL PHY_OFFSET + 0x2080
+#define PHY_CTRL_SDR_DQS BIT(14)
+#define PHY_CTRL_PHONY_DQS GENMASK(9, 4)
+
+/*
+ * This register handles the global control settings
+ * for the termination selects for reads.
+ */
+#define PHY_TSEL PHY_OFFSET + 0x2084
+
+/* Generic command layout. */
+#define GCMD_LAY_CS GENMASK_ULL(11, 8)
+/*
+ * This bit informs the minicotroller if it has to wait for tWB
+ * after sending the last CMD/ADDR/DATA in the sequence.
+ */
+#define GCMD_LAY_TWB BIT_ULL(6)
+/* Type of generic instruction. */
+#define GCMD_LAY_INSTR GENMASK_ULL(5, 0)
+
+/* Generic CMD sequence type. */
+#define GCMD_LAY_INSTR_CMD 0
+/* Generic ADDR sequence type. */
+#define GCMD_LAY_INSTR_ADDR 1
+/* Generic data transfer sequence type. */
+#define GCMD_LAY_INSTR_DATA 2
+
+/* Input part of generic command type of input is command. */
+#define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16)
+
+/* Generic command address sequence - address fields. */
+#define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16)
+/* Generic command address sequence - address size. */
+#define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11)
+
+/* Transfer direction field of generic command data sequence. */
+#define GCMD_DIR BIT_ULL(11)
+/* Read transfer direction of generic command data sequence. */
+#define GCMD_DIR_READ 0
+/* Write transfer direction of generic command data sequence. */
+#define GCMD_DIR_WRITE 1
+
+/* ECC enabled flag of generic command data sequence - ECC enabled. */
+#define GCMD_ECC_EN BIT_ULL(12)
+/* Generic command data sequence - sector size. */
+#define GCMD_SECT_SIZE GENMASK_ULL(31, 16)
+/* Generic command data sequence - sector count. */
+#define GCMD_SECT_CNT GENMASK_ULL(39, 32)
+/* Generic command data sequence - last sector size. */
+#define GCMD_LAST_SIZE GENMASK_ULL(55, 40)
+
+/* CDMA descriptor fields. */
+/* Erase command type of CDMA descriptor. */
+#define CDMA_CT_ERASE 0x1000
+/* Program page command type of CDMA descriptor. */
+#define CDMA_CT_WR 0x2100
+/* Read page command type of CDMA descriptor. */
+#define CDMA_CT_RD 0x2200
+
+/* Flash pointer memory shift. */
+#define CDMA_CFPTR_MEM_SHIFT 24
+/* Flash pointer memory mask. */
+#define CDMA_CFPTR_MEM GENMASK(26, 24)
+
+/*
+ * Command DMA descriptor flags. If set causes issue interrupt after
+ * the completion of descriptor processing.
+ */
+#define CDMA_CF_INT BIT(8)
+/*
+ * Command DMA descriptor flags - the next descriptor
+ * address field is valid and descriptor processing should continue.
+ */
+#define CDMA_CF_CONT BIT(9)
+/* DMA master flag of command DMA descriptor. */
+#define CDMA_CF_DMA_MASTER BIT(10)
+
+/* Operation complete status of command descriptor. */
+#define CDMA_CS_COMP BIT(15)
+/* Operation complete status of command descriptor. */
+/* Command descriptor status - operation fail. */
+#define CDMA_CS_FAIL BIT(14)
+/* Command descriptor status - page erased. */
+#define CDMA_CS_ERP BIT(11)
+/* Command descriptor status - timeout occurred. */
+#define CDMA_CS_TOUT BIT(10)
+/*
+ * Maximum amount of correction applied to one ECC sector.
+ * It is part of command descriptor status.
+ */
+#define CDMA_CS_MAXERR GENMASK(9, 2)
+/* Command descriptor status - uncorrectable ECC error. */
+#define CDMA_CS_UNCE BIT(1)
+/* Command descriptor status - descriptor error. */
+#define CDMA_CS_ERR BIT(0)
+
+/* Status of operation - OK. */
+#define STAT_OK 0
+/* Status of operation - FAIL. */
+#define STAT_FAIL 2
+/* Status of operation - uncorrectable ECC error. */
+#define STAT_ECC_UNCORR 3
+/* Status of operation - page erased. */
+#define STAT_ERASED 5
+/* Status of operation - correctable ECC error. */
+#define STAT_ECC_CORR 6
+/* Status of operation - unsuspected state. */
+#define STAT_UNKNOWN 7
+/* Status of operation - operation is not completed yet. */
+#define STAT_BUSY 0xFF
+
+#define BCH_MAX_NUM_CORR_CAPS 8
+#define BCH_MAX_NUM_SECTOR_SIZES 2
+
+#define ONE_CYCLE 1
+#define TIMEOUT_US 1000000
+
+struct cadence_nand_timings {
+ u32 async_toggle_timings;
+ u32 timings0;
+ u32 timings1;
+ u32 timings2;
+ u32 dll_phy_ctrl;
+ u32 phy_ctrl;
+ u32 phy_dqs_timing;
+ u32 phy_gate_lpbk_ctrl;
+};
+
+/* Command DMA descriptor. */
+struct cadence_nand_cdma_desc {
+ /* Next descriptor address. */
+ u64 next_pointer;
+
+ /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
+ u32 flash_pointer;
+ /*field appears in HPNFC version 13*/
+ u16 bank;
+ u16 rsvd0;
+
+ /* Operation the controller needs to perform. */
+ u16 command_type;
+ u16 rsvd1;
+ /* Flags for operation of this command. */
+ u16 command_flags;
+ u16 rsvd2;
+
+ /* System/host memory address required for data DMA commands. */
+ u64 memory_pointer;
+
+ /* Status of operation. */
+ u32 status;
+ u32 rsvd3;
+
+ /* Address pointer to sync buffer location. */
+ u64 sync_flag_pointer;
+
+ /* Controls the buffer sync mechanism. */
+ u32 sync_arguments;
+ u32 rsvd4;
+
+ /* Control data pointer. */
+ u64 ctrl_data_ptr;
+};
+
+/* Interrupt status. */
+struct cadence_nand_irq_status {
+ /* Thread operation complete status. */
+ u32 trd_status;
+ /* Thread operation error. */
+ u32 trd_error;
+ /* Controller status. */
+ u32 status;
+};
+
+/* Cadence NAND flash controller capabilities get from driver data. */
+struct cadence_nand_dt_devdata {
+ /* Skew value of the output signals of the NAND Flash interface. */
+ u32 if_skew;
+ /* It informs if slave DMA interface is connected to DMA engine. */
+ unsigned int has_dma:1;
+};
+
+/* Cadence NAND flash controller capabilities read from registers. */
+struct cdns_nand_caps {
+ /* Maximum number of banks supported by hardware. */
+ u8 max_banks;
+ /* Slave and Master DMA data width in bytes (4 or 8). */
+ u8 data_dma_width;
+ /* Control Data feature supported. */
+ bool data_control_supp;
+ /* Is PHY type DLL. */
+ bool is_phy_type_dll;
+};
+
+struct cadence_nand_info {
+ struct nand_hw_control controller;
+ struct udevice *dev;
+ struct reset_ctl softphy_reset;
+ struct reset_ctl nand_reset;
+ struct cadence_nand_cdma_desc *cdma_desc;
+ /* IP capability. */
+ const struct cadence_nand_dt_devdata *caps1;
+ struct cdns_nand_caps caps2;
+ u8 ctrl_rev;
+ dma_addr_t dma_cdma_desc;
+ /* command interface buffers */
+ u8 *buf;
+ u32 buf_size;
+ u8 *stat;
+ u8 cmd;
+ u32 buf_index;
+
+ u8 curr_corr_str_idx;
+
+ /* Register interface. */
+ void __iomem *reg;
+
+ struct {
+ void __iomem *virt;
+ dma_addr_t dma;
+ } io;
+
+ int irq;
+ /* Interrupts that have happened. */
+ struct cadence_nand_irq_status irq_status;
+ /* Interrupts we are waiting for. */
+ struct cadence_nand_irq_status irq_mask;
+
+ int ecc_strengths[BCH_MAX_NUM_CORR_CAPS];
+ struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES];
+ struct nand_ecc_caps ecc_caps;
+
+ int curr_trans_type;
+
+ struct clk clk;
+ u32 nf_clk_rate;
+ /*
+ * Estimated Board delay. The value includes the total
+ * round trip delay for the signals and is used for deciding on values
+ * associated with data read capture.
+ */
+ u32 board_delay;
+
+ struct nand_chip *selected_chip;
+
+ unsigned long assigned_cs;
+ struct list_head chips;
+ u8 bch_metadata_size;
+};
+
+struct cdns_nand_chip {
+ struct cadence_nand_timings timings;
+ struct nand_chip chip;
+ u8 nsels;
+ struct list_head node;
+
+ /*
+ * part of oob area of NAND flash memory page.
+ * This part is available for user to read or write.
+ */
+ u32 avail_oob_size;
+
+ /* Sector size. There are few sectors per mtd->writesize */
+ u32 sector_size;
+ u32 sector_count;
+
+ /* Offset of BBM. */
+ u8 bbm_offs;
+ /* Number of bytes reserved for BBM. */
+ u8 bbm_len;
+ /* ECC strength index. */
+ u8 corr_str_idx;
+
+ u8 cs[];
+};
+
+struct ecc_info {
+ int (*calc_ecc_bytes)(int step_size, int strength);
+ int max_step_size;
+};
+
+#endif /*_CADENCE_NAND_H_*/
diff --git a/include/clk.h b/include/clk.h
index 045e923..a6ef4e0 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -351,6 +351,15 @@
}
/**
+ * clk_resolve_parent_clk - Determine name of clock udevice based on clock-names
+ * @dev: The client udevice.
+ * @name: The name of the clock to look up.
+ *
+ * Return name of the clock udevice which represents clock with clock-names name.
+ */
+const char *clk_resolve_parent_clk(struct udevice *dev, const char *name);
+
+/**
* enum clk_defaults_stage - What stage clk_set_defaults() is called at
* @CLK_DEFAULTS_PRE: Called before probe. Setting of defaults for clocks owned
* by this clock driver will be defered until after probing.
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index aa31f3b..266b77f 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -37,20 +37,4 @@
/* CPSW Ethernet */
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CFG_SYS_SPI_ARGS_OFFS 0x140000
-#define CFG_SYS_SPI_ARGS_SIZE 0x80000
-
-/* SPI SPL */
-
#endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/beagley_ai.h b/include/configs/beagley_ai.h
new file mode 100644
index 0000000..a7072a0
--- /dev/null
+++ b/include/configs/beagley_ai.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for BeagleY-AI
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_BEAGLEY_AI_H
+#define __CONFIG_BEAGLEY_AI_H
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_BEAGLEY_AI_H */
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 98b1e5a..19d71d6 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -29,11 +29,6 @@
* 0x1F00000 - 0x2000000 : SPI.factory (1MiB)
*/
-/* Below values are "dummy" - only to avoid build break */
-#define CFG_SYS_SPI_KERNEL_OFFS 0x150000
-#define CFG_SYS_SPI_ARGS_OFFS 0x140000
-#define CFG_SYS_SPI_ARGS_SIZE 0x10000
-
#define CFG_MXC_UART_BASE UART5_BASE
/* MMC Configs */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 96dcd73..3c960ca 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -47,22 +47,6 @@
#include <configs/ti_omap5_common.h>
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CFG_SYS_SPI_ARGS_OFFS 0x140000
-#define CFG_SYS_SPI_ARGS_SIZE 0x80000
-
-/* SPI SPL */
-
/* NAND support */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h
index cd6af93..aec1208 100644
--- a/include/configs/imxrt1020-evk.h
+++ b/include/configs/imxrt1020-evk.h
@@ -9,8 +9,6 @@
#include <asm/arch/imx-regs.h>
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
-
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index c520c2f..5b8d6a7 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -9,8 +9,6 @@
#include <asm/arch/imx-regs.h>
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
-
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h
index 1ccaa15..f821212 100644
--- a/include/configs/imxrt1170-evk.h
+++ b/include/configs/imxrt1170-evk.h
@@ -10,8 +10,6 @@
#include <asm/arch/imx-regs.h>
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
-
/*
* Configuration of the external SDRAM memory
*/
diff --git a/include/configs/ouya.h b/include/configs/ouya.h
new file mode 100644
index 0000000..cc86c10
--- /dev/null
+++ b/include/configs/ouya.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2025
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "Ouya Game Console"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h
index 661ba8f..4f612d2 100644
--- a/include/configs/phycore_am62ax.h
+++ b/include/configs/phycore_am62ax.h
@@ -12,4 +12,8 @@
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM62AX_TIBOOT3"
+#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM62AX_SPL"
+#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM62AX_UBOOT"
+
#endif /* __PHYCORE_AM62AX_H */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 2996b37..cd8d043 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -11,7 +11,6 @@
#include <linux/sizes.h>
-#define CFG_SYS_SDRAM_BASE 0x80000000
#define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMEROFF 0xbff8
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 27e0912..e0064ed 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -11,6 +11,5 @@
#include <linux/sizes.h>
-#define CFG_SYS_SDRAM_BASE 0x80000000
#endif /* __SIFIVE_UNMATCHED_H */
diff --git a/include/configs/xea.h b/include/configs/xea.h
index 00d6274..21454d1 100644
--- a/include/configs/xea.h
+++ b/include/configs/xea.h
@@ -12,14 +12,6 @@
#ifndef __CONFIGS_XEA_H__
#define __CONFIGS_XEA_H__
-#include <linux/sizes.h>
-
-/* SPL */
-
-#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M
-#define CFG_SYS_SPI_ARGS_OFFS SZ_512K
-#define CFG_SYS_SPI_ARGS_SIZE SZ_32K
-
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 13941ba..ec78f2e 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -194,12 +194,6 @@
"dfu_bufsiz=0x1000\0"
#endif
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CFG_SYS_SPI_KERNEL_OFFS 0x80000
-# define CFG_SYS_SPI_ARGS_OFFS 0xa0000
-# define CFG_SYS_SPI_ARGS_SIZE 0xa0000
-#endif
-
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
#endif
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 37c77aa..93ae589 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -191,14 +191,6 @@
/* Not using MMC raw mode - just for compilation purpose */
-/* qspi mode is working fine */
-#ifdef CONFIG_ZYNQ_QSPI
-#define CFG_SYS_SPI_ARGS_OFFS 0x200000
-#define CFG_SYS_SPI_ARGS_SIZE 0x80000
-#define CFG_SYS_SPI_KERNEL_OFFS (CFG_SYS_SPI_ARGS_OFFS + \
- CFG_SYS_SPI_ARGS_SIZE)
-#endif
-
/* SP location before relocation, must use scratch RAM */
/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
diff --git a/include/dbsc5.h b/include/dbsc5.h
new file mode 100644
index 0000000..cec937d
--- /dev/null
+++ b/include/dbsc5.h
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024-2025 Renesas Electronics Corp.
+ */
+
+#ifndef __INCLUDE_DBSC5_H__
+#define __INCLUDE_DBSC5_H__
+
+/* The number of channels V4H has */
+#define DRAM_CH_CNT 4
+/* The number of slices V4H has */
+#define SLICE_CNT 2
+/* The number of chip select V4H has */
+#define CS_CNT 2
+
+struct renesas_dbsc5_board_config {
+ /* Channels in use */
+ u8 bdcfg_phyvalid;
+ /* Read vref (SoC) training range */
+ u32 bdcfg_vref_r;
+ /* Write vref (MR14, MR15) training range */
+ u16 bdcfg_vref_w;
+ /* CA vref (MR12) training range */
+ u16 bdcfg_vref_ca;
+ /* RFM required check */
+ bool bdcfg_rfm_chk;
+
+ /* Board parameter about channels */
+ struct {
+ /*
+ * 0x00: 4Gb dual channel die / 2Gb single channel die
+ * 0x01: 6Gb dual channel die / 3Gb single channel die
+ * 0x02: 8Gb dual channel die / 4Gb single channel die
+ * 0x03: 12Gb dual channel die / 6Gb single channel die
+ * 0x04: 16Gb dual channel die / 8Gb single channel die
+ * 0x05: 24Gb dual channel die / 12Gb single channel die
+ * 0x06: 32Gb dual channel die / 16Gb single channel die
+ * 0x07: 24Gb single channel die
+ * 0x08: 32Gb single channel die
+ * 0xFF: NO_MEMORY
+ */
+ u8 bdcfg_ddr_density[CS_CNT];
+ /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
+ u32 bdcfg_ca_swap;
+ /* SoC dqsX([1][0]) -> MEM dqsY: */
+ u8 bdcfg_dqs_swap;
+ /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
+ u32 bdcfg_dq_swap[SLICE_CNT];
+ /* SoC dm -> MEM dqY/dm: (8 means DM) */
+ u8 bdcfg_dm_swap[SLICE_CNT];
+ /* SoC ckeX([1][0]) -> MEM csY */
+ u8 bdcfg_cs_swap;
+ } ch[4];
+};
+
+#endif /* __INCLUDE_DBSC5_H__ */
diff --git a/include/dm/device.h b/include/dm/device.h
index add67f9..678cd83 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -81,7 +81,10 @@
*/
#define DM_FLAG_VITAL (1 << 14)
-/* Device must be probed after it was bound */
+/* Device must be probed after it was bound. This flag is per-device and does
+ * nothing if set on a U_BOOT_DRIVER() definition. Apply it with
+ * dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND) in the devices bind function.
+ */
#define DM_FLAG_PROBE_AFTER_BIND (1 << 15)
/*
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
index cc59eeb..52657aa 100644
--- a/include/dm/platform_data/serial_mxc.h
+++ b/include/dm/platform_data/serial_mxc.h
@@ -9,6 +9,9 @@
/* Information about a serial port */
struct mxc_serial_plat {
struct mxc_uart *reg; /* address of registers in physical memory */
+#if CONFIG_IS_ENABLED(CLK_CCF)
+ struct clk_bulk clks;
+#endif
bool use_dte;
};
diff --git a/include/dt-bindings/reset/spacemit-k1-reset.h b/include/dt-bindings/reset/spacemit-k1-reset.h
new file mode 100644
index 0000000..74db58b
--- /dev/null
+++ b/include/dt-bindings/reset/spacemit-k1-reset.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__
+#define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__
+/* APBC */
+#define RESET_UART1 1
+#define RESET_UART2 2
+#define RESET_GPIO 3
+#define RESET_PWM0 4
+#define RESET_PWM1 5
+#define RESET_PWM2 6
+#define RESET_PWM3 7
+#define RESET_PWM4 8
+#define RESET_PWM5 9
+#define RESET_PWM6 10
+#define RESET_PWM7 11
+#define RESET_PWM8 12
+#define RESET_PWM9 13
+#define RESET_PWM10 14
+#define RESET_PWM11 15
+#define RESET_PWM12 16
+#define RESET_PWM13 17
+#define RESET_PWM14 18
+#define RESET_PWM15 19
+#define RESET_PWM16 20
+#define RESET_PWM17 21
+#define RESET_PWM18 22
+#define RESET_PWM19 23
+#define RESET_SSP3 24
+#define RESET_UART3 25
+#define RESET_RTC 26
+#define RESET_TWSI0 27
+#define RESET_TIMERS1 28
+#define RESET_AIB 29
+#define RESET_TIMERS2 30
+#define RESET_ONEWIRE 31
+#define RESET_SSPA0 32
+#define RESET_SSPA1 33
+#define RESET_DRO 34
+#define RESET_IR 35
+#define RESET_TWSI1 36
+#define RESET_TSEN 37
+#define RESET_TWSI2 38
+#define RESET_TWSI4 39
+#define RESET_TWSI5 40
+#define RESET_TWSI6 41
+#define RESET_TWSI7 42
+#define RESET_TWSI8 43
+#define RESET_IPC_AP2AUD 44
+#define RESET_UART4 45
+#define RESET_UART5 46
+#define RESET_UART6 47
+#define RESET_UART7 48
+#define RESET_UART8 49
+#define RESET_UART9 50
+#define RESET_CAN0 51
+
+/* MPMU */
+#define RESET_WDT 52
+
+/* APMU */
+#define RESET_JPG 53
+#define RESET_CSI 54
+#define RESET_CCIC2_PHY 55
+#define RESET_CCIC3_PHY 56
+#define RESET_ISP 57
+#define RESET_ISP_AHB 58
+#define RESET_ISP_CI 59
+#define RESET_ISP_CPP 60
+#define RESET_LCD 61
+#define RESET_DSI_ESC 62
+#define RESET_V2D 63
+#define RESET_MIPI 64
+#define RESET_LCD_SPI 65
+#define RESET_LCD_SPI_BUS 66
+#define RESET_LCD_SPI_HBUS 67
+#define RESET_LCD_MCLK 68
+#define RESET_CCIC_4X 69
+#define RESET_CCIC1_PHY 70
+#define RESET_SDH_AXI 71
+#define RESET_SDH0 72
+#define RESET_SDH1 73
+#define RESET_USB_AXI 74
+#define RESET_USBP1_AXI 75
+#define RESET_USB3_0 76
+#define RESET_QSPI 77
+#define RESET_QSPI_BUS 78
+#define RESET_DMA 79
+#define RESET_AES 80
+#define RESET_VPU 81
+#define RESET_GPU 82
+#define RESET_SDH2 83
+#define RESET_MC 84
+#define RESET_EM_AXI 85
+#define RESET_EM 86
+#define RESET_AUDIO_SYS 87
+#define RESET_HDMI 88
+#define RESET_PCIE0 89
+#define RESET_PCIE1 90
+#define RESET_PCIE2 91
+#define RESET_EMAC0 92
+#define RESET_EMAC1 93
+
+/* APBC2 */
+#define RESET_SEC_UART1 94
+#define RESET_SEC_SSP2 95
+#define RESET_SEC_TWSI3 96
+#define RESET_SEC_RTC 97
+#define RESET_SEC_TIMERS0 98
+#define RESET_SEC_KPC 99
+#define RESET_SEC_GPIO 100
+#define RESET_NUMBER 101
+
+#endif
diff --git a/include/efi.h b/include/efi.h
index d005cb6..f9bbb17 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -705,4 +705,17 @@
*/
int efi_get_pxe_arch(void);
+/**
+ * fdt_efi_pmem_setup() - Pmem setup in DT and EFI memory map
+ * @fdt: Devicetree to add the pmem nodes to
+ *
+ * Iterate through all the blkmap devices, look for BLKMAP_MEM devices,
+ * and add pmem nodes corresponding to the blkmap slice to the
+ * devicetree along with removing the corresponding region from the
+ * EFI memory map.
+ *
+ * Returns: 0 on success, negative error on failure
+ */
+int fdt_efi_pmem_setup(void *fdt);
+
#endif /* _LINUX_EFI_H */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index e9c1081..5f76978 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -878,6 +878,21 @@
/* Adds a range into the EFI memory map */
efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type);
+/**
+ * efi_update_memory_map() - update the memory map by adding/removing pages
+ *
+ * @start: start address, must be a multiple of
+ * EFI_PAGE_SIZE
+ * @pages: number of pages to add
+ * @memory_type: type of memory added
+ * @overlap_conventional: region may only overlap free(conventional)
+ * memory
+ * @remove: remove memory map
+ * Return: status code
+ */
+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type,
+ bool overlap_conventional, bool remove);
+
/* Called by board init to initialize the EFI drivers */
efi_status_t efi_driver_init(void);
/* Called when a block device is added */
diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env
index f4e3819..6a457d1 100644
--- a/include/env/nvidia/prod_upd.env
+++ b/include/env/nvidia/prod_upd.env
@@ -3,6 +3,7 @@
bootloader_file=u-boot-dtb-tegra.bin
spi_size=0x400000
boot_dev=0
+boot_interface=mmc
flash_uboot=echo Preparing RAM;
mw ${kernel_addr_r} 0 ${boot_block_size_r};
@@ -11,9 +12,9 @@
mmc dev 0 1;
mmc read ${kernel_addr_r} 0 ${boot_block_size};
echo Reading bootloader;
- if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
+ if load ${boot_interface} ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
then echo Calculating bootloader size;
- size mmc ${boot_dev}:1 ${bootloader_file};
+ size ${boot_interface} ${boot_dev}:1 ${bootloader_file};
ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};
echo Writing bootloader to eMMC;
mmc dev 0 1;
diff --git a/include/env/phytec/k3_dfu.env b/include/env/phytec/k3_dfu.env
new file mode 100644
index 0000000..0cba87d
--- /dev/null
+++ b/include/env/phytec/k3_dfu.env
@@ -0,0 +1,3 @@
+dfu_alt_info_ram=
+ tispl.bin ram 0x80080000 0x200000;
+ u-boot.img ram 0x81000000 0x400000
diff --git a/include/fdt_support.h b/include/fdt_support.h
index f0ad2e6..049190c 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -471,6 +471,20 @@
*/
int fdt_get_cells_len(const void *blob, char *nr_cells_name);
+/**
+ * fdt_fixup_pmem_region() - add a pmem node on the device tree
+ *
+ * This functions adds/updates a pmem node to the device tree.
+ * Usually used with EFI installers to preserve installer
+ * images
+ *
+ * @fdt: device tree provided by caller
+ * @addr: start address of the pmem node
+ * @size: size of the memory of the pmem node
+ * Return: 0 on success or < 0 on failure
+ */
+int fdt_fixup_pmem_region(void *fdt, u64 pmem_start, u64 pmem_size);
+
#endif /* !USE_HOSTCC */
#ifdef USE_HOSTCC
diff --git a/include/image.h b/include/image.h
index c1db838..2455baa 100644
--- a/include/image.h
+++ b/include/image.h
@@ -244,7 +244,7 @@
* New IDs *MUST* be appended at the end of the list and *NEVER*
* inserted for backward compatibility.
*/
-enum {
+enum image_comp_t {
IH_COMP_NONE = 0, /* No Compression Used */
IH_COMP_GZIP, /* gzip Compression Used */
IH_COMP_BZIP2, /* bzip2 Compression Used */
@@ -598,10 +598,13 @@
ulong *setup_len);
/* Image format types, returned by _get_format() routine */
-#define IMAGE_FORMAT_INVALID 0x00
-#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
-#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
-#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
+enum image_fmt_t {
+ IMAGE_FORMAT_INVALID,
+ IMAGE_FORMAT_LEGACY, /* legacy image_header based format */
+ IMAGE_FORMAT_FIT, /* new, libfdt based format */
+ IMAGE_FORMAT_ANDROID, /* Android boot image */
+ IMAGE_FORMAT_BOOTI, /* Arm64/RISC-V boot image */
+};
/**
* genimg_get_kernel_addr_fit() - Parse FIT specifier
@@ -630,10 +633,43 @@
const char **fit_uname_kernel);
ulong genimg_get_kernel_addr(char * const img_addr);
-int genimg_get_format(const void *img_addr);
+
+/**
+ * genimg_get_format - get image format type
+ * @img_addr: image start address
+ * Return: image format type or IMAGE_FORMAT_INVALID if no image is present
+ *
+ * genimg_get_format() checks whether provided address points to a valid
+ * legacy or FIT image.
+ *
+ * New uImage format and FDT blob are based on a libfdt. FDT blob
+ * may be passed directly or embedded in a FIT image. In both situations
+ * genimg_get_format() must be able to dectect libfdt header.
+ */
+enum image_fmt_t genimg_get_format(const void *img_addr);
+
+/**
+ * genimg_get_format_comp() - Like genimg_get_format() but adds compressed booti
+ *
+ * If a compressed file is detected (with image_decomp_type()) and
+ * CONFIG_CMD_BOOTI is enabled, then this returns IMAGE_FORMAT_BOOTI
+ *
+ * @img_addr: image start address
+ * Return: image format type or IMAGE_FORMAT_INVALID if no image is present
+ */
+enum image_fmt_t genimg_get_format_comp(const void *img_addr);
+
int genimg_has_config(struct bootm_headers *images);
/**
+ * booti_is_valid() - Check if an image appears to be an Arm64 image
+ *
+ * @img: Pointer to image
+ * Return: true if the image has the Arm64 magic
+ */
+bool booti_is_valid(const void *img);
+
+/**
* boot_get_fpga() - Locate the FPGA image
*
* @images: Information about images being loaded
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 59f9c24..5ea2171 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -105,7 +105,7 @@
#define CLK_GATE_HIWORD_MASK BIT(1)
extern const struct clk_ops clk_gate_ops;
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
@@ -223,7 +223,7 @@
#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
-struct clk *clk_register_composite(struct device *dev, const char *name,
+struct clk *clk_register_composite(struct udevice *dev, const char *name,
const char * const *parent_names, int num_parents,
struct clk *mux_clk, const struct clk_ops *mux_ops,
struct clk *rate_clk, const struct clk_ops *rate_ops,
@@ -233,16 +233,16 @@
int clk_register(struct clk *clk, const char *drv_name, const char *name,
const char *parent_name);
-struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div);
-struct clk *clk_register_divider(struct device *dev, const char *name,
+struct clk *clk_register_divider(struct udevice *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags);
-struct clk *clk_register_mux(struct device *dev, const char *name,
+struct clk *clk_register_mux(struct udevice *dev, const char *name,
const char * const *parent_names, u8 num_parents,
unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 2d85b39..3e80b13 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -132,6 +132,17 @@
#define NAND_DATA_IFACE_CHECK_ONLY -1
/*
+ * There are different places where the manufacturer stores the factory bad
+ * block markers.
+ *
+ * Position within the block: Each of these pages needs to be checked for a
+ * bad block marking pattern.
+ */
+#define NAND_BBM_FIRSTPAGE BIT(24)
+#define NAND_BBM_SECONDPAGE BIT(25)
+#define NAND_BBM_LASTPAGE BIT(26)
+
+/*
* Constants for ECC_MODES
*/
typedef enum {
@@ -981,6 +992,7 @@
struct nand_bbt_descr *bbt_md;
struct nand_bbt_descr *badblock_pattern;
+ int cur_cs;
void *priv;
diff --git a/include/lmb.h b/include/lmb.h
index 09297a4..0d316c6 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -135,9 +135,9 @@
* parameter. The base parameter is used to specify the base address
* of the requested region.
*
- * Return: Base address on success, 0 on error.
+ * Return: 0 on success -1 on error
*/
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
+int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
/**
* lmb_is_reserved_flags() - Test if address is in reserved region with flag
@@ -175,7 +175,7 @@
static inline int lmb_read_check(phys_addr_t addr, phys_size_t len)
{
- return lmb_alloc_addr(addr, len, LMB_NONE) == addr ? 0 : -1;
+ return lmb_alloc_addr(addr, len, LMB_NONE);
}
/**
diff --git a/include/net-common.h b/include/net-common.h
index 1d507b1..6a39091 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -475,6 +475,36 @@
enum proto_t;
int net_loop(enum proto_t protocol);
+/* internal function: do not use! */
+int netboot_run_(enum proto_t proto, ulong addr, const char *fname, ulong size,
+ bool fname_explicit, bool ipv6);
+
+/**
+ * netboot_run() - Run a network operation
+ *
+ * The following proto values are NOT supported:
+ * PING, since net_ping_ip cannot be set
+ * NETCONS, since its parameters cannot bet set
+ * RS, since first_call cannot be set, along with perhaps other things
+ * UDP, since udp_ops cannot be set
+ * DNS, since net_dns_resolve and net_dns_env_var cannot be set
+ * WGET, since DNS must be done first and that is not supported
+ * DHCP6, since the required parameters cannot be passed in
+ *
+ * To support one of these, either add the required arguments or perhaps a
+ * separate function and a struct to hold the information.
+ *
+ * @proto: Operation to run: TFTPGET, FASTBOOT_UDP, FASTBOOT_TCP, BOOTP,
+ * TFTPPUT, RARP, NFS, DHCP
+ * @addr: Load/save address
+ * @fname: Filename
+ * @size: Save size (not used for TFTPGET)
+ * @ipv6: true to use IPv6, false to use IPv4
+ * Return 0 on success, else -ve error code
+ */
+int netboot_run(enum proto_t proto, ulong addr, const char *fname, ulong size,
+ bool ipv6);
+
/**
* dhcp_run() - Run DHCP on the current ethernet device
*
diff --git a/include/phy.h b/include/phy.h
index 3678503..36354aa 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -334,6 +334,30 @@
int gen10g_discover_mmds(struct phy_device *phydev);
/**
+ * phy_set_bits - Convenience function for setting bits in a PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @val: bits to set
+ */
+static inline int phy_set_bits(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+{
+ return phy_modify(phydev, devad, regnum, 0, val);
+}
+
+/**
+ * phy_clear_bits - Convenience function for clearing bits in a PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to write to
+ * @regnum: register number to write
+ * @val: bits to clear
+ */
+static inline int phy_clear_bits(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+{
+ return phy_modify(phydev, devad, regnum, val, 0);
+}
+
+/**
* U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver
* @__name: name of the driver
*/
diff --git a/include/renesas/rzg2l-usbphy.h b/include/renesas/rzg2l-usbphy.h
new file mode 100644
index 0000000..1a46b58
--- /dev/null
+++ b/include/renesas/rzg2l-usbphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/G2L USB PHY common definitions
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#ifndef RENESAS_RZG2L_USBPHY_H
+#define RENESAS_RZG2L_USBPHY_H
+
+#include <fdtdec.h>
+
+struct rzg2l_usbphy_ctrl_priv {
+ fdt_addr_t regs;
+};
+
+#endif /* RENESAS_RZG2L_USBPHY_H */
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index c6124c5..f9534ef 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -18,6 +18,8 @@
#include <efi_loader.h>
#include <efi_variable.h>
#include <asm/unaligned.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
static const struct efi_boot_services *bs;
static const struct efi_runtime_services *rs;
@@ -348,6 +350,7 @@
struct efi_device_path **dp,
struct udevice **blk)
{
+ u64 pages;
efi_status_t ret;
struct udevice *ramdisk_blk;
@@ -362,13 +365,18 @@
}
/*
- * TODO: expose the ramdisk to OS.
- * Need to pass the ramdisk information by the architecture-specific
- * methods such as 'pmem' device-tree node.
+ * Linux supports 'pmem' which allows OS installers to find, reclaim
+ * the mounted images and continue the installation since the contents
+ * of the pmem region are treated as local media.
+ *
+ * The memory regions used for it needs to be carved out of the EFI
+ * memory map.
*/
- ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE);
+ pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+ ret = efi_update_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY,
+ false, true);
if (ret != EFI_SUCCESS) {
- log_err("Memory reservation failed\n");
+ log_err("Failed to reserve memory\n");
goto err;
}
@@ -490,6 +498,13 @@
ret = EFI_INVALID_PARAMETER;
goto err;
}
+ /*
+ * Depending on the kernel configuration, pmem memory areas must be
+ * page aligned or 2MiB aligned. PowerPC is an exception here and
+ * requires 16MiB alignment, but since we don't have EFI support for
+ * it, limit the alignment to 2MiB.
+ */
+ image_size = ALIGN(image_size, SZ_2M);
/*
* If the file extension is ".iso" or ".img", mount it and try to load
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 04b2efc..8c32059 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -5,6 +5,7 @@
#define LOG_CATEGORY LOGC_EFI
+#include <blkmap.h>
#include <bootm.h>
#include <env.h>
#include <image.h>
@@ -454,22 +455,29 @@
*/
static efi_status_t copy_fdt(void **fdtp)
{
- unsigned long fdt_ram_start = -1L, fdt_pages;
efi_status_t ret = 0;
void *fdt, *new_fdt;
- u64 new_fdt_addr;
- uint fdt_size;
- int i;
+ static u64 new_fdt_addr;
+ static efi_uintn_t fdt_pages;
+ ulong fdt_size;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- u64 ram_start = gd->bd->bi_dram[i].start;
- u64 ram_size = gd->bd->bi_dram[i].size;
+ /*
+ * Remove the configuration table that might already be
+ * installed, ignoring EFI_NOT_FOUND if no device-tree
+ * is installed
+ */
+ efi_install_configuration_table(&efi_guid_fdt, NULL);
- if (!ram_size)
- continue;
+ if (new_fdt_addr) {
+ log_debug("%s: Found allocated memory at %#llx, with %#zx pages\n",
+ __func__, new_fdt_addr, fdt_pages);
- if (ram_start < fdt_ram_start)
- fdt_ram_start = ram_start;
+ ret = efi_free_pages(new_fdt_addr, fdt_pages);
+ if (ret != EFI_SUCCESS)
+ log_err("Unable to free up existing FDT memory region\n");
+
+ new_fdt_addr = 0;
+ fdt_pages = 0;
}
/*
@@ -485,15 +493,18 @@
&new_fdt_addr);
if (ret != EFI_SUCCESS) {
log_err("Failed to reserve space for FDT\n");
- goto done;
+ return ret;
}
+ log_debug("%s: Allocated memory at %#llx, with %#zx pages\n",
+ __func__, new_fdt_addr, fdt_pages);
+
new_fdt = (void *)(uintptr_t)new_fdt_addr;
memcpy(new_fdt, fdt, fdt_totalsize(fdt));
fdt_set_totalsize(new_fdt, fdt_size);
- *fdtp = (void *)(uintptr_t)new_fdt_addr;
-done:
- return ret;
+ *fdtp = new_fdt;
+
+ return EFI_SUCCESS;
}
/**
@@ -546,9 +557,6 @@
const char *fdt_opt;
uintptr_t fdt_addr;
- /* Look for device tree that is already installed */
- if (efi_get_configuration_table(&efi_guid_fdt))
- return EFI_SUCCESS;
/* Check if there is a hardware device tree */
fdt_opt = env_get("fdt_addr");
/* Use our own device tree as fallback */
@@ -680,3 +688,44 @@
return ret;
}
+
+/**
+ * pmem_node_efi_memmap_setup() - Add pmem node and tweak EFI memmap
+ * @fdt: The devicetree to which pmem node is added
+ * @addr: start address of the pmem node
+ * @size: size of the memory of the pmem node
+ *
+ * The function adds the pmem node to the device-tree along with removing
+ * the corresponding region from the EFI memory map. Used primarily to
+ * pass the information of a RAM based ISO image to the OS.
+ *
+ * Return: 0 on success, -ve value on error
+ */
+static int pmem_node_efi_memmap_setup(void *fdt, u64 addr, u64 size)
+{
+ int ret;
+ u64 pages;
+ efi_status_t status;
+
+ ret = fdt_fixup_pmem_region(fdt, addr, size);
+ if (ret) {
+ log_err("Failed to setup pmem node for addr %#llx, size %#llx, err %d\n",
+ addr, size, ret);
+ return ret;
+ }
+
+ /* Remove the pmem region from the EFI memory map */
+ pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+ status = efi_update_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY,
+ false, true);
+ if (status != EFI_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+int fdt_efi_pmem_setup(void *fdt)
+{
+ return blkmap_get_preserved_pmem_slices(pmem_node_efi_memmap_setup,
+ fdt);
+}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 6d00b18..0abb1f6 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -258,7 +258,7 @@
}
/**
- * efi_add_memory_map_pg() - add pages to the memory map
+ * efi_update_memory_map() - update the memory map by adding/removing pages
*
* @start: start address, must be a multiple of
* EFI_PAGE_SIZE
@@ -266,12 +266,11 @@
* @memory_type: type of memory added
* @overlap_conventional: region may only overlap free(conventional)
* memory
+ * @remove: remove memory map
* Return: status code
*/
-static
-efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
- int memory_type,
- bool overlap_conventional)
+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type,
+ bool overlap_conventional, bool remove)
{
struct efi_mem_list *lmem;
struct efi_mem_list *newlist;
@@ -279,9 +278,9 @@
uint64_t carved_pages = 0;
struct efi_event *evt;
- EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
+ EFI_PRINT("%s: 0x%llx 0x%llx %d %s %s\n", __func__,
start, pages, memory_type, overlap_conventional ?
- "yes" : "no");
+ "yes" : "no", remove ? "remove" : "add");
if (memory_type >= EFI_MAX_MEMORY_TYPE)
return EFI_INVALID_PARAMETER;
@@ -364,7 +363,10 @@
}
/* Add our new map */
- list_add_tail(&newlist->link, &efi_mem);
+ if (!remove)
+ list_add_tail(&newlist->link, &efi_mem);
+ else
+ free(newlist);
/* And make sure memory is listed in descending order */
efi_mem_sort();
@@ -401,7 +403,7 @@
pages = efi_size_in_pages(size + (start & EFI_PAGE_MASK));
start &= ~EFI_PAGE_MASK;
- return efi_add_memory_map_pg(start, pages, memory_type, false);
+ return efi_update_memory_map(start, pages, memory_type, false, false);
}
/**
@@ -491,8 +493,7 @@
return EFI_NOT_FOUND;
addr = map_to_sysmem((void *)(uintptr_t)*memory);
- addr = (u64)lmb_alloc_addr(addr, len, flags);
- if (!addr)
+ if (lmb_alloc_addr(addr, len, flags))
return EFI_NOT_FOUND;
break;
default:
@@ -502,7 +503,7 @@
efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0);
/* Reserve that map in our memory maps */
- ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true);
+ ret = efi_update_memory_map(efi_addr, pages, memory_type, true, false);
if (ret != EFI_SUCCESS) {
/* Map would overlap, bail out */
lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags);
@@ -823,8 +824,8 @@
uboot_stack_size) & ~EFI_PAGE_MASK;
uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) -
uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
- efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
- false);
+ efi_update_memory_map(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
+ false, false);
#if defined(__aarch64__)
/*
* Runtime Services must be 64KiB aligned according to the
@@ -842,8 +843,8 @@
runtime_end = (uintptr_t)__efi_runtime_stop;
runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
- efi_add_memory_map_pg(runtime_start, runtime_pages,
- EFI_RUNTIME_SERVICES_CODE, false);
+ efi_update_memory_map(runtime_start, runtime_pages,
+ EFI_RUNTIME_SERVICES_CODE, false, false);
}
int efi_memory_init(void)
@@ -878,11 +879,11 @@
pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
efi_addr &= ~EFI_PAGE_MASK;
- status = efi_add_memory_map_pg(efi_addr, pages,
+ status = efi_update_memory_map(efi_addr, pages,
op == LMB_MAP_OP_RESERVE ?
EFI_BOOT_SERVICES_DATA :
EFI_CONVENTIONAL_MEMORY,
- false);
+ false, false);
if (status != EFI_SUCCESS) {
log_err("LMB Map notify failure %lu\n",
status & ~EFI_ERROR_MASK);
diff --git a/lib/efi_loader/elf_efi.ldsi b/lib/efi_loader/elf_efi.ldsi
index 190a88f..4fa5ca4 100644
--- a/lib/efi_loader/elf_efi.ldsi
+++ b/lib/efi_loader/elf_efi.ldsi
@@ -21,10 +21,10 @@
*(.gnu.linkonce.t.*)
*(.srodata)
*(.rodata*)
- . = ALIGN(16);
- *(.dynamic);
- . = ALIGN(512);
}
+ . = ALIGN(16);
+ .dynamic : { *(.dynamic) }
+ . = ALIGN(512);
.rela.dyn : { *(.rela.dyn) }
.rela.plt : { *(.rela.plt) }
.rela.got : { *(.rela.got) }
diff --git a/lib/lmb.c b/lib/lmb.c
index 93fc1be..bb6f232 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -23,6 +23,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define LMB_RGN_OVERLAP 1
+#define LMB_RGN_ADJACENT 2
+
/*
* The following low level LMB functions must not access the global LMB memory
* map since they are also used to manage IOVA memory maps in iommu drivers like
@@ -49,8 +52,22 @@
return 0;
}
-static long lmb_regions_overlap(struct alist *lmb_rgn_lst, unsigned long r1,
- unsigned long r2)
+/**
+ * lmb_regions_check() - Check if the regions overlap, or are adjacent
+ * @lmb_rgn_lst: List of LMB regions
+ * @r1: First region to check
+ * @r2: Second region to check
+ *
+ * Check if the two regions with matching flags, r1 and r2 are
+ * adjacent to each other, or if they overlap.
+ *
+ * Return:
+ * * %LMB_RGN_OVERLAP - Regions overlap
+ * * %LMB_RGN_ADJACENT - Regions adjacent to each other
+ * * 0 - Neither of the above, or flags mismatch
+ */
+static long lmb_regions_check(struct alist *lmb_rgn_lst, unsigned long r1,
+ unsigned long r2)
{
struct lmb_region *rgn = lmb_rgn_lst->data;
phys_addr_t base1 = rgn[r1].base;
@@ -58,19 +75,15 @@
phys_addr_t base2 = rgn[r2].base;
phys_size_t size2 = rgn[r2].size;
- return lmb_addrs_overlap(base1, size1, base2, size2);
-}
+ if (rgn[r1].flags != rgn[r2].flags)
+ return 0;
-static long lmb_regions_adjacent(struct alist *lmb_rgn_lst, unsigned long r1,
- unsigned long r2)
-{
- struct lmb_region *rgn = lmb_rgn_lst->data;
- phys_addr_t base1 = rgn[r1].base;
- phys_size_t size1 = rgn[r1].size;
- phys_addr_t base2 = rgn[r2].base;
- phys_size_t size2 = rgn[r2].size;
+ if (lmb_addrs_overlap(base1, size1, base2, size2))
+ return LMB_RGN_OVERLAP;
+ else if (lmb_addrs_adjacent(base1, size1, base2, size2))
+ return LMB_RGN_ADJACENT;
- return lmb_addrs_adjacent(base1, size1, base2, size2);
+ return 0;
}
static void lmb_remove_region(struct alist *lmb_rgn_lst, unsigned long r)
@@ -96,25 +109,6 @@
lmb_remove_region(lmb_rgn_lst, r2);
}
-/*Assumption : base addr of region 1 < base addr of region 2*/
-static void lmb_fix_over_lap_regions(struct alist *lmb_rgn_lst,
- unsigned long r1, unsigned long r2)
-{
- struct lmb_region *rgn = lmb_rgn_lst->data;
-
- phys_addr_t base1 = rgn[r1].base;
- phys_size_t size1 = rgn[r1].size;
- phys_addr_t base2 = rgn[r2].base;
- phys_size_t size2 = rgn[r2].size;
-
- if (base1 + size1 > base2 + size2) {
- printf("This will not be a case any time\n");
- return;
- }
- rgn[r1].size = base2 + size2 - base1;
- lmb_remove_region(lmb_rgn_lst, r2);
-}
-
static long lmb_resize_regions(struct alist *lmb_rgn_lst,
unsigned long idx_start,
phys_addr_t base, phys_size_t size)
@@ -209,14 +203,11 @@
break;
} else if (ret < 0) {
if (flags != rgnflags)
- break;
+ continue;
rgn[i].size += size;
coalesced++;
break;
} else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
- if (flags != LMB_NONE)
- return -EEXIST;
-
ret = lmb_resize_regions(lmb_rgn_lst, i, base, size);
if (ret < 0)
return -1;
@@ -229,16 +220,21 @@
}
if (lmb_rgn_lst->count && i < lmb_rgn_lst->count - 1) {
- rgn = lmb_rgn_lst->data;
- if (rgn[i].flags == rgn[i + 1].flags) {
- if (lmb_regions_adjacent(lmb_rgn_lst, i, i + 1)) {
- lmb_coalesce_regions(lmb_rgn_lst, i, i + 1);
- coalesced++;
- } else if (lmb_regions_overlap(lmb_rgn_lst, i, i + 1)) {
- /* fix overlapping area */
- lmb_fix_over_lap_regions(lmb_rgn_lst, i, i + 1);
- coalesced++;
- }
+ ret = lmb_regions_check(lmb_rgn_lst, i, i + 1);
+ if (ret == LMB_RGN_ADJACENT) {
+ lmb_coalesce_regions(lmb_rgn_lst, i, i + 1);
+ coalesced++;
+ } else if (ret == LMB_RGN_OVERLAP) {
+ /* fix overlapping areas */
+ phys_addr_t rgnbase = rgn[i].base;
+ phys_size_t rgnsize = rgn[i].size;
+
+ ret = lmb_resize_regions(lmb_rgn_lst, i,
+ rgnbase, rgnsize);
+ if (ret < 0)
+ return -1;
+
+ coalesced++;
}
}
@@ -561,6 +557,39 @@
}
}
+/**
+ * lmb_can_reserve_region() - check if the region can be reserved
+ * @base: base address of region to be reserved
+ * @size: size of region to be reserved
+ * @flags: flag of the region to be reserved
+ *
+ * Go through all the reserved regions and ensure that the requested
+ * region does not overlap with any existing regions. An overlap is
+ * allowed only when the flag of the request region and the existing
+ * region is LMB_NONE.
+ *
+ * Return: true if region can be reserved, false otherwise
+ */
+static bool lmb_can_reserve_region(phys_addr_t base, phys_size_t size,
+ u32 flags)
+{
+ uint i;
+ struct lmb_region *lmb_reserved = lmb.used_mem.data;
+
+ for (i = 0; i < lmb.used_mem.count; i++) {
+ u32 rgnflags = lmb_reserved[i].flags;
+ phys_addr_t rgnbase = lmb_reserved[i].base;
+ phys_size_t rgnsize = lmb_reserved[i].size;
+
+ if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
+ if (flags != LMB_NONE || flags != rgnflags)
+ return false;
+ }
+ }
+
+ return true;
+}
+
void lmb_add_memory(void)
{
int i;
@@ -633,6 +662,9 @@
long ret = 0;
struct alist *lmb_rgn_lst = &lmb.used_mem;
+ if (!lmb_can_reserve_region(base, size, flags))
+ return -EEXIST;
+
ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
if (ret)
return ret;
@@ -692,29 +724,25 @@
base = ALIGN_DOWN(res_base - size, align);
}
}
+
+ log_debug("%s: Failed to allocate 0x%lx bytes below 0x%lx\n",
+ __func__, (ulong)size, (ulong)max_addr);
+
return 0;
}
phys_addr_t lmb_alloc(phys_size_t size, ulong align)
{
- return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, LMB_NONE);
+ return _lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, LMB_NONE);
}
phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
uint flags)
{
- phys_addr_t alloc;
-
- alloc = _lmb_alloc_base(size, align, max_addr, flags);
-
- if (alloc == 0)
- printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
- (ulong)size, (ulong)max_addr);
-
- return alloc;
+ return _lmb_alloc_base(size, align, max_addr, flags);
}
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
+int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
{
long rgn;
struct lmb_region *lmb_memory = lmb.available_mem.data;
@@ -731,11 +759,11 @@
base + size - 1, 1)) {
/* ok, reserve the memory */
if (!lmb_reserve(base, size, flags))
- return base;
+ return 0;
}
}
- return 0;
+ return -1;
}
/* Return number of bytes from a given address that are free */
diff --git a/net/net.c b/net/net.c
index 1828f1c..ef97377 100644
--- a/net/net.c
+++ b/net/net.c
@@ -775,6 +775,50 @@
return ret;
}
+int netboot_run_(enum proto_t proto, ulong addr, const char *fname, ulong size,
+ bool fname_explicit, bool ipv6)
+{
+ int ret;
+
+ bootstage_mark(BOOTSTAGE_ID_NET_START);
+
+ /*
+ * For now we use the global variables as that is the only way to
+ * control the network stack. At some point, perhaps, the state could be
+ * in a struct
+ */
+ if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT)
+ image_save_addr = addr;
+ else
+ image_load_addr = addr;
+
+ net_boot_file_name_explicit = fname_explicit;
+ copy_filename(net_boot_file_name, fname, sizeof(net_boot_file_name));
+ if (IS_ENABLED(CONFIG_IPV6))
+ use_ip6 = ipv6;
+ if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT) {
+ image_save_addr = addr;
+ image_save_size = size;
+ } else {
+ image_load_addr = addr;
+ }
+
+ ret = net_loop(proto);
+ if (ret < 0) {
+ bootstage_error(BOOTSTAGE_ID_NET_NETLOOP_OK);
+ return ret;
+ }
+ bootstage_mark(BOOTSTAGE_ID_NET_NETLOOP_OK);
+
+ return 0;
+}
+
+int netboot_run(enum proto_t proto, ulong addr, const char *fname, ulong size,
+ bool ipv6)
+{
+ return netboot_run_(proto, addr, fname, size, true, ipv6);
+}
+
/**********************************************************************/
static void start_again_timeout_handler(void)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 1899343..275c308 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -513,8 +513,8 @@
$(call cmd,S_efi)
quiet_cmd_efi_objcopy = OBJCOPY $@
-cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j \
- .dynamic -j .dynsym -j .rel* -j .rela* -j .reloc \
+cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data \
+ -j .dynamic -j .dynstr -j .dynsym -j .rel* -j .reloc \
$(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@
$(obj)/%.efi: $(obj)/%_efi.so
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index f9f8891..414019c 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2692,6 +2692,12 @@
ERROR("PRE_SCHEMA",
"Driver model schema uses 'bootph-...' tags now\n" . $herecurr);
}
+
+ # Do not allow CONFIG_xPL_BUILD in device trees
+ if ($realfile =~ /\.dtsi?$/ && $line =~ /^\+.*CONFIG_(X|S|T|V)PL_BUILD.*/) {
+ ERROR("CONFIG_xPL_BUILD",
+ "Do not use CONFIG_xPL_BUILD in device trees\n" . $herecurr);
+ }
}
sub exclude_global_initialisers {
diff --git a/scripts/event_dump.py b/scripts/event_dump.py
index 24dfe2b..61bb3a8 100755
--- a/scripts/event_dump.py
+++ b/scripts/event_dump.py
@@ -107,7 +107,7 @@
Args:
argv (list of str): List of program arguments, excluding arvg[0]
"""
- epilog = 'Show a list of even spies in a U-Boot EFL file'
+ epilog = 'Show a list of event spies in a U-Boot ELF file'
parser = ArgumentParser(epilog=epilog)
parser.add_argument('elf', type=str, help='ELF file to decode')
parser.add_argument('-e', '--endian', type=str, default='auto',
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index fcb5f1a..3bf558f 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -471,17 +471,17 @@
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
- /* allocate overlapping region should return the coalesced count */
+ /* allocate overlapping region */
ret = lmb_reserve(0x40011000, 0x10000, LMB_NONE);
ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000,
0, 0, 0, 0);
- /* allocate 3nd region */
+ /* allocate 2nd region */
ret = lmb_reserve(0x40030000, 0x10000, LMB_NONE);
ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40010000, 0x11000,
0x40030000, 0x10000, 0, 0);
- /* allocate 2nd region , This should coalesced all region into one */
+ /* allocate 3rd region , This should coalesce all regions into one */
ret = lmb_reserve(0x40020000, 0x10000, LMB_NONE);
ut_assert(ret >= 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x30000,
@@ -499,6 +499,41 @@
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x40000,
0, 0, 0, 0);
+ /* try to allocate overlapping region with a different flag, should fail */
+ ret = lmb_reserve(0x40008000, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(ret, -EEXIST);
+
+ /* allocate another region at 0x40050000 with a different flag */
+ ret = lmb_reserve(0x40050000, 0x10000, LMB_NOOVERWRITE);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x40000,
+ 0x40050000, 0x10000, 0, 0);
+
+ /*
+ * try to reserve a region adjacent to region 1 overlapping the 2nd region,
+ * should fail
+ */
+ ret = lmb_reserve(0x40040000, 0x20000, LMB_NONE);
+ ut_asserteq(ret, -EEXIST);
+
+ /*
+ * try to reserve a region between the two regions, but without an overlap,
+ * should succeed. this added region coalesces with the region 1
+ */
+ ret = lmb_reserve(0x40040000, 0x10000, LMB_NONE);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x50000,
+ 0x40050000, 0x10000, 0, 0);
+
+ /*
+ * try to reserve a region which overlaps with both the regions,
+ * should fail as the flags do not match
+ */
+ ret = lmb_reserve(0x40020000, 0x80000, LMB_NONE);
+ ut_asserteq(ret, -EEXIST);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x50000,
+ 0x40050000, 0x10000, 0, 0);
+
lmb_pop(&store);
return 0;
@@ -531,23 +566,94 @@
/* Try to allocate a page twice */
b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
- ut_asserteq(b, alloc_addr_a);
- b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
ut_asserteq(b, 0);
+ b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(b, -1);
b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
- ut_asserteq(b, alloc_addr_a);
+ ut_asserteq(b, 0);
b = lmb_alloc_addr(alloc_addr_a, 0x2000, LMB_NONE);
- ut_asserteq(b, alloc_addr_a);
+ ut_asserteq(b, 0);
ret = lmb_free(alloc_addr_a, 0x2000);
ut_asserteq(ret, 0);
b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
- ut_asserteq(b, alloc_addr_a);
- b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
ut_asserteq(b, 0);
+ b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
+ ut_asserteq(b, -1);
b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(b, -1);
+ ret = lmb_free(alloc_addr_a, 0x1000);
+ ut_asserteq(ret, 0);
+
+ /*
+ * Add two regions with different flags, region1 and region2 with
+ * a gap between them.
+ * Try adding another region, adjacent to region 1 and overlapping
+ * region 2. Should fail.
+ */
+ a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
+ ut_asserteq(a, 0);
+
+ b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE);
ut_asserteq(b, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+ alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+ c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE);
+ ut_asserteq(c, -1);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+ alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+ ret = lmb_free(alloc_addr_a, 0x1000);
+ ut_asserteq(ret, 0);
+ ret = lmb_free(alloc_addr_a + 0x4000, 0x1000);
+ ut_asserteq(ret, 0);
+
+ /*
+ * Add two regions with same flags(LMB_NONE), region1 and region2
+ * with a gap between them.
+ * Try adding another region, adjacent to region 1 and overlapping
+ * region 2. Should succeed. All regions should coalesce into a
+ * single region.
+ */
+ a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
+ ut_asserteq(a, 0);
+
+ b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NONE);
+ ut_asserteq(b, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+ alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+ c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE);
+ ut_asserteq(c, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_addr_a, 0x6000,
+ 0, 0, 0, 0);
+
+ ret = lmb_free(alloc_addr_a, 0x6000);
+ ut_asserteq(ret, 0);
+
+ /*
+ * Add two regions with same flags(LMB_NOOVERWRITE), region1 and
+ * region2 with a gap between them.
+ * Try adding another region, adjacent to region 1 and overlapping
+ * region 2. Should fail.
+ */
+ a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(a, 0);
+
+ b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE);
+ ut_asserteq(b, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+ alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+ c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NOOVERWRITE);
+ ut_asserteq(c, -1);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+ alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
ret = lmb_free(alloc_addr_a, 0x1000);
ut_asserteq(ret, 0);
+ ret = lmb_free(alloc_addr_a + 0x4000, 0x1000);
+ ut_asserteq(ret, 0);
/* reserve 3 blocks */
ret = lmb_reserve(alloc_addr_a, 0x10000, LMB_NONE);
@@ -561,22 +667,22 @@
/* allocate blocks */
a = lmb_alloc_addr(ram, alloc_addr_a - ram, LMB_NONE);
- ut_asserteq(a, ram);
+ ut_asserteq(a, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, ram, 0x8010000,
alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
b = lmb_alloc_addr(alloc_addr_a + 0x10000,
alloc_addr_b - alloc_addr_a - 0x10000, LMB_NONE);
- ut_asserteq(b, alloc_addr_a + 0x10000);
+ ut_asserteq(b, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x10010000,
alloc_addr_c, 0x10000, 0, 0);
c = lmb_alloc_addr(alloc_addr_b + 0x10000,
alloc_addr_c - alloc_addr_b - 0x10000, LMB_NONE);
- ut_asserteq(c, alloc_addr_b + 0x10000);
+ ut_asserteq(c, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
d = lmb_alloc_addr(alloc_addr_c + 0x10000,
ram_end - alloc_addr_c - 0x10000, LMB_NONE);
- ut_asserteq(d, alloc_addr_c + 0x10000);
+ ut_asserteq(d, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
0, 0, 0, 0);
@@ -586,57 +692,58 @@
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
0, 0, 0, 0);
- ret = lmb_free(d, ram_end - alloc_addr_c - 0x10000);
+ /* free thge allocation from d */
+ ret = lmb_free(alloc_addr_c + 0x10000, ram_end - alloc_addr_c - 0x10000);
ut_asserteq(ret, 0);
/* allocate at 3 points in free range */
d = lmb_alloc_addr(ram_end - 4, 4, LMB_NONE);
- ut_asserteq(d, ram_end - 4);
+ ut_asserteq(d, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
- d, 4, 0, 0);
- ret = lmb_free(d, 4);
+ ram_end - 4, 4, 0, 0);
+ ret = lmb_free(ram_end - 4, 4);
ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
d = lmb_alloc_addr(ram_end - 128, 4, LMB_NONE);
- ut_asserteq(d, ram_end - 128);
+ ut_asserteq(d, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
- d, 4, 0, 0);
- ret = lmb_free(d, 4);
+ ram_end - 128, 4, 0, 0);
+ ret = lmb_free(ram_end - 128, 4);
ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4, LMB_NONE);
- ut_asserteq(d, alloc_addr_c + 0x10000);
+ ut_asserteq(d, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004,
0, 0, 0, 0);
- ret = lmb_free(d, 4);
+ ret = lmb_free(alloc_addr_c + 0x10000, 4);
ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
- /* allocate at the bottom */
- ret = lmb_free(a, alloc_addr_a - ram);
+ /* allocate at the bottom a was assigned to ram at the top */
+ ret = lmb_free(ram, alloc_addr_a - ram);
ut_asserteq(ret, 0);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000,
0x10010000, 0, 0, 0, 0);
d = lmb_alloc_addr(ram, 4, LMB_NONE);
- ut_asserteq(d, ram);
- ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, d, 4,
+ ut_asserteq(d, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 4,
ram + 0x8000000, 0x10010000, 0, 0);
/* check that allocating outside memory fails */
if (ram_end != 0) {
ret = lmb_alloc_addr(ram_end, 1, LMB_NONE);
- ut_asserteq(ret, 0);
+ ut_asserteq(ret, -1);
}
if (ram != 0) {
ret = lmb_alloc_addr(ram - 1, 1, LMB_NONE);
- ut_asserteq(ret, 0);
+ ut_asserteq(ret, -1);
}
lmb_pop(&store);
@@ -760,7 +867,7 @@
/* reserve again, new flag */
ret = lmb_reserve(0x40010000, 0x10000, LMB_NONE);
- ut_asserteq(ret, -1);
+ ut_asserteq(ret, -EEXIST);
ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
diff --git a/test/py/conftest.py b/test/py/conftest.py
index 31043a6..e59897c 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -7,7 +7,7 @@
# test, at shutdown etc. These hooks perform functions such as:
# - Parsing custom command-line options.
# - Pullilng in user-specified board configuration.
-# - Creating the U-Boot console test fixture.
+# - Creating the ubman test fixture.
# - Creating the HTML log file.
# - Monitoring each test's results.
# - Implementing custom pytest markers.
@@ -25,12 +25,12 @@
from _pytest.runner import runtestprotocol
import subprocess
import sys
+from spawn import BootFail, Timeout, Unexpected, handle_exception
import time
-from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception
-# Globals: The HTML log file, and the connection to the U-Boot console.
+# Globals: The HTML log file, and the top-level fixture
log = None
-console = None
+ubman_fix = None
TEST_PY_DIR = os.path.dirname(os.path.abspath(__file__))
@@ -247,7 +247,7 @@
ubconfig.buildconfig.update(parser.items('root'))
global log
- global console
+ global ubman_fix
global ubconfig
(board_type, board_type_extra, board_identity, build_dir, build_dir_extra,
@@ -289,19 +289,26 @@
ubconfig = ArbitraryAttributeContainer()
ubconfig.brd = dict()
ubconfig.env = dict()
+ not_found = []
- modules = [
- (ubconfig.brd, 'u_boot_board_' + board_type_filename),
- (ubconfig.env, 'u_boot_boardenv_' + board_type_filename),
- (ubconfig.env, 'u_boot_boardenv_' + board_type_filename + '_' +
- board_identity_filename),
- ]
- for (dict_to_fill, module_name) in modules:
- try:
- module = __import__(module_name)
- except ImportError:
- continue
- dict_to_fill.update(module.__dict__)
+ with log.section('Loading lab modules', 'load_modules'):
+ modules = [
+ (ubconfig.brd, 'u_boot_board_' + board_type_filename),
+ (ubconfig.env, 'u_boot_boardenv_' + board_type_filename),
+ (ubconfig.env, 'u_boot_boardenv_' + board_type_filename + '_' +
+ board_identity_filename),
+ ]
+ for (dict_to_fill, module_name) in modules:
+ try:
+ module = __import__(module_name)
+ except ImportError:
+ not_found.append(module_name)
+ continue
+ dict_to_fill.update(module.__dict__)
+ log.info(f"Loaded {module}")
+
+ if not_found:
+ log.warning(f"Failed to find modules: {' '.join(not_found)}")
ubconfig.buildconfig = dict()
@@ -343,11 +350,11 @@
os.environ['U_BOOT_' + v.upper()] = getattr(ubconfig, v)
if board_type.startswith('sandbox'):
- import u_boot_console_sandbox
- console = u_boot_console_sandbox.ConsoleSandbox(log, ubconfig)
+ import console_sandbox
+ ubman_fix = console_sandbox.ConsoleSandbox(log, ubconfig)
else:
- import u_boot_console_exec_attach
- console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig)
+ import console_board
+ ubman_fix = console_board.ConsoleExecAttach(log, ubconfig)
def generate_ut_subtest(metafunc, fixture_name, sym_path):
@@ -366,7 +373,7 @@
Returns:
Nothing.
"""
- fn = console.config.build_dir + sym_path
+ fn = ubman_fix.config.build_dir + sym_path
try:
with open(fn, 'rt') as f:
lines = f.readlines()
@@ -407,8 +414,8 @@
"""
subconfigs = {
- 'brd': console.config.brd,
- 'env': console.config.env,
+ 'brd': ubman_fix.config.brd,
+ 'env': ubman_fix.config.env,
}
parts = fixture_name.split('__')
if len(parts) < 2:
@@ -470,7 +477,7 @@
The fixture value.
"""
- return console.log
+ return ubman_fix.log
@pytest.fixture(scope='session')
def u_boot_config(request):
@@ -483,11 +490,11 @@
The fixture value.
"""
- return console.config
+ return ubman_fix.config
@pytest.fixture(scope='function')
-def u_boot_console(request):
- """Generate the value of a test's u_boot_console fixture.
+def ubman(request):
+ """Generate the value of a test's ubman fixture.
Args:
request: The pytest request.
@@ -499,18 +506,18 @@
pytest.skip('Cannot get target connection')
return None
try:
- console.ensure_spawned()
+ ubman_fix.ensure_spawned()
except OSError as err:
- handle_exception(ubconfig, console, log, err, 'Lab failure', True)
+ handle_exception(ubconfig, ubman_fix, log, err, 'Lab failure', True)
except Timeout as err:
- handle_exception(ubconfig, console, log, err, 'Lab timeout', True)
+ handle_exception(ubconfig, ubman_fix, log, err, 'Lab timeout', True)
except BootFail as err:
- handle_exception(ubconfig, console, log, err, 'Boot fail', True,
- console.get_spawn_output())
+ handle_exception(ubconfig, ubman_fix, log, err, 'Boot fail', True,
+ ubman.get_spawn_output())
except Unexpected:
- handle_exception(ubconfig, console, log, err, 'Unexpected test output',
+ handle_exception(ubconfig, ubman_fix, log, err, 'Unexpected test output',
False)
- return console
+ return ubman_fix
anchors = {}
tests_not_run = []
@@ -623,8 +630,8 @@
Nothing.
"""
- if console:
- console.close()
+ if ubman_fix:
+ ubman_fix.close()
if log:
with log.section('Status Report', 'status_report'):
log.status_pass('%d passed' % len(tests_passed))
@@ -845,7 +852,7 @@
test_durations[item.name] = duration
if failure_cleanup:
- console.drain_console()
+ ubman_fix.drain_console()
test_list.append(item.name)
tests_not_run.remove(item.name)
@@ -855,7 +862,7 @@
except:
# If something went wrong with logging, it's better to let the test
# process continue, which may report other exceptions that triggered
- # the logging issue (e.g. console.log wasn't created). Hence, just
+ # the logging issue (e.g. ubman_fix.log wasn't created). Hence, just
# squash the exception. If the test setup failed due to e.g. syntax
# error somewhere else, this won't be seen. However, once that issue
# is fixed, if this exception still exists, it will then be logged as
@@ -868,6 +875,6 @@
log.end_section(item.name)
if failure_cleanup:
- console.cleanup_spawn()
+ ubman_fix.cleanup_spawn()
return True
diff --git a/test/py/u_boot_console_base.py b/test/py/console_base.py
similarity index 98%
rename from test/py/u_boot_console_base.py
rename to test/py/console_base.py
index 7eaceb3..260df77 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/console_base.py
@@ -13,8 +13,8 @@
import pytest
import re
import sys
-import u_boot_spawn
-from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception
+import spawn
+from spawn import BootFail, Timeout, Unexpected, handle_exception
# Regexes for text we expect U-Boot to send to the console.
pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))')
@@ -157,9 +157,9 @@
def get_spawn(self):
# This is not called, ssubclass must define this.
# Return a value to avoid:
- # u_boot_console_base.py:348:12: E1128: Assigning result of a function
+ # console_base.py:348:12: E1128: Assigning result of a function
# call, where the function returns None (assignment-from-none)
- return u_boot_spawn.Spawn([])
+ return spawn.Spawn([])
def eval_bad_patterns(self):
diff --git a/test/py/u_boot_console_exec_attach.py b/test/py/console_board.py
similarity index 94%
rename from test/py/u_boot_console_exec_attach.py
rename to test/py/console_board.py
index 8b253b4..bacb1e2 100644
--- a/test/py/u_boot_console_exec_attach.py
+++ b/test/py/console_board.py
@@ -8,8 +8,8 @@
"""
import sys
-from u_boot_spawn import Spawn
-from u_boot_console_base import ConsoleBase
+from spawn import Spawn
+from console_base import ConsoleBase
class ConsoleExecAttach(ConsoleBase):
"""Represents a physical connection to a U-Boot console, typically via a
@@ -53,7 +53,7 @@
None.
Returns:
- A u_boot_spawn.Spawn object that is attached to U-Boot.
+ A spawn.Spawn object that is attached to U-Boot.
"""
args = [self.config.board_type, self.config.board_identity]
diff --git a/test/py/u_boot_console_sandbox.py b/test/py/console_sandbox.py
similarity index 93%
rename from test/py/u_boot_console_sandbox.py
rename to test/py/console_sandbox.py
index 7bc44c7..da55d2f 100644
--- a/test/py/u_boot_console_sandbox.py
+++ b/test/py/console_sandbox.py
@@ -7,8 +7,8 @@
"""
import time
-from u_boot_spawn import Spawn
-from u_boot_console_base import ConsoleBase
+from spawn import Spawn
+from console_base import ConsoleBase
class ConsoleSandbox(ConsoleBase):
"""Represents a connection to a sandbox U-Boot console, executed as a sub-
@@ -39,7 +39,7 @@
None.
Returns:
- A u_boot_spawn.Spawn object that is attached to U-Boot.
+ A spawn.Spawn object that is attached to U-Boot.
"""
bcfg = self.config.buildconfig
@@ -71,7 +71,7 @@
use_dtb: True to use a device tree file, False to run without one
Returns:
- A u_boot_spawn.Spawn object that is attached to U-Boot.
+ A spawn.Spawn object that is attached to U-Boot.
"""
try:
diff --git a/test/py/u_boot_spawn.py b/test/py/spawn.py
similarity index 100%
rename from test/py/u_boot_spawn.py
rename to test/py/spawn.py
diff --git a/test/py/tests/fit_util.py b/test/py/tests/fit_util.py
index 79718d4..f322b50 100644
--- a/test/py/tests/fit_util.py
+++ b/test/py/tests/fit_util.py
@@ -5,25 +5,25 @@
import os
-import u_boot_utils as util
+import utils
-def make_fname(cons, basename):
+def make_fname(ubman, basename):
"""Make a temporary filename
Args:
- cons (ConsoleBase): u_boot_console to use
+ ubman (ConsoleBase): ubman to use
basename (str): Base name of file to create (within temporary directory)
Return:
Temporary filename
"""
- return os.path.join(cons.config.build_dir, basename)
+ return os.path.join(ubman.config.build_dir, basename)
-def make_its(cons, base_its, params, basename='test.its'):
+def make_its(ubman, base_its, params, basename='test.its'):
"""Make a sample .its file with parameters embedded
Args:
- cons (ConsoleBase): u_boot_console to use
+ ubman (ConsoleBase): ubman to use
base_its (str): Template text for the .its file, typically containing
%() references
params (dict of str): Parameters to embed in the %() strings
@@ -31,19 +31,19 @@
Returns:
str: Filename of .its file created
"""
- its = make_fname(cons, basename)
+ its = make_fname(ubman, basename)
with open(its, 'w', encoding='utf-8') as outf:
print(base_its % params, file=outf)
return its
-def make_fit(cons, mkimage, base_its, params, basename='test.fit', base_fdt=None):
+def make_fit(ubman, mkimage, base_its, params, basename='test.fit', base_fdt=None):
"""Make a sample .fit file ready for loading
This creates a .its script with the selected parameters and uses mkimage to
turn this into a .fit image.
Args:
- cons (ConsoleBase): u_boot_console to use
+ ubman (ConsoleBase): ubman to use
mkimage (str): Filename of 'mkimage' utility
base_its (str): Template text for the .its file, typically containing
%() references
@@ -52,25 +52,25 @@
Return:
Filename of .fit file created
"""
- fit = make_fname(cons, basename)
- its = make_its(cons, base_its, params)
- util.run_and_log(cons, [mkimage, '-f', its, fit])
+ fit = make_fname(ubman, basename)
+ its = make_its(ubman, base_its, params)
+ utils.run_and_log(ubman, [mkimage, '-f', its, fit])
if base_fdt:
- with open(make_fname(cons, 'u-boot.dts'), 'w') as fd:
+ with open(make_fname(ubman, 'u-boot.dts'), 'w') as fd:
fd.write(base_fdt)
return fit
-def make_kernel(cons, basename, text):
+def make_kernel(ubman, basename, text):
"""Make a sample kernel with test data
Args:
- cons (ConsoleBase): u_boot_console to use
+ ubman (ConsoleBase): ubman to use
basename (str): base name to write to (will be placed in the temp dir)
text (str): Contents of the kernel file (will be repeated 100 times)
Returns:
str: Full path and filename of the kernel it created
"""
- fname = make_fname(cons, basename)
+ fname = make_fname(ubman, basename)
data = ''
for i in range(100):
data += f'this {text} {i} is unlikely to boot\n'
@@ -78,16 +78,16 @@
print(data, file=outf)
return fname
-def make_dtb(cons, base_fdt, basename):
+def make_dtb(ubman, base_fdt, basename):
"""Make a sample .dts file and compile it to a .dtb
Returns:
- cons (ConsoleBase): u_boot_console to use
+ ubman (ConsoleBase): ubman to use
Filename of .dtb file created
"""
- src = make_fname(cons, f'{basename}.dts')
- dtb = make_fname(cons, f'{basename}.dtb')
+ src = make_fname(ubman, f'{basename}.dts')
+ dtb = make_fname(ubman, f'{basename}.dtb')
with open(src, 'w', encoding='utf-8') as outf:
outf.write(base_fdt)
- util.run_and_log(cons, ['dtc', src, '-O', 'dtb', '-o', dtb])
+ utils.run_and_log(ubman, ['dtc', src, '-O', 'dtb', '-o', dtb])
return dtb
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index ccfc020..d85e2b9 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -54,7 +54,7 @@
try:
check_call(f'rm -f {fs_img}', shell=True)
- check_call(f'dd if=/dev/zero of={fs_img} bs={size_gran} count={count}',
+ check_call(f'truncate -s $(( {size_gran} * {count} )) {fs_img}',
shell=True)
check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True)
if fs_type == 'ext4':
diff --git a/test/py/tests/test_000_version.py b/test/py/tests/test_000_version.py
index bd089ab..b95ceae 100644
--- a/test/py/tests/test_000_version.py
+++ b/test/py/tests/test_000_version.py
@@ -7,13 +7,13 @@
# first, simply as a very basic sanity check of the functionality of the U-Boot
# command prompt.
-def test_version(u_boot_console):
+def test_version(ubman):
"""Test that the "version" command prints the U-Boot version."""
# "version" prints the U-Boot sign-on message. This is usually considered
# an error, so that any unexpected reboot causes an error. Here, this
# error detection is disabled since the sign-on message is expected.
- with u_boot_console.disable_check('main_signon'):
- response = u_boot_console.run_command('version')
+ with ubman.disable_check('main_signon'):
+ response = ubman.run_command('version')
# Ensure "version" printed what we expected.
- u_boot_console.validate_version_string_in_text(response)
+ ubman.validate_version_string_in_text(response)
diff --git a/test/py/tests/test_android/test_ab.py b/test/py/tests/test_android/test_ab.py
index 9bf1a0e..5876a13 100644
--- a/test/py/tests/test_android/test_ab.py
+++ b/test/py/tests/test_android/test_ab.py
@@ -5,16 +5,16 @@
import os
import pytest
-import u_boot_utils
+import utils
class ABTestDiskImage(object):
"""Disk Image used by the A/B tests."""
- def __init__(self, u_boot_console):
+ def __init__(self, ubman):
"""Initialize a new ABTestDiskImage object.
Args:
- u_boot_console: A U-Boot console.
+ ubman: A U-Boot console.
Returns:
Nothing.
@@ -22,40 +22,40 @@
filename = 'test_ab_disk_image.bin'
- persistent = u_boot_console.config.persistent_data_dir + '/' + filename
- self.path = u_boot_console.config.result_dir + '/' + filename
+ persistent = ubman.config.persistent_data_dir + '/' + filename
+ self.path = ubman.config.result_dir + '/' + filename
- with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
+ with utils.persistent_file_helper(ubman.log, persistent):
if os.path.exists(persistent):
- u_boot_console.log.action('Disk image file ' + persistent +
+ ubman.log.action('Disk image file ' + persistent +
' already exists')
else:
- u_boot_console.log.action('Generating ' + persistent)
+ ubman.log.action('Generating ' + persistent)
fd = os.open(persistent, os.O_RDWR | os.O_CREAT)
os.ftruncate(fd, 524288)
os.close(fd)
cmd = ('sgdisk', persistent)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('sgdisk', '--new=1:64:512', '--change-name=1:misc',
persistent)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('sgdisk', '--load-backup=' + persistent)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('cp', persistent, self.path)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
di = None
@pytest.fixture(scope='function')
-def ab_disk_image(u_boot_console):
+def ab_disk_image(ubman):
global di
if not di:
- di = ABTestDiskImage(u_boot_console)
+ di = ABTestDiskImage(ubman)
return di
-def ab_dump(u_boot_console, slot_num, crc):
- output = u_boot_console.run_command('bcb ab_dump host 0#misc')
+def ab_dump(ubman, slot_num, crc):
+ output = ubman.run_command('bcb ab_dump host 0#misc')
header, slot0, slot1 = output.split('\r\r\n\r\r\n')
slots = [slot0, slot1]
slot_suffixes = ['_a', '_b']
@@ -79,20 +79,20 @@
@pytest.mark.buildconfigspec('android_ab')
@pytest.mark.buildconfigspec('cmd_bcb')
@pytest.mark.requiredtool('sgdisk')
-def test_ab(ab_disk_image, u_boot_console):
+def test_ab(ab_disk_image, ubman):
"""Test the 'bcb ab_select' command."""
- u_boot_console.run_command('host bind 0 ' + ab_disk_image.path)
+ ubman.run_command('host bind 0 ' + ab_disk_image.path)
- output = u_boot_console.run_command('bcb ab_select slot_name host 0#misc')
+ output = ubman.run_command('bcb ab_select slot_name host 0#misc')
assert 're-initializing A/B metadata' in output
assert 'Attempting slot a, tries remaining 7' in output
- output = u_boot_console.run_command('printenv slot_name')
+ output = ubman.run_command('printenv slot_name')
assert 'slot_name=a' in output
- ab_dump(u_boot_console, 0, '0xd438d1b9')
+ ab_dump(ubman, 0, '0xd438d1b9')
- output = u_boot_console.run_command('bcb ab_select slot_name host 0:1')
+ output = ubman.run_command('bcb ab_select slot_name host 0:1')
assert 'Attempting slot b, tries remaining 7' in output
- output = u_boot_console.run_command('printenv slot_name')
+ output = ubman.run_command('printenv slot_name')
assert 'slot_name=b' in output
- ab_dump(u_boot_console, 1, '0x011ec016')
+ ab_dump(ubman, 1, '0x011ec016')
diff --git a/test/py/tests/test_android/test_abootimg.py b/test/py/tests/test_android/test_abootimg.py
index 6a8ff34..2aadb69 100644
--- a/test/py/tests/test_android/test_abootimg.py
+++ b/test/py/tests/test_android/test_abootimg.py
@@ -6,7 +6,7 @@
import os
import pytest
-import u_boot_utils
+import utils
"""
These tests rely on disk image (boot.img), which is automatically created by
@@ -105,78 +105,78 @@
class AbootimgTestDiskImage(object):
"""Disk image used by abootimg tests."""
- def __init__(self, u_boot_console, image_name, hex_img):
+ def __init__(self, ubman, image_name, hex_img):
"""Initialize a new AbootimgDiskImage object.
Args:
- u_boot_console: A U-Boot console.
+ ubman: A U-Boot console.
Returns:
Nothing.
"""
- gz_hex = u_boot_console.config.persistent_data_dir + '/' + image_name + '.gz.hex'
- gz = u_boot_console.config.persistent_data_dir + '/' + image_name + '.gz'
+ gz_hex = ubman.config.persistent_data_dir + '/' + image_name + '.gz.hex'
+ gz = ubman.config.persistent_data_dir + '/' + image_name + '.gz'
filename = image_name
- persistent = u_boot_console.config.persistent_data_dir + '/' + filename
- self.path = u_boot_console.config.result_dir + '/' + filename
- u_boot_console.log.action('persistent is ' + persistent)
- with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
+ persistent = ubman.config.persistent_data_dir + '/' + filename
+ self.path = ubman.config.result_dir + '/' + filename
+ ubman.log.action('persistent is ' + persistent)
+ with utils.persistent_file_helper(ubman.log, persistent):
if os.path.exists(persistent):
- u_boot_console.log.action('Disk image file ' + persistent +
+ ubman.log.action('Disk image file ' + persistent +
' already exists')
else:
- u_boot_console.log.action('Generating ' + persistent)
+ ubman.log.action('Generating ' + persistent)
f = open(gz_hex, "w")
f.write(hex_img)
f.close()
cmd = ('xxd', '-r', '-p', gz_hex, gz)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('gunzip', '-9', gz)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('cp', persistent, self.path)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
gtdi1 = None
@pytest.fixture(scope='function')
-def abootimg_disk_image(u_boot_console):
+def abootimg_disk_image(ubman):
"""pytest fixture to provide a AbootimgTestDiskImage object to tests.
- This is function-scoped because it uses u_boot_console, which is also
+ This is function-scoped because it uses ubman, which is also
function-scoped. However, we don't need to actually do any function-scope
work, so this simply returns the same object over and over each time."""
global gtdi1
if not gtdi1:
- gtdi1 = AbootimgTestDiskImage(u_boot_console, 'boot.img', img_hex)
+ gtdi1 = AbootimgTestDiskImage(ubman, 'boot.img', img_hex)
return gtdi1
gtdi2 = None
@pytest.fixture(scope='function')
-def abootimgv4_disk_image_vboot(u_boot_console):
+def abootimgv4_disk_image_vboot(ubman):
"""pytest fixture to provide a AbootimgTestDiskImage object to tests.
- This is function-scoped because it uses u_boot_console, which is also
+ This is function-scoped because it uses ubman, which is also
function-scoped. However, we don't need to actually do any function-scope
work, so this simply returns the same object over and over each time."""
global gtdi2
if not gtdi2:
- gtdi2 = AbootimgTestDiskImage(u_boot_console, 'vendor_boot.img', vboot_img_hex)
+ gtdi2 = AbootimgTestDiskImage(ubman, 'vendor_boot.img', vboot_img_hex)
return gtdi2
gtdi3 = None
@pytest.fixture(scope='function')
-def abootimgv4_disk_image_boot(u_boot_console):
+def abootimgv4_disk_image_boot(ubman):
"""pytest fixture to provide a AbootimgTestDiskImage object to tests.
- This is function-scoped because it uses u_boot_console, which is also
+ This is function-scoped because it uses ubman, which is also
function-scoped. However, we don't need to actually do any function-scope
work, so this simply returns the same object over and over each time."""
global gtdi3
if not gtdi3:
- gtdi3 = AbootimgTestDiskImage(u_boot_console, 'bootv4.img', boot_img_hex)
+ gtdi3 = AbootimgTestDiskImage(ubman, 'bootv4.img', boot_img_hex)
return gtdi3
@pytest.mark.boardspec('sandbox')
@@ -185,42 +185,42 @@
@pytest.mark.buildconfigspec('cmd_fdt')
@pytest.mark.requiredtool('xxd')
@pytest.mark.requiredtool('gunzip')
-def test_abootimg(abootimg_disk_image, u_boot_console):
+def test_abootimg(abootimg_disk_image, ubman):
"""Test the 'abootimg' command."""
- u_boot_console.log.action('Loading disk image to RAM...')
- u_boot_console.run_command('setenv loadaddr 0x%x' % (loadaddr))
- u_boot_console.run_command('host load hostfs - 0x%x %s' % (loadaddr,
+ ubman.log.action('Loading disk image to RAM...')
+ ubman.run_command('setenv loadaddr 0x%x' % (loadaddr))
+ ubman.run_command('host load hostfs - 0x%x %s' % (loadaddr,
abootimg_disk_image.path))
- u_boot_console.log.action('Testing \'abootimg get ver\'...')
- response = u_boot_console.run_command('abootimg get ver')
+ ubman.log.action('Testing \'abootimg get ver\'...')
+ response = ubman.run_command('abootimg get ver')
assert response == "2"
- u_boot_console.run_command('abootimg get ver v')
- response = u_boot_console.run_command('env print v')
+ ubman.run_command('abootimg get ver v')
+ response = ubman.run_command('env print v')
assert response == 'v=2'
- u_boot_console.log.action('Testing \'abootimg get recovery_dtbo\'...')
- response = u_boot_console.run_command('abootimg get recovery_dtbo a')
+ ubman.log.action('Testing \'abootimg get recovery_dtbo\'...')
+ response = ubman.run_command('abootimg get recovery_dtbo a')
assert response == 'Error: recovery_dtbo_size is 0'
- u_boot_console.log.action('Testing \'abootimg dump dtb\'...')
- response = u_boot_console.run_command('abootimg dump dtb').replace('\r', '')
+ ubman.log.action('Testing \'abootimg dump dtb\'...')
+ response = ubman.run_command('abootimg dump dtb').replace('\r', '')
assert response == dtb_dump_resp
- u_boot_console.log.action('Testing \'abootimg get dtb_load_addr\'...')
- u_boot_console.run_command('abootimg get dtb_load_addr a')
- response = u_boot_console.run_command('env print a')
+ ubman.log.action('Testing \'abootimg get dtb_load_addr\'...')
+ ubman.run_command('abootimg get dtb_load_addr a')
+ response = ubman.run_command('env print a')
assert response == 'a=11f00000'
- u_boot_console.log.action('Testing \'abootimg get dtb --index\'...')
- u_boot_console.run_command('abootimg get dtb --index=1 dtb1_start')
- response = u_boot_console.run_command('env print dtb1_start')
+ ubman.log.action('Testing \'abootimg get dtb --index\'...')
+ ubman.run_command('abootimg get dtb --index=1 dtb1_start')
+ response = ubman.run_command('env print dtb1_start')
correct_str = "dtb1_start=%x" % (dtb1_addr)
assert response == correct_str
- u_boot_console.run_command('fdt addr $dtb1_start')
- u_boot_console.run_command('fdt get value v / model')
- response = u_boot_console.run_command('env print v')
+ ubman.run_command('fdt addr $dtb1_start')
+ ubman.run_command('fdt get value v / model')
+ response = ubman.run_command('env print v')
assert response == 'v=x2'
@pytest.mark.boardspec('sandbox')
@@ -229,41 +229,40 @@
@pytest.mark.buildconfigspec('cmd_fdt')
@pytest.mark.requiredtool('xxd')
@pytest.mark.requiredtool('gunzip')
-def test_abootimgv4(abootimgv4_disk_image_vboot, abootimgv4_disk_image_boot, u_boot_console):
+def test_abootimgv4(abootimgv4_disk_image_vboot, abootimgv4_disk_image_boot, ubman):
"""Test the 'abootimg' command with boot image header v4."""
- cons = u_boot_console
- cons.log.action('Loading disk image to RAM...')
- cons.run_command('setenv loadaddr 0x%x' % (loadaddr))
- cons.run_command('setenv vloadaddr 0x%x' % (vloadaddr))
- cons.run_command('host load hostfs - 0x%x %s' % (vloadaddr,
+ ubman.log.action('Loading disk image to RAM...')
+ ubman.run_command('setenv loadaddr 0x%x' % (loadaddr))
+ ubman.run_command('setenv vloadaddr 0x%x' % (vloadaddr))
+ ubman.run_command('host load hostfs - 0x%x %s' % (vloadaddr,
abootimgv4_disk_image_vboot.path))
- cons.run_command('host load hostfs - 0x%x %s' % (loadaddr,
+ ubman.run_command('host load hostfs - 0x%x %s' % (loadaddr,
abootimgv4_disk_image_boot.path))
- cons.run_command('abootimg addr 0x%x 0x%x' % (loadaddr, vloadaddr))
- cons.log.action('Testing \'abootimg get ver\'...')
- response = cons.run_command('abootimg get ver')
+ ubman.run_command('abootimg addr 0x%x 0x%x' % (loadaddr, vloadaddr))
+ ubman.log.action('Testing \'abootimg get ver\'...')
+ response = ubman.run_command('abootimg get ver')
assert response == "4"
- cons.run_command('abootimg get ver v')
- response = cons.run_command('env print v')
+ ubman.run_command('abootimg get ver v')
+ response = ubman.run_command('env print v')
assert response == 'v=4'
- cons.log.action('Testing \'abootimg get recovery_dtbo\'...')
- response = cons.run_command('abootimg get recovery_dtbo a')
+ ubman.log.action('Testing \'abootimg get recovery_dtbo\'...')
+ response = ubman.run_command('abootimg get recovery_dtbo a')
assert response == 'Error: header version must be >= 1 and <= 2 to get dtbo'
- cons.log.action('Testing \'abootimg get dtb_load_addr\'...')
- cons.run_command('abootimg get dtb_load_addr a')
- response = cons.run_command('env print a')
+ ubman.log.action('Testing \'abootimg get dtb_load_addr\'...')
+ ubman.run_command('abootimg get dtb_load_addr a')
+ response = ubman.run_command('env print a')
assert response == 'a=11f00000'
- cons.log.action('Testing \'abootimg get dtb --index\'...')
- cons.run_command('abootimg get dtb --index=1 dtb2_start')
- response = cons.run_command('env print dtb2_start')
+ ubman.log.action('Testing \'abootimg get dtb --index\'...')
+ ubman.run_command('abootimg get dtb --index=1 dtb2_start')
+ response = ubman.run_command('env print dtb2_start')
correct_str = "dtb2_start=%x" % (dtb2_addr)
assert response == correct_str
- cons.run_command('fdt addr $dtb2_start')
- cons.run_command('fdt get value v / model')
- response = cons.run_command('env print v')
+ ubman.run_command('fdt addr $dtb2_start')
+ ubman.run_command('fdt get value v / model')
+ response = ubman.run_command('env print v')
assert response == 'v=x2'
diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py
index 865efbc..137d83e 100644
--- a/test/py/tests/test_android/test_avb.py
+++ b/test/py/tests/test_android/test_avb.py
@@ -15,7 +15,6 @@
"""
import pytest
-import u_boot_utils as util
# defauld mmc id
mmc_dev = 1
@@ -24,34 +23,34 @@
@pytest.mark.buildconfigspec('cmd_avb')
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_avb_verify(u_boot_console):
+def test_avb_verify(ubman):
"""Run AVB 2.0 boot verification chain with avb subset of commands
"""
success_str = "Verification passed successfully"
- response = u_boot_console.run_command('avb init %s' %str(mmc_dev))
+ response = ubman.run_command('avb init %s' %str(mmc_dev))
assert response == ''
- response = u_boot_console.run_command('avb verify')
+ response = ubman.run_command('avb verify')
assert response.find(success_str)
@pytest.mark.buildconfigspec('cmd_avb')
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.notbuildconfigspec('sandbox')
-def test_avb_mmc_uuid(u_boot_console):
+def test_avb_mmc_uuid(ubman):
"""Check if 'avb get_uuid' works, compare results with
'part list mmc 1' output
"""
- response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+ response = ubman.run_command('avb init %s' % str(mmc_dev))
assert response == ''
- response = u_boot_console.run_command('mmc rescan; mmc dev %s' %
+ response = ubman.run_command('mmc rescan; mmc dev %s' %
str(mmc_dev))
assert response.find('is current device')
- part_lines = u_boot_console.run_command('mmc part').splitlines()
+ part_lines = ubman.run_command('mmc part').splitlines()
part_list = {}
cur_partname = ''
@@ -67,72 +66,72 @@
# lets check all guids with avb get_guid
for part, guid in part_list.items():
- avb_guid_resp = u_boot_console.run_command('avb get_uuid %s' % part)
+ avb_guid_resp = ubman.run_command('avb get_uuid %s' % part)
assert guid == avb_guid_resp.split('UUID: ')[1]
@pytest.mark.buildconfigspec('cmd_avb')
-def test_avb_read_rb(u_boot_console):
+def test_avb_read_rb(ubman):
"""Test reading rollback indexes
"""
- response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+ response = ubman.run_command('avb init %s' % str(mmc_dev))
assert response == ''
- response = u_boot_console.run_command('avb read_rb 1')
+ response = ubman.run_command('avb read_rb 1')
assert response == 'Rollback index: 0'
@pytest.mark.buildconfigspec('cmd_avb')
-def test_avb_is_unlocked(u_boot_console):
+def test_avb_is_unlocked(ubman):
"""Test if device is in the unlocked state
"""
- response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+ response = ubman.run_command('avb init %s' % str(mmc_dev))
assert response == ''
- response = u_boot_console.run_command('avb is_unlocked')
+ response = ubman.run_command('avb is_unlocked')
assert response == 'Unlocked = 1'
@pytest.mark.buildconfigspec('cmd_avb')
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.notbuildconfigspec('sandbox')
-def test_avb_mmc_read(u_boot_console):
+def test_avb_mmc_read(ubman):
"""Test mmc read operation
"""
- response = u_boot_console.run_command('mmc rescan; mmc dev %s 0' %
+ response = ubman.run_command('mmc rescan; mmc dev %s 0' %
str(mmc_dev))
assert response.find('is current device')
- response = u_boot_console.run_command('mmc read 0x%x 0x100 0x1' % temp_addr)
+ response = ubman.run_command('mmc read 0x%x 0x100 0x1' % temp_addr)
assert response.find('read: OK')
- response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+ response = ubman.run_command('avb init %s' % str(mmc_dev))
assert response == ''
- response = u_boot_console.run_command('avb read_part xloader 0 100 0x%x' %
+ response = ubman.run_command('avb read_part xloader 0 100 0x%x' %
temp_addr2)
assert response.find('Read 512 bytes')
# Now lets compare two buffers
- response = u_boot_console.run_command('cmp 0x%x 0x%x 40' %
+ response = ubman.run_command('cmp 0x%x 0x%x 40' %
(temp_addr, temp_addr2))
assert response.find('64 word')
@pytest.mark.buildconfigspec('cmd_avb')
@pytest.mark.buildconfigspec('optee_ta_avb')
-def test_avb_persistent_values(u_boot_console):
+def test_avb_persistent_values(ubman):
"""Test reading/writing persistent storage to avb
"""
- response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+ response = ubman.run_command('avb init %s' % str(mmc_dev))
assert response == ''
- response = u_boot_console.run_command('avb write_pvalue test value_value')
+ response = ubman.run_command('avb write_pvalue test value_value')
assert response == 'Wrote 12 bytes'
- response = u_boot_console.run_command('avb read_pvalue test 12')
+ response = ubman.run_command('avb read_pvalue test 12')
assert response == 'Read 12 bytes, value = value_value'
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 1376ab5..16c63ae 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -27,82 +27,82 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_bind')
-def test_bind_unbind_with_node(u_boot_console):
+def test_bind_unbind_with_node(ubman):
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
#bind usb_ether driver (which has no compatible) to usb@1 node.
##New entry usb_ether should appear in the dm tree
- response = u_boot_console.run_command('bind /usb@1 usb_ether')
+ response = ubman.run_command('bind /usb@1 usb_ether')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True)
#Unbind child #1. No error expected and all devices should be there except for bind-test-child1
- response = u_boot_console.run_command('unbind /bind-test/bind-test-child1')
+ response = ubman.run_command('unbind /bind-test/bind-test-child1')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
assert 'bind-test-child1' not in tree
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
#bind child #1. No error expected and all devices should be there
- response = u_boot_console.run_command('bind /bind-test/bind-test-child1 phy_sandbox')
+ response = ubman.run_command('bind /bind-test/bind-test-child1 phy_sandbox')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True)
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, False)
#Unbind child #2. No error expected and all devices should be there except for bind-test-child2
- response = u_boot_console.run_command('unbind /bind-test/bind-test-child2')
+ response = ubman.run_command('unbind /bind-test/bind-test-child2')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True)
assert 'bind-test-child2' not in tree
#Bind child #2. No error expected and all devices should be there
- response = u_boot_console.run_command('bind /bind-test/bind-test-child2 simple_bus')
+ response = ubman.run_command('bind /bind-test/bind-test-child2 simple_bus')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
#Unbind parent. No error expected. All devices should be removed and unbound
- response = u_boot_console.run_command('unbind /bind-test')
+ response = ubman.run_command('unbind /bind-test')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert 'bind-test' not in tree
assert 'bind-test-child1' not in tree
assert 'bind-test-child2' not in tree
#try binding invalid node with valid driver
- response = u_boot_console.run_command('bind /not-a-valid-node simple_bus')
+ response = ubman.run_command('bind /not-a-valid-node simple_bus')
assert response != ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert 'not-a-valid-node' not in tree
#try binding valid node with invalid driver
- response = u_boot_console.run_command('bind /bind-test not_a_driver')
+ response = ubman.run_command('bind /bind-test not_a_driver')
assert response != ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert 'bind-test' not in tree
#bind /bind-test. Device should come up as well as its children
- response = u_boot_console.run_command('bind /bind-test simple_bus')
+ response = ubman.run_command('bind /bind-test simple_bus')
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
- response = u_boot_console.run_command('unbind /bind-test')
+ response = ubman.run_command('unbind /bind-test')
assert response == ''
def get_next_line(tree, name):
@@ -120,13 +120,13 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_bind')
@pytest.mark.singlethread
-def test_bind_unbind_with_uclass(u_boot_console):
+def test_bind_unbind_with_uclass(ubman):
#bind /bind-test
- response = u_boot_console.run_command('bind /bind-test simple_bus')
+ response = ubman.run_command('bind /bind-test simple_bus')
assert response == ''
#make sure bind-test-child2 is there and get its uclass/index pair
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
child2_line = [x.strip() for x in tree.splitlines() if '-- bind-test-child2' in x]
assert len(child2_line) == 1
@@ -134,11 +134,11 @@
child2_index = int(child2_line[0].split()[1])
#bind simple_bus as a child of bind-test-child2
- response = u_boot_console.run_command(
+ response = ubman.run_command(
'bind {} {} simple_bus'.format(child2_uclass, child2_index))
#check that the child is there and its uclass/index pair is right
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
child_of_child2_line = get_next_line(tree, 'bind-test-child2')
assert child_of_child2_line
@@ -147,20 +147,20 @@
assert child_of_child2_index == child2_index + 1
#unbind the child and check it has been removed
- response = u_boot_console.run_command('unbind simple_bus {}'.format(child_of_child2_index))
+ response = ubman.run_command('unbind simple_bus {}'.format(child_of_child2_index))
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
assert not in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True)
child_of_child2_line = get_next_line(tree, 'bind-test-child2')
assert child_of_child2_line == ''
#bind simple_bus as a child of bind-test-child2
- response = u_boot_console.run_command(
+ response = ubman.run_command(
'bind {} {} simple_bus'.format(child2_uclass, child2_index))
#check that the child is there and its uclass/index pair is right
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
treelines = [x.strip() for x in tree.splitlines() if x.strip()]
child_of_child2_line = get_next_line(tree, 'bind-test-child2')
@@ -170,24 +170,24 @@
assert child_of_child2_index == child2_index + 1
#unbind the child and check it has been removed
- response = u_boot_console.run_command(
+ response = ubman.run_command(
'unbind {} {} simple_bus'.format(child2_uclass, child2_index))
assert response == ''
- tree = u_boot_console.run_command('dm tree')
+ tree = ubman.run_command('dm tree')
assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
child_of_child2_line = get_next_line(tree, 'bind-test-child2')
assert child_of_child2_line == ''
#unbind the child again and check it doesn't change the tree
- tree_old = u_boot_console.run_command('dm tree')
- response = u_boot_console.run_command(
+ tree_old = ubman.run_command('dm tree')
+ response = ubman.run_command(
'unbind {} {} simple_bus'.format(child2_uclass, child2_index))
- tree_new = u_boot_console.run_command('dm tree')
+ tree_new = ubman.run_command('dm tree')
assert response == ''
assert tree_old == tree_new
- response = u_boot_console.run_command('unbind /bind-test')
+ response = ubman.run_command('unbind /bind-test')
assert response == ''
diff --git a/test/py/tests/test_bootmenu.py b/test/py/tests/test_bootmenu.py
index 70f51de..66f3fb8 100644
--- a/test/py/tests/test_bootmenu.py
+++ b/test/py/tests/test_bootmenu.py
@@ -5,42 +5,42 @@
import pytest
@pytest.mark.buildconfigspec('cmd_bootmenu')
-def test_bootmenu(u_boot_console):
+def test_bootmenu(ubman):
"""Test bootmenu
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
"""
- with u_boot_console.temporary_timeout(500):
- u_boot_console.run_command('setenv bootmenu_default 1')
- u_boot_console.run_command('setenv bootmenu_0 test 1=echo ok 1')
- u_boot_console.run_command('setenv bootmenu_1 test 2=echo ok 2')
- u_boot_console.run_command('setenv bootmenu_2 test 3=echo ok 3')
- u_boot_console.run_command('bootmenu 2', wait_for_prompt=False)
+ with ubman.temporary_timeout(500):
+ ubman.run_command('setenv bootmenu_default 1')
+ ubman.run_command('setenv bootmenu_0 test 1=echo ok 1')
+ ubman.run_command('setenv bootmenu_1 test 2=echo ok 2')
+ ubman.run_command('setenv bootmenu_2 test 3=echo ok 3')
+ ubman.run_command('bootmenu 2', wait_for_prompt=False)
for i in ('U-Boot Boot Menu', 'test 1', 'test 2', 'test 3', 'autoboot'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Press enter key to execute default entry
- response = u_boot_console.run_command(cmd='\x0d', wait_for_echo=False, send_nl=False)
+ response = ubman.run_command(cmd='\x0d', wait_for_echo=False, send_nl=False)
assert 'ok 2' in response
- u_boot_console.run_command('bootmenu 2', wait_for_prompt=False)
- u_boot_console.p.expect(['autoboot'])
+ ubman.run_command('bootmenu 2', wait_for_prompt=False)
+ ubman.p.expect(['autoboot'])
# Press up key to select prior entry followed by the enter key
- response = u_boot_console.run_command(cmd='\x1b\x5b\x41\x0d', wait_for_echo=False,
+ response = ubman.run_command(cmd='\x1b\x5b\x41\x0d', wait_for_echo=False,
send_nl=False)
assert 'ok 1' in response
- u_boot_console.run_command('bootmenu 2', wait_for_prompt=False)
- u_boot_console.p.expect(['autoboot'])
+ ubman.run_command('bootmenu 2', wait_for_prompt=False)
+ ubman.p.expect(['autoboot'])
# Press down key to select next entry followed by the enter key
- response = u_boot_console.run_command(cmd='\x1b\x5b\x42\x0d', wait_for_echo=False,
+ response = ubman.run_command(cmd='\x1b\x5b\x42\x0d', wait_for_echo=False,
send_nl=False)
assert 'ok 3' in response
- u_boot_console.run_command('bootmenu 2; echo rc:$?', wait_for_prompt=False)
- u_boot_console.p.expect(['autoboot'])
+ ubman.run_command('bootmenu 2; echo rc:$?', wait_for_prompt=False)
+ ubman.p.expect(['autoboot'])
# Press the escape key
- response = u_boot_console.run_command(cmd='\x1b', wait_for_echo=False, send_nl=False)
+ response = ubman.run_command(cmd='\x1b', wait_for_echo=False, send_nl=False)
assert 'ok' not in response
assert 'rc:0' in response
- u_boot_console.run_command('setenv bootmenu_default')
- u_boot_console.run_command('setenv bootmenu_0')
- u_boot_console.run_command('setenv bootmenu_1')
- u_boot_console.run_command('setenv bootmenu_2')
+ ubman.run_command('setenv bootmenu_default')
+ ubman.run_command('setenv bootmenu_0')
+ ubman.run_command('setenv bootmenu_1')
+ ubman.run_command('setenv bootmenu_2')
diff --git a/test/py/tests/test_bootstage.py b/test/py/tests/test_bootstage.py
index bd71a1a..379c1ca 100644
--- a/test/py/tests/test_bootstage.py
+++ b/test/py/tests/test_bootstage.py
@@ -24,8 +24,8 @@
@pytest.mark.buildconfigspec('bootstage')
@pytest.mark.buildconfigspec('cmd_bootstage')
-def test_bootstage_report(u_boot_console):
- output = u_boot_console.run_command('bootstage report')
+def test_bootstage_report(ubman):
+ output = ubman.run_command('bootstage report')
assert 'Timer summary in microseconds' in output
assert 'Accumulated time:' in output
assert 'dm_r' in output
@@ -33,8 +33,8 @@
@pytest.mark.buildconfigspec('bootstage')
@pytest.mark.buildconfigspec('cmd_bootstage')
@pytest.mark.buildconfigspec('bootstage_stash')
-def test_bootstage_stash_and_unstash(u_boot_console):
- f = u_boot_console.config.env.get('env__bootstage_cmd_file', None)
+def test_bootstage_stash_and_unstash(ubman):
+ f = ubman.config.env.get('env__bootstage_cmd_file', None)
if not f:
pytest.skip('No bootstage environment file is defined')
@@ -43,11 +43,11 @@
bootstage_magic = f.get('bootstage_magic_addr')
expected_text = 'dm_r'
- u_boot_console.run_command('bootstage stash %x %x' % (addr, size))
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('bootstage stash %x %x' % (addr, size))
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- output = u_boot_console.run_command('md %x 100' % addr)
+ output = ubman.run_command('md %x 100' % addr)
# Check BOOTSTAGE_MAGIC address at 4th byte address
assert '0x' + output.split('\n')[0].split()[4] == hex(bootstage_magic)
@@ -57,6 +57,6 @@
assert expected_text in output_last_col
# Check that unstash works as expected
- u_boot_console.run_command('bootstage unstash %x %x' % (addr, size))
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('bootstage unstash %x %x' % (addr, size))
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
diff --git a/test/py/tests/test_button.py b/test/py/tests/test_button.py
index 3b7f148..f0d85be 100644
--- a/test/py/tests/test_button.py
+++ b/test/py/tests/test_button.py
@@ -4,10 +4,10 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_button')
-def test_button_list(u_boot_console):
+def test_button_list(ubman):
"""Test listing buttons"""
- response = u_boot_console.run_command('button list; echo rc:$?')
+ response = ubman.run_command('button list; echo rc:$?')
assert('button1' in response)
assert('button2' in response)
assert('rc:0' in response)
@@ -15,23 +15,23 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_button')
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_button_return_code(u_boot_console):
+def test_button_return_code(ubman):
"""Test correct reporting of the button status
The sandbox gpio driver reports the last output value as input value.
We can use this in our test to emulate different input statuses.
"""
- u_boot_console.run_command('gpio set a3; gpio input a3');
- response = u_boot_console.run_command('button button1; echo rc:$?')
+ ubman.run_command('gpio set a3; gpio input a3');
+ response = ubman.run_command('button button1; echo rc:$?')
assert('on' in response)
assert('rc:0' in response)
- u_boot_console.run_command('gpio clear a3; gpio input a3');
- response = u_boot_console.run_command('button button1; echo rc:$?')
+ ubman.run_command('gpio clear a3; gpio input a3');
+ response = ubman.run_command('button button1; echo rc:$?')
assert('off' in response)
assert('rc:1' in response)
- response = u_boot_console.run_command('button nonexistent-button; echo rc:$?')
+ response = ubman.run_command('button nonexistent-button; echo rc:$?')
assert('not found' in response)
assert('rc:1' in response)
diff --git a/test/py/tests/test_cat/test_cat.py b/test/py/tests/test_cat/test_cat.py
index 132527b..883803f 100644
--- a/test/py/tests/test_cat/test_cat.py
+++ b/test/py/tests/test_cat/test_cat.py
@@ -7,14 +7,14 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_cat')
-def test_cat(u_boot_console, cat_data):
+def test_cat(ubman, cat_data):
""" Unit test for cat
Args:
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
cat_data -- Path to the disk image used for testing.
"""
- response = u_boot_console.run_command_list([
+ response = ubman.run_command_list([
f'host bind 0 {cat_data}',
'cat host 0 hello'])
assert 'hello world' in response
diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 5d87eb3..7d6f41d 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -9,7 +9,7 @@
import os
import os.path
import pytest
-import u_boot_utils
+import utils
"""
Note: This test relies on:
@@ -113,13 +113,13 @@
@pytest.mark.buildconfigspec('cmd_dfu')
@pytest.mark.requiredtool('dfu-util')
-def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
+def test_dfu(ubman, env__usb_dev_port, env__dfu_config):
"""Test the "dfu" command; the host system must be able to enumerate a USB
device when "dfu" is running, various DFU transfers are tested, and the
USB device must disappear when "dfu" is aborted.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__usb_dev_port: The single USB device-mode port specification on
which to run the test. See the file-level comment above for
details of the format.
@@ -143,15 +143,15 @@
Nothing.
"""
- u_boot_utils.wait_until_file_open_fails(
+ utils.wait_until_file_open_fails(
env__usb_dev_port['host_usb_dev_node'], True)
- fh = u_boot_utils.attempt_to_open_file(
+ fh = utils.attempt_to_open_file(
env__usb_dev_port['host_usb_dev_node'])
if fh:
fh.close()
raise Exception('USB device present before dfu command invoked')
- u_boot_console.log.action(
+ ubman.log.action(
'Starting long-running U-Boot dfu shell command')
dfu_alt_info_env = env__dfu_config.get('alt_info_env_name', \
@@ -159,12 +159,12 @@
cmd = 'setenv "%s" "%s"' % (dfu_alt_info_env,
env__dfu_config['alt_info'])
- u_boot_console.run_command(cmd)
+ ubman.run_command(cmd)
cmd = 'dfu 0 ' + env__dfu_config['cmd_params']
- u_boot_console.run_command(cmd, wait_for_prompt=False)
- u_boot_console.log.action('Waiting for DFU USB device to appear')
- fh = u_boot_utils.wait_until_open_succeeds(
+ ubman.run_command(cmd, wait_for_prompt=False)
+ ubman.log.action('Waiting for DFU USB device to appear')
+ fh = utils.wait_until_open_succeeds(
env__usb_dev_port['host_usb_dev_node'])
fh.close()
@@ -185,12 +185,12 @@
"""
try:
- u_boot_console.log.action(
+ ubman.log.action(
'Stopping long-running U-Boot dfu shell command')
- u_boot_console.ctrlc()
- u_boot_console.log.action(
+ ubman.ctrlc()
+ ubman.log.action(
'Waiting for DFU USB device to disappear')
- u_boot_utils.wait_until_file_open_fails(
+ utils.wait_until_file_open_fails(
env__usb_dev_port['host_usb_dev_node'], ignore_errors)
except:
if not ignore_errors:
@@ -213,8 +213,8 @@
cmd = ['dfu-util', '-a', alt_setting, up_dn_load_arg, fn]
if 'host_usb_port_path' in env__usb_dev_port:
cmd += ['-p', env__usb_dev_port['host_usb_port_path']]
- u_boot_utils.run_and_log(u_boot_console, cmd)
- u_boot_console.wait_for('Ctrl+C to exit ...')
+ utils.run_and_log(ubman, cmd)
+ ubman.wait_for('Ctrl+C to exit ...')
def dfu_write(alt_setting, fn):
"""Write a file to the target board using DFU.
@@ -261,25 +261,25 @@
Nothing.
"""
- test_f = u_boot_utils.PersistentRandomFile(u_boot_console,
+ test_f = utils.PersistentRandomFile(ubman,
'dfu_%d.bin' % size, size)
- readback_fn = u_boot_console.config.result_dir + '/dfu_readback.bin'
+ readback_fn = ubman.config.result_dir + '/dfu_readback.bin'
- u_boot_console.log.action('Writing test data to DFU primary ' +
+ ubman.log.action('Writing test data to DFU primary ' +
'altsetting')
dfu_write(alt_setting_test_file, test_f.abs_fn)
- u_boot_console.log.action('Writing dummy data to DFU secondary ' +
+ ubman.log.action('Writing dummy data to DFU secondary ' +
'altsetting to clear DFU buffers')
dfu_write(alt_setting_dummy_file, dummy_f.abs_fn)
- u_boot_console.log.action('Reading DFU primary altsetting for ' +
+ ubman.log.action('Reading DFU primary altsetting for ' +
'comparison')
dfu_read(alt_setting_test_file, readback_fn)
- u_boot_console.log.action('Comparing written and read data')
+ ubman.log.action('Comparing written and read data')
written_hash = test_f.content_hash
- read_back_hash = u_boot_utils.md5sum_file(readback_fn, size)
+ read_back_hash = utils.md5sum_file(readback_fn, size)
assert(written_hash == read_back_hash)
# This test may be executed against multiple USB ports. The test takes a
@@ -295,7 +295,7 @@
else:
sizes = []
- dummy_f = u_boot_utils.PersistentRandomFile(u_boot_console,
+ dummy_f = utils.PersistentRandomFile(ubman,
'dfu_dummy.bin', 1024)
alt_setting_test_file = env__dfu_config.get('alt_id_test_file', '0')
@@ -305,16 +305,16 @@
try:
start_dfu()
- u_boot_console.log.action(
+ ubman.log.action(
'Overwriting DFU primary altsetting with dummy data')
dfu_write(alt_setting_test_file, dummy_f.abs_fn)
for size in sizes:
- with u_boot_console.log.section('Data size %d' % size):
+ with ubman.log.section('Data size %d' % size):
dfu_write_read_check(size)
# Make the status of each sub-test obvious. If the test didn't
# pass, an exception was thrown so this code isn't executed.
- u_boot_console.log.status_pass('OK')
+ ubman.log.status_pass('OK')
ignore_cleanup_errors = False
finally:
stop_dfu(ignore_cleanup_errors)
diff --git a/test/py/tests/test_dm.py b/test/py/tests/test_dm.py
index be94971..f4c2ccd 100644
--- a/test/py/tests/test_dm.py
+++ b/test/py/tests/test_dm.py
@@ -4,15 +4,15 @@
import pytest
@pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_compat(u_boot_console):
+def test_dm_compat(ubman):
"""Test that each driver in `dm tree` is also listed in `dm compat`."""
- response = u_boot_console.run_command('dm tree')
+ response = ubman.run_command('dm tree')
driver_index = response.find('Driver')
assert driver_index != -1
drivers = (line[driver_index:].split()[0]
for line in response[:-1].split('\n')[2:])
- response = u_boot_console.run_command('dm compat')
+ response = ubman.run_command('dm compat')
bad_drivers = set()
for driver in drivers:
if not driver in response:
@@ -29,7 +29,7 @@
# checking sorting only after UCLASS_AXI_EMUL after which the names should
# be sorted.
- response = u_boot_console.run_command('dm tree -s')
+ response = ubman.run_command('dm tree -s')
lines = response.split('\n')[2:]
stack = [] # holds where we were up to at the previous indent level
prev = '' # uclass name of previous line
@@ -58,27 +58,27 @@
@pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_drivers(u_boot_console):
+def test_dm_drivers(ubman):
"""Test that each driver in `dm compat` is also listed in `dm drivers`."""
- response = u_boot_console.run_command('dm compat')
+ response = ubman.run_command('dm compat')
drivers = (line[:20].rstrip() for line in response[:-1].split('\n')[2:])
- response = u_boot_console.run_command('dm drivers')
+ response = ubman.run_command('dm drivers')
for driver in drivers:
assert driver in response
@pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_static(u_boot_console):
+def test_dm_static(ubman):
"""Test that each driver in `dm static` is also listed in `dm drivers`."""
- response = u_boot_console.run_command('dm static')
+ response = ubman.run_command('dm static')
drivers = (line[:25].rstrip() for line in response[:-1].split('\n')[2:])
- response = u_boot_console.run_command('dm drivers')
+ response = ubman.run_command('dm drivers')
for driver in drivers:
assert driver in response
@pytest.mark.buildconfigspec("cmd_dm")
-def test_dm_uclass(u_boot_console):
- response = u_boot_console.run_command("dm uclass")
+def test_dm_uclass(ubman):
+ response = ubman.run_command("dm uclass")
@pytest.mark.buildconfigspec("cmd_dm")
-def test_dm_devres(u_boot_console):
- response = u_boot_console.run_command("dm devres")
+def test_dm_devres(ubman):
+ response = ubman.run_command("dm devres")
diff --git a/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py b/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
index 1bb59d8..8800e9d 100644
--- a/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
+++ b/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
@@ -8,37 +8,37 @@
@pytest.mark.buildconfigspec('cmd_efidebug')
@pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
@pytest.mark.singlethread
-def test_efi_bootmgr(u_boot_console, efi_bootmgr_data):
+def test_efi_bootmgr(ubman, efi_bootmgr_data):
""" Unit test for UEFI bootmanager
The efidebug command is used to set up UEFI load options.
The bootefi bootmgr loads initrddump.efi as a payload.
The crc32 of the loaded initrd.img is checked
Args:
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
efi_bootmgr_data -- Path to the disk image used for testing.
"""
- u_boot_console.run_command(cmd = f'host bind 0 {efi_bootmgr_data}')
+ ubman.run_command(cmd = f'host bind 0 {efi_bootmgr_data}')
- u_boot_console.run_command(cmd = 'efidebug boot add ' \
+ ubman.run_command(cmd = 'efidebug boot add ' \
'-b 0001 label-1 host 0:1 initrddump.efi ' \
'-i host 0:1 initrd-1.img -s nocolor')
- u_boot_console.run_command(cmd = 'efidebug boot dump')
- u_boot_console.run_command(cmd = 'efidebug boot order 0001')
- u_boot_console.run_command(cmd = 'bootefi bootmgr')
- response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ ubman.run_command(cmd = 'efidebug boot dump')
+ ubman.run_command(cmd = 'efidebug boot order 0001')
+ ubman.run_command(cmd = 'bootefi bootmgr')
+ response = ubman.run_command(cmd = 'load', wait_for_echo=False)
assert 'crc32: 0x181464af' in response
- u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+ ubman.run_command(cmd = 'exit', wait_for_echo=False)
- u_boot_console.run_command(cmd = 'efidebug boot add ' \
+ ubman.run_command(cmd = 'efidebug boot add ' \
'-B 0002 label-2 host 0:1 initrddump.efi ' \
'-I host 0:1 initrd-2.img -s nocolor')
- u_boot_console.run_command(cmd = 'efidebug boot dump')
- u_boot_console.run_command(cmd = 'efidebug boot order 0002')
- u_boot_console.run_command(cmd = 'bootefi bootmgr')
- response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ ubman.run_command(cmd = 'efidebug boot dump')
+ ubman.run_command(cmd = 'efidebug boot order 0002')
+ ubman.run_command(cmd = 'bootefi bootmgr')
+ response = ubman.run_command(cmd = 'load', wait_for_echo=False)
assert 'crc32: 0x811d3515' in response
- u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+ ubman.run_command(cmd = 'exit', wait_for_echo=False)
- u_boot_console.run_command(cmd = 'efidebug boot rm 0001')
- u_boot_console.run_command(cmd = 'efidebug boot rm 0002')
+ ubman.run_command(cmd = 'efidebug boot rm 0001')
+ ubman.run_command(cmd = 'efidebug boot rm 0002')
diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py
index fc0d851..40b3fca 100644
--- a/test/py/tests/test_efi_capsule/capsule_common.py
+++ b/test/py/tests/test_efi_capsule/capsule_common.py
@@ -6,15 +6,15 @@
from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
-def capsule_setup(u_boot_console, disk_img, osindications):
+def capsule_setup(ubman, disk_img, osindications):
"""setup the test
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
disk_img -- A path to disk image to be used for testing.
osindications -- String of osindications value.
"""
- u_boot_console.run_command_list([
+ ubman.run_command_list([
f'host bind 0 {disk_img}',
'printenv -e PlatformLangCodes', # workaround for terminal size determination
'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
@@ -23,22 +23,22 @@
'u-boot-env raw 0x150000 0x200000"'])
if osindications is None:
- u_boot_console.run_command('env set -e OsIndications')
+ ubman.run_command('env set -e OsIndications')
else:
- u_boot_console.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}')
+ ubman.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}')
- u_boot_console.run_command('env save')
+ ubman.run_command('env save')
-def init_content(u_boot_console, target, filename, expected):
+def init_content(ubman, target, filename, expected):
"""initialize test content
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
target -- Target address to place the content.
filename -- File name of the content.
expected -- Expected string of the content.
"""
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'sf probe 0:0',
f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{filename}',
f'sf write 4000000 {target} 10',
@@ -46,34 +46,34 @@
'md.b 5000000 10'])
assert expected in ''.join(output)
-def place_capsule_file(u_boot_console, filenames):
+def place_capsule_file(ubman, filenames):
"""place the capsule file
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
filenames -- File name array of the target capsule files.
"""
for name in filenames:
- u_boot_console.run_command_list([
+ ubman.run_command_list([
f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{name}',
f'fatwrite host 0:1 4000000 {CAPSULE_INSTALL_DIR}/{name} $filesize'])
- output = u_boot_console.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}')
+ output = ubman.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}')
for name in filenames:
assert name in ''.join(output)
-def exec_manual_update(u_boot_console, disk_img, filenames, need_reboot = True):
+def exec_manual_update(ubman, disk_img, filenames, need_reboot = True):
"""execute capsule update manually
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
disk_img -- A path to disk image to be used for testing.
filenames -- File name array of the target capsule files.
need_reboot -- Flag indicates whether system reboot is required.
"""
# make sure that dfu_alt_info exists even persistent variables
# are not available.
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'env set dfu_alt_info '
'"sf 0:0=u-boot-bin raw 0x100000 0x50000;'
'u-boot-env raw 0x150000 0x200000"',
@@ -83,60 +83,60 @@
assert name in ''.join(output)
# need to run uefi command to initiate capsule handling
- u_boot_console.run_command(
+ ubman.run_command(
'env print -e Capsule0000', wait_for_reboot = need_reboot)
-def check_file_removed(u_boot_console, disk_img, filenames):
+def check_file_removed(ubman, disk_img, filenames):
"""check files are removed
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
disk_img -- A path to disk image to be used for testing.
filenames -- File name array of the target capsule files.
"""
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
f'host bind 0 {disk_img}',
f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
for name in filenames:
assert name not in ''.join(output)
-def check_file_exist(u_boot_console, disk_img, filenames):
+def check_file_exist(ubman, disk_img, filenames):
"""check files exist
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
disk_img -- A path to disk image to be used for testing.
filenames -- File name array of the target capsule files.
"""
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
f'host bind 0 {disk_img}',
f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
for name in filenames:
assert name in ''.join(output)
-def verify_content(u_boot_console, target, expected):
+def verify_content(ubman, target, expected):
"""verify the content
Args:
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
target -- Target address to verify.
expected -- Expected string of the content.
"""
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'sf probe 0:0',
f'sf read 4000000 {target} 10',
'md.b 4000000 10'])
assert expected in ''.join(output)
-def do_reboot_dtb_specified(u_boot_config, u_boot_console, dtb_filename):
+def do_reboot_dtb_specified(u_boot_config, ubman, dtb_filename):
"""do reboot with specified DTB
Args:
u_boot_config -- U-boot configuration.
- u_boot_console -- A console connection to U-Boot.
+ ubman -- A console connection to U-Boot.
dtb_filename -- DTB file name.
"""
mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
- u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+ ubman.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+ f'/{dtb_filename}'
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
index a726c71..0162745 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
@@ -33,7 +33,7 @@
"""
def test_efi_capsule_fw1(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 1
Update U-Boot and U-Boot environment on SPI Flash
but with an incorrect GUID value in the capsule
@@ -44,34 +44,34 @@
# other tests might have run and the
# system might not be in a clean state.
# Restart before starting the tests.
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_capsule_data
capsule_files = ['Test05']
- with u_boot_console.log.section('Test Case 1-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 1-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
# reboot
- u_boot_console.restart_uboot(expect_reset = capsule_early)
+ ubman.restart_uboot(expect_reset = capsule_early)
- with u_boot_console.log.section('Test Case 1-b, after reboot'):
+ with ubman.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted anyway
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:Old')
- verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
+ verify_content(ubman, '150000', 'u-boot-env:Old')
def test_efi_capsule_fw2(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 2
Update U-Boot and U-Boot environment on SPI Flash
0x100000-0x150000: U-Boot binary (but dummy)
@@ -80,11 +80,11 @@
disk_img = efi_capsule_data
capsule_files = ['Test04']
- with u_boot_console.log.section('Test Case 2-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 2-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
@@ -92,22 +92,22 @@
'config_efi_capsule_authenticate')
# reboot
- u_boot_console.restart_uboot(expect_reset = capsule_early)
+ ubman.restart_uboot(expect_reset = capsule_early)
- with u_boot_console.log.section('Test Case 2-b, after reboot'):
+ with ubman.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
- verify_content(u_boot_console, '100000', expected)
+ verify_content(ubman, '100000', expected)
expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
- verify_content(u_boot_console, '150000', expected)
+ verify_content(ubman, '150000', expected)
def test_efi_capsule_fw3(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 3
Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
0x100000-0x150000: U-Boot binary (but dummy)
@@ -115,47 +115,47 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test104']
- with u_boot_console.log.section('Test Case 3-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 3-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
# reboot
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
capsule_auth = u_boot_config.buildconfig.get(
'config_efi_capsule_authenticate')
- with u_boot_console.log.section('Test Case 3-b, after reboot'):
+ with ubman.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted anyway
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
# make sure the dfu_alt_info exists because it is required for making ESRT.
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
'u-boot-env raw 0x150000 0x200000"',
'efidebug capsule esrt'])
if capsule_auth:
# capsule authentication failed
- verify_content(u_boot_console, '100000', 'u-boot:Old')
- verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
+ verify_content(ubman, '150000', 'u-boot-env:Old')
else:
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
assert 'ESRT: fw_version=5' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
- verify_content(u_boot_console, '100000', 'u-boot:New')
- verify_content(u_boot_console, '150000', 'u-boot-env:New')
+ verify_content(ubman, '100000', 'u-boot:New')
+ verify_content(ubman, '150000', 'u-boot-env:New')
def test_efi_capsule_fw4(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 4
Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
but fw_version is lower than lowest_supported_version
@@ -164,20 +164,20 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test105']
- with u_boot_console.log.section('Test Case 4-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 4-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
# reboot
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ with ubman.log.section('Test Case 4-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
index 8a790405..b8cb483 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
@@ -34,7 +34,7 @@
"""
def test_efi_capsule_fw1(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 1
Update U-Boot and U-Boot environment on SPI Flash
but with an incorrect GUID value in the capsule
@@ -46,34 +46,34 @@
# other tests might have run and the
# system might not be in a clean state.
# Restart before starting the tests.
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_capsule_data
capsule_files = ['Test03']
- with u_boot_console.log.section('Test Case 1-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 1-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
# reboot
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 1-b, after reboot'):
+ with ubman.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted anyway
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:Old')
- verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
+ verify_content(ubman, '150000', 'u-boot-env:Old')
def test_efi_capsule_fw2(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 2
Update U-Boot and U-Boot environment on SPI Flash but with OsIndications unset
No update should happen unless CONFIG_EFI_IGNORE_OSINDICATIONS is set
@@ -82,14 +82,14 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test01', 'Test02']
- with u_boot_console.log.section('Test Case 2-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, None)
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 2-a, before reboot'):
+ capsule_setup(ubman, disk_img, None)
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
# reboot
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
ignore_os_indications = u_boot_config.buildconfig.get(
'config_efi_ignore_osindications')
@@ -100,32 +100,32 @@
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 2-b, after reboot'):
+ with ubman.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files, need_reboot)
+ exec_manual_update(ubman, disk_img, capsule_files, need_reboot)
if not ignore_os_indications:
- check_file_exist(u_boot_console, disk_img, capsule_files)
+ check_file_exist(ubman, disk_img, capsule_files)
expected = 'u-boot:New' if (ignore_os_indications and not capsule_auth) else 'u-boot:Old'
- verify_content(u_boot_console, '100000', expected)
+ verify_content(ubman, '100000', expected)
expected = 'u-boot-env:New' if (ignore_os_indications and not capsule_auth) else 'u-boot-env:Old'
- verify_content(u_boot_console, '150000', expected)
+ verify_content(ubman, '150000', expected)
def test_efi_capsule_fw3(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 3
Update U-Boot on SPI Flash, raw image format
0x100000-0x150000: U-Boot binary (but dummy)
"""
disk_img = efi_capsule_data
capsule_files = ['Test01', 'Test02']
- with u_boot_console.log.section('Test Case 3-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 3-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
@@ -133,14 +133,14 @@
'config_efi_capsule_authenticate')
# reboot
- u_boot_console.restart_uboot(expect_reset = capsule_early)
+ ubman.restart_uboot(expect_reset = capsule_early)
- with u_boot_console.log.section('Test Case 3-b, after reboot'):
+ with ubman.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# make sure the dfu_alt_info exists because it is required for making ESRT.
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
'efidebug capsule esrt'])
@@ -150,16 +150,16 @@
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
- verify_content(u_boot_console, '100000', expected)
+ verify_content(ubman, '100000', expected)
expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
- verify_content(u_boot_console, '150000', expected)
+ verify_content(ubman, '150000', expected)
def test_efi_capsule_fw4(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 4
Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
0x100000-0x150000: U-Boot binary (but dummy)
@@ -167,36 +167,36 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test101', 'Test102']
- with u_boot_console.log.section('Test Case 4-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 4-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
# reboot
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
capsule_auth = u_boot_config.buildconfig.get(
'config_efi_capsule_authenticate')
- with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ with ubman.log.section('Test Case 4-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted anyway
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
# make sure the dfu_alt_info exists because it is required for making ESRT.
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000'
'u-boot-env raw 0x150000 0x200000"',
'efidebug capsule esrt'])
if capsule_auth:
# capsule authentication failed
- verify_content(u_boot_console, '100000', 'u-boot:Old')
- verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
+ verify_content(ubman, '150000', 'u-boot-env:Old')
else:
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
@@ -208,11 +208,11 @@
assert 'ESRT: fw_version=10' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
- verify_content(u_boot_console, '100000', 'u-boot:New')
- verify_content(u_boot_console, '150000', 'u-boot-env:New')
+ verify_content(ubman, '100000', 'u-boot:New')
+ verify_content(ubman, '150000', 'u-boot-env:New')
def test_efi_capsule_fw5(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
""" Test Case 5
Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
but fw_version is lower than lowest_supported_version
@@ -221,20 +221,20 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test103']
- with u_boot_console.log.section('Test Case 5-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 5-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
# reboot
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 5-b, after reboot'):
+ with ubman.log.section('Test Case 5-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
index debbce8..29545c5 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
@@ -36,7 +36,7 @@
"""
def test_efi_capsule_auth1(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 1
Update U-Boot on SPI Flash, FIT image format
x150000: U-Boot binary (but dummy)
@@ -46,25 +46,25 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test13']
- with u_boot_console.log.section('Test Case 1-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 1-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 1-b, after reboot'):
+ with ubman.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:New')
+ verify_content(ubman, '100000', 'u-boot:New')
def test_efi_capsule_auth2(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 2
Update U-Boot on SPI Flash, FIT image format
0x100000-0x150000: U-Boot binary (but dummy)
@@ -75,28 +75,28 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test14']
- with u_boot_console.log.section('Test Case 2-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 2-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 2-b, after reboot'):
+ with ubman.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted any way
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
def test_efi_capsule_auth3(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 3
Update U-Boot on SPI Flash, FIT image format
0x100000-0x150000: U-Boot binary (but dummy)
@@ -106,28 +106,28 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test02']
- with u_boot_console.log.section('Test Case 3-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 3-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 3-b, after reboot'):
+ with ubman.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted any way
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
def test_efi_capsule_auth4(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
0x100000-0x150000: U-Boot binary (but dummy)
@@ -136,22 +136,22 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test114']
- with u_boot_console.log.section('Test Case 4-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 4-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ with ubman.log.section('Test Case 4-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
'u-boot-env raw 0x150000 0x200000"',
'efidebug capsule esrt'])
@@ -161,11 +161,11 @@
assert 'ESRT: fw_version=5' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
- verify_content(u_boot_console, '100000', 'u-boot:New')
- verify_content(u_boot_console, '150000', 'u-boot-env:New')
+ verify_content(ubman, '100000', 'u-boot:New')
+ verify_content(ubman, '150000', 'u-boot-env:New')
def test_efi_capsule_auth5(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
0x100000-0x150000: U-Boot binary (but dummy)
@@ -175,19 +175,19 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test115']
- with u_boot_console.log.section('Test Case 5-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 5-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 5-b, after reboot'):
+ with ubman.log.section('Test Case 5-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
index 439bd71..a500c49 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
@@ -34,7 +34,7 @@
"""
def test_efi_capsule_auth1(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 1 - Update U-Boot on SPI Flash, raw image format
0x100000-0x150000: U-Boot binary (but dummy)
@@ -43,25 +43,25 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test11']
- with u_boot_console.log.section('Test Case 1-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 1-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 1-b, after reboot'):
+ with ubman.log.section('Test Case 1-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:New')
+ verify_content(ubman, '100000', 'u-boot:New')
def test_efi_capsule_auth2(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 2 - Update U-Boot on SPI Flash, raw image format
0x100000-0x150000: U-Boot binary (but dummy)
@@ -71,27 +71,27 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test12']
- with u_boot_console.log.section('Test Case 2-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 2-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 2-b, after reboot'):
+ with ubman.log.section('Test Case 2-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
def test_efi_capsule_auth3(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 3 - Update U-Boot on SPI Flash, raw image format
0x100000-0x150000: U-Boot binary (but dummy)
@@ -100,28 +100,28 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test02']
- with u_boot_console.log.section('Test Case 3-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 3-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 3-b, after reboot'):
+ with ubman.log.section('Test Case 3-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
# deleted anyway
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
# TODO: check CapsuleStatus in CapsuleXXXX
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
def test_efi_capsule_auth4(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
0x100000-0x150000: U-Boot binary (but dummy)
@@ -130,22 +130,22 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test111', 'Test112']
- with u_boot_console.log.section('Test Case 4-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 4-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 4-b, after reboot'):
+ with ubman.log.section('Test Case 4-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
'u-boot-env raw 0x150000 0x200000"',
'efidebug capsule esrt'])
@@ -160,11 +160,11 @@
assert 'ESRT: fw_version=10' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
- verify_content(u_boot_console, '100000', 'u-boot:New')
- verify_content(u_boot_console, '150000', 'u-boot-env:New')
+ verify_content(ubman, '100000', 'u-boot:New')
+ verify_content(ubman, '150000', 'u-boot-env:New')
def test_efi_capsule_auth5(
- self, u_boot_config, u_boot_console, efi_capsule_data):
+ self, u_boot_config, ubman, efi_capsule_data):
"""Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
0x100000-0x150000: U-Boot binary (but dummy)
@@ -174,19 +174,19 @@
"""
disk_img = efi_capsule_data
capsule_files = ['Test113']
- with u_boot_console.log.section('Test Case 5-a, before reboot'):
- capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
- init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
- place_capsule_file(u_boot_console, capsule_files)
+ with ubman.log.section('Test Case 5-a, before reboot'):
+ capsule_setup(ubman, disk_img, '0x0000000000000004')
+ init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+ place_capsule_file(ubman, capsule_files)
- do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+ do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
capsule_early = u_boot_config.buildconfig.get(
'config_efi_capsule_on_disk_early')
- with u_boot_console.log.section('Test Case 5-b, after reboot'):
+ with ubman.log.section('Test Case 5-b, after reboot'):
if not capsule_early:
- exec_manual_update(u_boot_console, disk_img, capsule_files)
+ exec_manual_update(ubman, disk_img, capsule_files)
- check_file_removed(u_boot_console, disk_img, capsule_files)
+ check_file_removed(ubman, disk_img, capsule_files)
- verify_content(u_boot_console, '100000', 'u-boot:Old')
+ verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py
index 550058a..5f352e7 100644
--- a/test/py/tests/test_efi_fit.py
+++ b/test/py/tests/test_efi_fit.py
@@ -55,7 +55,7 @@
import os.path
import pytest
-import u_boot_utils as util
+import utils
# Define the parametrized ITS data to be used for FIT images generation.
ITS_DATA = '''
@@ -123,7 +123,7 @@
@pytest.mark.buildconfigspec('fit')
@pytest.mark.notbuildconfigspec('generate_acpi_table')
@pytest.mark.requiredtool('dtc')
-def test_efi_fit_launch(u_boot_console):
+def test_efi_fit_launch(ubman):
"""Test handling of UEFI binaries inside FIT images.
The tests are trying to launch U-Boot's helloworld.efi embedded into
@@ -148,13 +148,13 @@
at the beginning of this file.
"""
- init_usb = cons.config.env.get('env__net_uses_usb', False)
+ init_usb = ubman.config.env.get('env__net_uses_usb', False)
if init_usb:
- cons.run_command('usb start')
+ ubman.run_command('usb start')
- init_pci = cons.config.env.get('env__net_uses_pci', False)
+ init_pci = ubman.config.env.get('env__net_uses_pci', False)
if init_pci:
- cons.run_command('pci enum')
+ ubman.run_command('pci enum')
def net_dhcp():
"""Execute the dhcp command.
@@ -163,18 +163,18 @@
comment at the beginning of this file.
"""
- has_dhcp = cons.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
+ has_dhcp = ubman.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
if not has_dhcp:
- cons.log.warning('CONFIG_CMD_DHCP != y: Skipping DHCP network setup')
+ ubman.log.warning('CONFIG_CMD_DHCP != y: Skipping DHCP network setup')
return False
- test_dhcp = cons.config.env.get('env__net_dhcp_server', False)
+ test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
if not test_dhcp:
- cons.log.info('No DHCP server available')
+ ubman.log.info('No DHCP server available')
return False
- cons.run_command('setenv autoload no')
- output = cons.run_command('dhcp')
+ ubman.run_command('setenv autoload no')
+ output = ubman.run_command('dhcp')
assert 'DHCP client bound to address ' in output
return True
@@ -185,18 +185,18 @@
the beginning of this file.
"""
- has_dhcp = cons.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
+ has_dhcp = ubman.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
if not has_dhcp:
- cons.log.warning('CONFIG_NET != y: Skipping static network setup')
+ ubman.log.warning('CONFIG_NET != y: Skipping static network setup')
return False
- env_vars = cons.config.env.get('env__net_static_env_vars', None)
+ env_vars = ubman.config.env.get('env__net_static_env_vars', None)
if not env_vars:
- cons.log.info('No static network configuration is defined')
+ ubman.log.info('No static network configuration is defined')
return False
for (var, val) in env_vars:
- cons.run_command('setenv %s %s' % (var, val))
+ ubman.run_command('setenv %s %s' % (var, val))
return True
def make_fpath(file_name):
@@ -208,7 +208,7 @@
The computed file path.
"""
- return os.path.join(cons.config.build_dir, file_name)
+ return os.path.join(ubman.config.build_dir, file_name)
def make_efi(fname, comp):
"""Create an UEFI binary.
@@ -224,11 +224,11 @@
"""
bin_path = make_fpath(fname)
- util.run_and_log(cons,
- ['cp', make_fpath('lib/efi_loader/helloworld.efi'),
- bin_path])
+ utils.run_and_log(ubman,
+ ['cp', make_fpath('lib/efi_loader/helloworld.efi'),
+ bin_path])
if comp:
- util.run_and_log(cons, ['gzip', '-f', bin_path])
+ utils.run_and_log(ubman, ['gzip', '-f', bin_path])
bin_path += '.gz'
return bin_path
@@ -257,9 +257,10 @@
# Build the test FDT.
dtb = make_fpath('test-efi-fit-%s.dtb' % fdt_type)
- util.run_and_log(cons, ['dtc', '-I', 'dts', '-O', 'dtb', '-o', dtb, dts])
+ utils.run_and_log(ubman,
+ ['dtc', '-I', 'dts', '-O', 'dtb', '-o', dtb, dts])
if comp:
- util.run_and_log(cons, ['gzip', '-f', dtb])
+ utils.run_and_log(ubman, ['gzip', '-f', dtb])
dtb += '.gz'
return dtb
@@ -290,8 +291,8 @@
# Build the test ITS.
fit_path = make_fpath('test-efi-fit-helloworld.fit')
- util.run_and_log(
- cons, [make_fpath('tools/mkimage'), '-f', its_path, fit_path])
+ utils.run_and_log(
+ ubman, [make_fpath('tools/mkimage'), '-f', its_path, fit_path])
return fit_path
def load_fit_from_host(fit):
@@ -307,9 +308,9 @@
addr = fit.get('addr', None)
if not addr:
- addr = util.find_ram_base(cons)
+ addr = utils.find_ram_base(ubman)
- output = cons.run_command(
+ output = ubman.run_command(
'host load hostfs - %x %s/%s' % (addr, fit['dn'], fit['fn']))
expected_text = ' bytes read'
size = fit.get('size', None)
@@ -334,10 +335,10 @@
addr = fit.get('addr', None)
if not addr:
- addr = util.find_ram_base(cons)
+ addr = utils.find_ram_base(ubman)
file_name = fit['fn']
- output = cons.run_command('tftpboot %x %s' % (addr, file_name))
+ output = ubman.run_command('tftpboot %x %s' % (addr, file_name))
expected_text = 'Bytes transferred = '
size = fit.get('size', None)
if size:
@@ -348,10 +349,10 @@
if not expected_crc:
return addr
- if cons.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
return addr
- output = cons.run_command('crc32 $fileaddr $filesize')
+ output = ubman.run_command('crc32 $fileaddr $filesize')
assert expected_crc in output
return addr
@@ -383,10 +384,10 @@
generated content.
"""
- with cons.log.section('FDT=%s;COMP=%s' % (enable_fdt, enable_comp)):
+ with ubman.log.section('FDT=%s;COMP=%s' % (enable_fdt, enable_comp)):
if is_sandbox:
fit = {
- 'dn': cons.config.build_dir,
+ 'dn': ubman.config.build_dir,
}
else:
# Init networking.
@@ -396,7 +397,7 @@
if not net_set_up:
pytest.skip('Network not initialized')
- fit = cons.config.env.get('env__efi_fit_tftp_file', None)
+ fit = ubman.config.env.get('env__efi_fit_tftp_file', None)
if not fit:
pytest.skip('No env__efi_fit_tftp_file binary specified in environment')
@@ -411,8 +412,9 @@
fit['size'] = os.path.getsize(fit_path)
# Copy image to TFTP root directory.
- if fit['dn'] != cons.config.build_dir:
- util.run_and_log(cons, ['mv', '-f', fit_path, '%s/' % fit['dn']])
+ if fit['dn'] != ubman.config.build_dir:
+ utils.run_and_log(ubman,
+ ['mv', '-f', fit_path, '%s/' % fit['dn']])
# Load FIT image.
addr = load_fit_from_host(fit) if is_sandbox else load_fit_from_tftp(fit)
@@ -421,31 +423,30 @@
fit_config = 'config-efi-fdt' if enable_fdt else 'config-efi-nofdt'
# Try booting.
- output = cons.run_command('bootm %x#%s' % (addr, fit_config))
+ output = ubman.run_command('bootm %x#%s' % (addr, fit_config))
if enable_fdt:
assert 'Booting using the fdt blob' in output
assert 'Hello, world' in output
assert '## Application failed' not in output
- cons.restart_uboot()
+ ubman.restart_uboot()
- cons = u_boot_console
# Array slice removes leading/trailing quotes.
- sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
+ sys_arch = ubman.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
if sys_arch == 'arm':
- arm64 = cons.config.buildconfig.get('config_arm64')
+ arm64 = ubman.config.buildconfig.get('config_arm64')
if arm64:
sys_arch = 'arm64'
is_sandbox = sys_arch == 'sandbox'
if is_sandbox:
- old_dtb = cons.config.dtb
+ old_dtb = ubman.config.dtb
try:
if is_sandbox:
# Use our own device tree file, will be restored afterwards.
control_dtb = make_dtb('internal', False)
- cons.config.dtb = control_dtb
+ ubman.config.dtb = control_dtb
# Run tests
# - fdt OFF, gzip OFF
@@ -462,5 +463,5 @@
finally:
if is_sandbox:
# Go back to the original U-Boot with the correct dtb.
- cons.config.dtb = old_dtb
- cons.restart_uboot()
+ ubman.config.dtb = old_dtb
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index 3343493..58f2655 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -53,71 +53,71 @@
"""
import pytest
-import u_boot_utils
+import utils
PROTO_TFTP, PROTO_HTTP = range(0, 2)
net_set_up = False
-def test_efi_pre_commands(u_boot_console):
+def test_efi_pre_commands(ubman):
"""Execute any commands required to enable network hardware.
These commands are provided by the boardenv_* file; see the comment at the
beginning of this file.
"""
- init_usb = u_boot_console.config.env.get('env__net_uses_usb', False)
+ init_usb = ubman.config.env.get('env__net_uses_usb', False)
if init_usb:
- u_boot_console.run_command('usb start')
+ ubman.run_command('usb start')
- init_pci = u_boot_console.config.env.get('env__net_uses_pci', False)
+ init_pci = ubman.config.env.get('env__net_uses_pci', False)
if init_pci:
- u_boot_console.run_command('pci enum')
+ ubman.run_command('pci enum')
@pytest.mark.buildconfigspec('cmd_dhcp')
-def test_efi_setup_dhcp(u_boot_console):
+def test_efi_setup_dhcp(ubman):
"""Set up the network using DHCP.
The boardenv_* file may be used to enable/disable this test; see the
comment at the beginning of this file.
"""
- test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+ test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
if not test_dhcp:
- env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+ env_vars = ubman.config.env.get('env__net_static_env_vars', None)
if not env_vars:
pytest.skip('No DHCP server available')
return
- u_boot_console.run_command('setenv autoload no')
- output = u_boot_console.run_command('dhcp')
+ ubman.run_command('setenv autoload no')
+ output = ubman.run_command('dhcp')
assert 'DHCP client bound to address ' in output
global net_set_up
net_set_up = True
@pytest.mark.buildconfigspec('net')
-def test_efi_setup_static(u_boot_console):
+def test_efi_setup_static(ubman):
"""Set up the network using a static IP configuration.
The configuration is provided by the boardenv_* file; see the comment at
the beginning of this file.
"""
- env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+ env_vars = ubman.config.env.get('env__net_static_env_vars', None)
if not env_vars:
- test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+ test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
if not test_dhcp:
pytest.skip('No static network configuration is defined')
return None
for (var, val) in env_vars:
- u_boot_console.run_command('setenv %s %s' % (var, val))
+ ubman.run_command('setenv %s %s' % (var, val))
global net_set_up
net_set_up = True
-def fetch_file(u_boot_console, env_conf, proto):
+def fetch_file(ubman, env_conf, proto):
"""Grab an env described file via TFTP or HTTP and return its address
A file as described by an env config <env_conf> is downloaded from the
@@ -126,13 +126,13 @@
if not net_set_up:
pytest.skip('Network not initialized')
- f = u_boot_console.config.env.get(env_conf, None)
+ f = ubman.config.env.get(env_conf, None)
if not f:
pytest.skip('No %s binary specified in environment' % env_conf)
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
fn = f['fn']
if proto == PROTO_TFTP:
@@ -141,7 +141,7 @@
cmd = 'wget'
else:
assert False
- output = u_boot_console.run_command('%s %x %s' % (cmd, addr, fn))
+ output = ubman.run_command('%s %x %s' % (cmd, addr, fn))
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
if sz:
@@ -152,18 +152,18 @@
if not expected_crc:
return addr
- if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
return addr
- output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+ output = ubman.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
return addr
-def do_test_efi_helloworld_net(u_boot_console, proto):
- addr = fetch_file(u_boot_console, 'env__efi_loader_helloworld_file', proto)
+def do_test_efi_helloworld_net(ubman, proto):
+ addr = fetch_file(ubman, 'env__efi_loader_helloworld_file', proto)
- output = u_boot_console.run_command('bootefi %x' % addr)
+ output = ubman.run_command('bootefi %x' % addr)
expected_text = 'Hello, world'
assert expected_text in output
expected_text = '## Application failed'
@@ -172,65 +172,65 @@
@pytest.mark.buildconfigspec('of_control')
@pytest.mark.buildconfigspec('bootefi_hello_compile')
@pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_efi_helloworld_net_tftp(u_boot_console):
+def test_efi_helloworld_net_tftp(ubman):
"""Run the helloworld.efi binary via TFTP.
The helloworld.efi file is downloaded from the TFTP server and is executed
using the fallback device tree at $fdtcontroladdr.
"""
- do_test_efi_helloworld_net(u_boot_console, PROTO_TFTP);
+ do_test_efi_helloworld_net(ubman, PROTO_TFTP);
@pytest.mark.buildconfigspec('of_control')
@pytest.mark.buildconfigspec('bootefi_hello_compile')
@pytest.mark.buildconfigspec('cmd_wget')
-def test_efi_helloworld_net_http(u_boot_console):
+def test_efi_helloworld_net_http(ubman):
"""Run the helloworld.efi binary via HTTP.
The helloworld.efi file is downloaded from the HTTP server and is executed
using the fallback device tree at $fdtcontroladdr.
"""
- if u_boot_console.config.env.get('env__efi_helloworld_net_http_test_skip', True):
+ if ubman.config.env.get('env__efi_helloworld_net_http_test_skip', True):
pytest.skip('helloworld.efi HTTP test is not enabled!')
- do_test_efi_helloworld_net(u_boot_console, PROTO_HTTP);
+ do_test_efi_helloworld_net(ubman, PROTO_HTTP);
@pytest.mark.buildconfigspec('cmd_bootefi_hello')
-def test_efi_helloworld_builtin(u_boot_console):
+def test_efi_helloworld_builtin(ubman):
"""Run the builtin helloworld.efi binary.
The helloworld.efi file is included in U-Boot, execute it using the
special "bootefi hello" command.
"""
- output = u_boot_console.run_command('bootefi hello')
+ output = ubman.run_command('bootefi hello')
expected_text = 'Hello, world'
assert expected_text in output
@pytest.mark.buildconfigspec('of_control')
@pytest.mark.buildconfigspec('cmd_bootefi')
@pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_efi_grub_net(u_boot_console):
+def test_efi_grub_net(ubman):
"""Run the grub.efi binary via TFTP.
The grub.efi file is downloaded from the TFTP server and gets
executed.
"""
- addr = fetch_file(u_boot_console, 'env__efi_loader_grub_file', PROTO_TFTP)
+ addr = fetch_file(ubman, 'env__efi_loader_grub_file', PROTO_TFTP)
- u_boot_console.run_command('bootefi %x' % addr, wait_for_prompt=False)
+ ubman.run_command('bootefi %x' % addr, wait_for_prompt=False)
# Verify that we have an SMBIOS table
- check_smbios = u_boot_console.config.env.get('env__efi_loader_check_smbios', False)
+ check_smbios = ubman.config.env.get('env__efi_loader_check_smbios', False)
if check_smbios:
- u_boot_console.wait_for('grub>')
- u_boot_console.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
- u_boot_console.wait_for('SMBIOS')
+ ubman.wait_for('grub>')
+ ubman.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
+ ubman.wait_for('SMBIOS')
# Then exit cleanly
- u_boot_console.wait_for('grub>')
- u_boot_console.run_command('exit', wait_for_prompt=False, wait_for_echo=False)
- u_boot_console.wait_for(u_boot_console.prompt)
+ ubman.wait_for('grub>')
+ ubman.run_command('exit', wait_for_prompt=False, wait_for_echo=False)
+ ubman.wait_for(ubman.prompt)
# And give us our U-Boot prompt back
- u_boot_console.run_command('')
+ ubman.run_command('')
diff --git a/test/py/tests/test_efi_secboot/test_authvar.py b/test/py/tests/test_efi_secboot/test_authvar.py
index d5aeb65..7b45f8f 100644
--- a/test/py/tests/test_efi_secboot/test_authvar.py
+++ b/test/py/tests/test_efi_secboot/test_authvar.py
@@ -17,119 +17,119 @@
@pytest.mark.buildconfigspec('cmd_nvedit_efi')
@pytest.mark.slow
class TestEfiAuthVar(object):
- def test_efi_var_auth1(self, u_boot_console, efi_boot_env):
+ def test_efi_var_auth1(self, ubman, efi_boot_env):
"""
Test Case 1 - Install signature database
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 1a'):
+ with ubman.log.section('Test Case 1a'):
# Test Case 1a, Initial secure state
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'printenv -e SecureBoot'])
assert '00000000: 00' in ''.join(output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SetupMode')
assert '00000000: 01' in output
- with u_boot_console.log.section('Test Case 1b'):
+ with ubman.log.section('Test Case 1b'):
# Test Case 1b, PK without AUTHENTICATED_WRITE_ACCESS
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' in ''.join(output)
- with u_boot_console.log.section('Test Case 1c'):
+ with ubman.log.section('Test Case 1c'):
# Test Case 1c, install PK
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
'printenv -e -n PK'])
assert 'PK:' in ''.join(output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SecureBoot')
assert '00000000: 01' in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SetupMode')
assert '00000000: 00' in output
- with u_boot_console.log.section('Test Case 1d'):
+ with ubman.log.section('Test Case 1d'):
# Test Case 1d, db/dbx without KEK
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' in ''.join(output)
- with u_boot_console.log.section('Test Case 1e'):
+ with ubman.log.section('Test Case 1e'):
# Test Case 1e, install KEK
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -i 4000000:$filesize KEK'])
assert 'Failed to set EFI variable' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
'printenv -e -n KEK'])
assert 'KEK:' in ''.join(output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SecureBoot')
assert '00000000: 01' in output
- with u_boot_console.log.section('Test Case 1f'):
+ with ubman.log.section('Test Case 1f'):
# Test Case 1f, install db
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'db:' in ''.join(output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SecureBoot')
assert '00000000: 01' in output
- with u_boot_console.log.section('Test Case 1g'):
+ with ubman.log.section('Test Case 1g'):
# Test Case 1g, install dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 dbx.auth',
'setenv -e -nv -bs -rt -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 dbx.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'dbx:' in ''.join(output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SecureBoot')
assert '00000000: 01' in output
- def test_efi_var_auth2(self, u_boot_console, efi_boot_env):
+ def test_efi_var_auth2(self, ubman, efi_boot_env):
"""
Test Case 2 - Update database by overwriting
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 2a'):
+ with ubman.log.section('Test Case 2a'):
# Test Case 2a, update without AUTHENTICATED_WRITE_ACCESS
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -141,36 +141,36 @@
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'db:' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db1.auth',
'setenv -e -nv -bs -rt -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
- with u_boot_console.log.section('Test Case 2b'):
+ with ubman.log.section('Test Case 2b'):
# Test Case 2b, update without correct signature
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.esl',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
- with u_boot_console.log.section('Test Case 2c'):
+ with ubman.log.section('Test Case 2c'):
# Test Case 2c, update with correct signature
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db1.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'db:' in ''.join(output)
- def test_efi_var_auth3(self, u_boot_console, efi_boot_env):
+ def test_efi_var_auth3(self, ubman, efi_boot_env):
"""
Test Case 3 - Append database
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 3a'):
+ with ubman.log.section('Test Case 3a'):
# Test Case 3a, update without AUTHENTICATED_WRITE_ACCESS
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -182,36 +182,36 @@
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'db:' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
- with u_boot_console.log.section('Test Case 3b'):
+ with ubman.log.section('Test Case 3b'):
# Test Case 3b, update without correct signature
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.esl',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' in ''.join(output)
- with u_boot_console.log.section('Test Case 3c'):
+ with ubman.log.section('Test Case 3c'):
# Test Case 3c, update with correct signature
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'db:' in ''.join(output)
- def test_efi_var_auth4(self, u_boot_console, efi_boot_env):
+ def test_efi_var_auth4(self, ubman, efi_boot_env):
"""
Test Case 4 - Delete database without authentication
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 4a'):
+ with ubman.log.section('Test Case 4a'):
# Test Case 4a, update without AUTHENTICATED_WRITE_ACCESS
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -223,29 +223,29 @@
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'db:' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'setenv -e -nv -bs -rt db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
assert 'Failed to set EFI variable' in ''.join(output)
assert 'db:' in ''.join(output)
- with u_boot_console.log.section('Test Case 4b'):
+ with ubman.log.section('Test Case 4b'):
# Test Case 4b, update without correct signature/data
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'setenv -e -nv -bs -rt -at db',
'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
assert 'Failed to set EFI variable' in ''.join(output)
assert 'db:' in ''.join(output)
- def test_efi_var_auth5(self, u_boot_console, efi_boot_env):
+ def test_efi_var_auth5(self, ubman, efi_boot_env):
"""
Test Case 5 - Uninstall(delete) PK
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 5a'):
+ with ubman.log.section('Test Case 5a'):
# Test Case 5a, Uninstall PK without correct signature
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -257,25 +257,25 @@
assert 'Failed to set EFI variable' not in ''.join(output)
assert 'PK:' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 PK_null.esl',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
'printenv -e -n PK'])
assert 'Failed to set EFI variable' in ''.join(output)
assert 'PK:' in ''.join(output)
- with u_boot_console.log.section('Test Case 5b'):
+ with ubman.log.section('Test Case 5b'):
# Test Case 5b, Uninstall PK with correct signature
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 PK_null.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
'printenv -e -n PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
assert '\"PK\" not defined' in ''.join(output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SecureBoot')
assert '00000000: 00' in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'printenv -e SetupMode')
assert '00000000: 01' in output
diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py
index f604138..e8aaef7 100644
--- a/test/py/tests/test_efi_secboot/test_signed.py
+++ b/test/py/tests/test_efi_secboot/test_signed.py
@@ -18,83 +18,83 @@
@pytest.mark.buildconfigspec('cmd_nvedit_efi')
@pytest.mark.slow
class TestEfiSignedImage(object):
- def test_efi_signed_image_auth1(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth1(self, ubman, efi_boot_env):
"""
Test Case 1 - Secure boot is not in force
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 1a'):
+ with ubman.log.section('Test Case 1a'):
# Test Case 1a, run signed image if no PK
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
- with u_boot_console.log.section('Test Case 1b'):
+ with ubman.log.section('Test Case 1b'):
# Test Case 1b, run unsigned image if no PK
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
'efidebug boot order 2',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
- def test_efi_signed_image_auth2(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth2(self, ubman, efi_boot_env):
"""
Test Case 2 - Secure boot is in force,
authenticated by db (TEST_db certificate in db)
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 2a'):
+ with ubman.log.section('Test Case 2a'):
# Test Case 2a, db is not yet installed
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert('\'HELLO1\' failed' in ''.join(output))
assert('efi_bootmgr_load() returned: 26' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
'efidebug boot order 2',
'efidebug test bootmgr'])
assert '\'HELLO2\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 2b'):
+ with ubman.log.section('Test Case 2b'):
# Test Case 2b, authenticated by db
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 2',
'efidebug test bootmgr'])
assert '\'HELLO2\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
- def test_efi_signed_image_auth3(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth3(self, ubman, efi_boot_env):
"""
Test Case 3 - rejected by dbx (TEST_db certificate in dbx)
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 3a'):
+ with ubman.log.section('Test Case 3a'):
# Test Case 3a, rejected by dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -103,34 +103,34 @@
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 3b'):
+ with ubman.log.section('Test Case 3b'):
# Test Case 3b, rejected by dbx even if db allows
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- def test_efi_signed_image_auth4(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth4(self, ubman, efi_boot_env):
"""
Test Case 4 - revoked by dbx (digest of TEST_db certificate in dbx)
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 4'):
+ with ubman.log.section('Test Case 4'):
# Test Case 4, rejected by dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 dbx_hash.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -141,25 +141,25 @@
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- def test_efi_signed_image_auth5(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth5(self, ubman, efi_boot_env):
"""
Test Case 5 - multiple signatures
one signed with TEST_db, and
one signed with TEST_db1
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 5a'):
+ with ubman.log.section('Test Case 5a'):
# Test Case 5a, authenticated even if only one of signatures
# is verified
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -168,54 +168,54 @@
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
- with u_boot_console.log.section('Test Case 5b'):
+ with ubman.log.section('Test Case 5b'):
# Test Case 5b, authenticated if both signatures are verified
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
- with u_boot_console.log.section('Test Case 5c'):
+ with ubman.log.section('Test Case 5c'):
# Test Case 5c, rejected if one of signatures (digest of
# certificate) is revoked
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 dbx_hash.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 5d'):
+ with ubman.log.section('Test Case 5d'):
# Test Case 5d, rejected if both of signatures are revoked
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 dbx_hash2.auth',
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
# Try rejection in reverse order.
- u_boot_console.restart_uboot()
- with u_boot_console.log.section('Test Case 5e'):
+ ubman.restart_uboot()
+ with ubman.log.section('Test Case 5e'):
# Test Case 5e, authenticated even if only one of signatures
# is verified. Same as before but reject dbx_hash1.auth only
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -228,22 +228,22 @@
'fatload host 0:1 4000000 dbx_hash1.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- def test_efi_signed_image_auth6(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth6(self, ubman, efi_boot_env):
"""
Test Case 6 - using digest of signed image in database
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 6a'):
+ with ubman.log.section('Test Case 6a'):
# Test Case 6a, verified by image's digest in db
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db_hello_signed.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -252,47 +252,47 @@
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
- with u_boot_console.log.section('Test Case 6b'):
+ with ubman.log.section('Test Case 6b'):
# Test Case 6b, rejected by TEST_db certificate in dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 dbx_db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 6c'):
+ with ubman.log.section('Test Case 6c'):
# Test Case 6c, rejected by image's digest in dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
'fatload host 0:1 4000000 dbx_hello_signed.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- def test_efi_signed_image_auth7(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth7(self, ubman, efi_boot_env):
"""
Test Case 7 - Reject images based on the sha384/512 of their x509 cert
"""
# sha384 of an x509 cert in dbx
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 7a'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 7a'):
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -305,7 +305,7 @@
'fatload host 0:1 4000000 dbx_hash384.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
@@ -313,9 +313,9 @@
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
# sha512 of an x509 cert in dbx
- u_boot_console.restart_uboot()
- with u_boot_console.log.section('Test Case 7b'):
- output = u_boot_console.run_command_list([
+ ubman.restart_uboot()
+ with ubman.log.section('Test Case 7b'):
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -328,34 +328,34 @@
'fatload host 0:1 4000000 dbx_hash512.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- def test_efi_signed_image_auth8(self, u_boot_console, efi_boot_env):
+ def test_efi_signed_image_auth8(self, ubman, efi_boot_env):
"""
Test Case 8 - Secure boot is in force,
Same as Test Case 2 but the image binary to be loaded
was willfully modified (forged)
Must be rejected.
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 8a'):
+ with ubman.log.section('Test Case 8a'):
# Test Case 8a, Secure boot is not yet forced
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld_forged.efi.signed -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert('hELLO, world!' in ''.join(output))
- with u_boot_console.log.section('Test Case 8b'):
+ with ubman.log.section('Test Case 8b'):
# Test Case 8b, Install signature database and verify the image
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
'fatload host 0:1 4000000 KEK.auth',
@@ -363,7 +363,7 @@
'fatload host 0:1 4000000 PK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert(not 'hELLO, world!' in ''.join(output))
diff --git a/test/py/tests/test_efi_secboot/test_signed_intca.py b/test/py/tests/test_efi_secboot/test_signed_intca.py
index cf90620..58f7be0 100644
--- a/test/py/tests/test_efi_secboot/test_signed_intca.py
+++ b/test/py/tests/test_efi_secboot/test_signed_intca.py
@@ -20,15 +20,15 @@
@pytest.mark.buildconfigspec('cmd_nvedit_efi')
@pytest.mark.slow
class TestEfiSignedImageIntca(object):
- def test_efi_signed_image_intca1(self, u_boot_console, efi_boot_env_intca):
+ def test_efi_signed_image_intca1(self, ubman, efi_boot_env_intca):
"""
Test Case 1 - authenticated by root CA in db
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env_intca
- with u_boot_console.log.section('Test Case 1a'):
+ with ubman.log.section('Test Case 1a'):
# Test Case 1a, with no Int CA and not authenticated by root CA
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -38,30 +38,30 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO_a host 0:1 /helloworld.efi.signed_a -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_a\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 1b'):
+ with ubman.log.section('Test Case 1b'):
# Test Case 1b, signed and authenticated by root CA
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 2 HELLO_ab host 0:1 /helloworld.efi.signed_ab -s ""',
'efidebug boot order 2',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
- def test_efi_signed_image_intca2(self, u_boot_console, efi_boot_env_intca):
+ def test_efi_signed_image_intca2(self, ubman, efi_boot_env_intca):
"""
Test Case 2 - authenticated by root CA in db
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env_intca
- with u_boot_console.log.section('Test Case 2a'):
+ with ubman.log.section('Test Case 2a'):
# Test Case 2a, unsigned and not authenticated by root CA
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
@@ -69,16 +69,16 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 2b'):
+ with ubman.log.section('Test Case 2b'):
# Test Case 2b, signed and authenticated by root CA
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db_b.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
'efidebug boot order 1',
@@ -86,24 +86,24 @@
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 2c'):
+ with ubman.log.section('Test Case 2c'):
# Test Case 2c, signed and authenticated by root CA
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
- def test_efi_signed_image_intca3(self, u_boot_console, efi_boot_env_intca):
+ def test_efi_signed_image_intca3(self, ubman, efi_boot_env_intca):
"""
Test Case 3 - revoked by dbx
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env_intca
- with u_boot_console.log.section('Test Case 3a'):
+ with ubman.log.section('Test Case 3a'):
# Test Case 3a, revoked by int CA in dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 dbx_b.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -115,7 +115,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
'efidebug boot order 1',
'efidebug test bootmgr'])
@@ -124,9 +124,9 @@
# assert '\'HELLO_abc\' failed' in ''.join(output)
# assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
- with u_boot_console.log.section('Test Case 3b'):
+ with ubman.log.section('Test Case 3b'):
# Test Case 3b, revoked by root CA in dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 dbx_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
'efidebug boot order 1',
diff --git a/test/py/tests/test_efi_secboot/test_unsigned.py b/test/py/tests/test_efi_secboot/test_unsigned.py
index b4320ae..bd6e1b2 100644
--- a/test/py/tests/test_efi_secboot/test_unsigned.py
+++ b/test/py/tests/test_efi_secboot/test_unsigned.py
@@ -18,15 +18,15 @@
@pytest.mark.buildconfigspec('cmd_nvedit_efi')
@pytest.mark.slow
class TestEfiUnsignedImage(object):
- def test_efi_unsigned_image_auth1(self, u_boot_console, efi_boot_env):
+ def test_efi_unsigned_image_auth1(self, ubman, efi_boot_env):
"""
Test Case 1 - rejected when not digest in db or dbx
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 1'):
+ with ubman.log.section('Test Case 1'):
# Test Case 1
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 KEK.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
@@ -34,26 +34,26 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
- def test_efi_unsigned_image_auth2(self, u_boot_console, efi_boot_env):
+ def test_efi_unsigned_image_auth2(self, ubman, efi_boot_env):
"""
Test Case 2 - authenticated by digest in db
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 2'):
+ with ubman.log.section('Test Case 2'):
# Test Case 2
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db_hello.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -63,21 +63,21 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
- def test_efi_unsigned_image_auth3(self, u_boot_console, efi_boot_env):
+ def test_efi_unsigned_image_auth3(self, ubman, efi_boot_env):
"""
Test Case 3 - rejected by digest in dbx
"""
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
disk_img = efi_boot_env
- with u_boot_console.log.section('Test Case 3a'):
+ with ubman.log.section('Test Case 3a'):
# Test Case 3a, rejected by dbx
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % disk_img,
'fatload host 0:1 4000000 db_hello.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -87,30 +87,30 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
- with u_boot_console.log.section('Test Case 3b'):
+ with ubman.log.section('Test Case 3b'):
# Test Case 3b, rejected by dbx even if db allows
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'fatload host 0:1 4000000 db_hello.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py
index 310d8ed..12cbe5c 100644
--- a/test/py/tests/test_efi_selftest.py
+++ b/test/py/tests/test_efi_selftest.py
@@ -7,191 +7,191 @@
import pytest
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_base(u_boot_console):
+def test_efi_selftest_base(ubman):
"""Run UEFI unit tests
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
This function executes all selftests that are not marked as on request.
"""
- u_boot_console.run_command(cmd='setenv efi_selftest')
- u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
- if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+ ubman.run_command(cmd='setenv efi_selftest')
+ ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+ if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
raise Exception('Failures occurred during the EFI selftest')
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
@pytest.mark.buildconfigspec('hush_parser')
@pytest.mark.buildconfigspec('of_control')
@pytest.mark.notbuildconfigspec('generate_acpi_table')
-def test_efi_selftest_device_tree(u_boot_console):
+def test_efi_selftest_device_tree(ubman):
"""Test the device tree support in the UEFI sub-system
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
This test executes the UEFI unit test by calling 'bootefi selftest'.
"""
- u_boot_console.run_command(cmd='setenv efi_selftest list')
- output = u_boot_console.run_command('bootefi selftest')
+ ubman.run_command(cmd='setenv efi_selftest list')
+ output = ubman.run_command('bootefi selftest')
assert '\'device tree\'' in output
- u_boot_console.run_command(cmd='setenv efi_selftest device tree')
+ ubman.run_command(cmd='setenv efi_selftest device tree')
# Set serial# if it is not already set.
- u_boot_console.run_command(cmd='setenv efi_test "${serial#}x"')
- u_boot_console.run_command(cmd='test "${efi_test}" = x && setenv serial# 0')
- u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
- if u_boot_console.p.expect(['serial-number:', 'U-Boot']):
+ ubman.run_command(cmd='setenv efi_test "${serial#}x"')
+ ubman.run_command(cmd='test "${efi_test}" = x && setenv serial# 0')
+ ubman.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
+ if ubman.p.expect(['serial-number:', 'U-Boot']):
raise Exception('serial-number missing in device tree')
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_watchdog_reboot(u_boot_console):
+def test_efi_selftest_watchdog_reboot(ubman):
"""Test the watchdog timer
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
This function executes the 'watchdog reboot' unit test.
"""
- u_boot_console.run_command(cmd='setenv efi_selftest list')
- output = u_boot_console.run_command('bootefi selftest')
+ ubman.run_command(cmd='setenv efi_selftest list')
+ output = ubman.run_command('bootefi selftest')
assert '\'watchdog reboot\'' in output
- u_boot_console.run_command(cmd='setenv efi_selftest watchdog reboot')
- u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
- if u_boot_console.p.expect(['resetting', 'U-Boot']):
+ ubman.run_command(cmd='setenv efi_selftest watchdog reboot')
+ ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+ if ubman.p.expect(['resetting', 'U-Boot']):
raise Exception('Reset failed in \'watchdog reboot\' test')
- u_boot_console.run_command(cmd='', send_nl=False, wait_for_reboot=True)
+ ubman.run_command(cmd='', send_nl=False, wait_for_reboot=True)
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_text_input(u_boot_console):
+def test_efi_selftest_text_input(ubman):
"""Test the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
This function calls the text input EFI selftest.
"""
- u_boot_console.run_command(cmd='setenv efi_selftest text input')
- u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
- if u_boot_console.p.expect([r'To terminate type \'x\'']):
+ ubman.run_command(cmd='setenv efi_selftest text input')
+ ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+ if ubman.p.expect([r'To terminate type \'x\'']):
raise Exception('No prompt for \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# EOT
- u_boot_console.run_command(cmd=chr(4), wait_for_echo=False,
+ ubman.run_command(cmd=chr(4), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 4 \(unknown\), scan code 0 \(Null\)']):
+ if ubman.p.expect([r'Unicode char 4 \(unknown\), scan code 0 \(Null\)']):
raise Exception('EOT failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# BS
- u_boot_console.run_command(cmd=chr(8), wait_for_echo=False,
+ ubman.run_command(cmd=chr(8), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(Null\)']):
+ if ubman.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(Null\)']):
raise Exception('BS failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# TAB
- u_boot_console.run_command(cmd=chr(9), wait_for_echo=False,
+ ubman.run_command(cmd=chr(9), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(Null\)']):
+ if ubman.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(Null\)']):
raise Exception('BS failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# a
- u_boot_console.run_command(cmd='a', wait_for_echo=False, send_nl=False,
+ ubman.run_command(cmd='a', wait_for_echo=False, send_nl=False,
wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
+ if ubman.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
raise Exception('\'a\' failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# UP escape sequence
- u_boot_console.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
+ ubman.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(Up\)']):
+ if ubman.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(Up\)']):
raise Exception('UP failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# Euro sign
- u_boot_console.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
+ ubman.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 8364 \(\'']):
+ if ubman.p.expect([r'Unicode char 8364 \(\'']):
raise Exception('Euro sign failed in \'text input\' test')
- u_boot_console.drain_console()
- u_boot_console.run_command(cmd='x', wait_for_echo=False, send_nl=False,
+ ubman.drain_console()
+ ubman.run_command(cmd='x', wait_for_echo=False, send_nl=False,
wait_for_prompt=False)
- if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+ if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
raise Exception('Failures occurred during the EFI selftest')
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_text_input_ex(u_boot_console):
+def test_efi_selftest_text_input_ex(ubman):
"""Test the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
This function calls the extended text input EFI selftest.
"""
- u_boot_console.run_command(cmd='setenv efi_selftest extended text input')
- u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
- if u_boot_console.p.expect([r'To terminate type \'CTRL\+x\'']):
+ ubman.run_command(cmd='setenv efi_selftest extended text input')
+ ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+ if ubman.p.expect([r'To terminate type \'CTRL\+x\'']):
raise Exception('No prompt for \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# EOT
- u_boot_console.run_command(cmd=chr(4), wait_for_echo=False,
+ ubman.run_command(cmd=chr(4), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 100 \(\'d\'\), scan code 0 \(CTRL\+Null\)']):
+ if ubman.p.expect([r'Unicode char 100 \(\'d\'\), scan code 0 \(CTRL\+Null\)']):
raise Exception('EOT failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# BS
- u_boot_console.run_command(cmd=chr(8), wait_for_echo=False,
+ ubman.run_command(cmd=chr(8), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(\+Null\)']):
+ if ubman.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(\+Null\)']):
raise Exception('BS failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# TAB
- u_boot_console.run_command(cmd=chr(9), wait_for_echo=False,
+ ubman.run_command(cmd=chr(9), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(\+Null\)']):
+ if ubman.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(\+Null\)']):
raise Exception('TAB failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# a
- u_boot_console.run_command(cmd='a', wait_for_echo=False, send_nl=False,
+ ubman.run_command(cmd='a', wait_for_echo=False, send_nl=False,
wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
+ if ubman.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
raise Exception('\'a\' failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# UP escape sequence
- u_boot_console.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
+ ubman.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(\+Up\)']):
+ if ubman.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(\+Up\)']):
raise Exception('UP failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# Euro sign
- u_boot_console.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
+ ubman.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
send_nl=False, wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 8364 \(\'']):
+ if ubman.p.expect([r'Unicode char 8364 \(\'']):
raise Exception('Euro sign failed in \'text input\' test')
- u_boot_console.drain_console()
+ ubman.drain_console()
# SHIFT+ALT+FN 5
- u_boot_console.run_command(cmd=b'\x1b\x5b\x31\x35\x3b\x34\x7e'.decode(),
+ ubman.run_command(cmd=b'\x1b\x5b\x31\x35\x3b\x34\x7e'.decode(),
wait_for_echo=False, send_nl=False,
wait_for_prompt=False)
- if u_boot_console.p.expect([r'Unicode char 0 \(Null\), scan code 15 \(SHIFT\+ALT\+FN 5\)']):
+ if ubman.p.expect([r'Unicode char 0 \(Null\), scan code 15 \(SHIFT\+ALT\+FN 5\)']):
raise Exception('SHIFT+ALT+FN 5 failed in \'text input\' test')
- u_boot_console.drain_console()
- u_boot_console.run_command(cmd=chr(24), wait_for_echo=False, send_nl=False,
+ ubman.drain_console()
+ ubman.run_command(cmd=chr(24), wait_for_echo=False, send_nl=False,
wait_for_prompt=False)
- if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+ if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
raise Exception('Failures occurred during the EFI selftest')
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
@pytest.mark.buildconfigspec('cmd_bootefi_selftest')
@pytest.mark.buildconfigspec('efi_tcg2_protocol')
-def test_efi_selftest_tcg2(u_boot_console):
+def test_efi_selftest_tcg2(ubman):
"""Test the EFI_TCG2 PROTOCOL
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
This function executes the 'tcg2' unit test.
"""
- u_boot_console.restart_uboot()
- u_boot_console.run_command(cmd='setenv efi_selftest list')
- output = u_boot_console.run_command('bootefi selftest')
+ ubman.restart_uboot()
+ ubman.run_command(cmd='setenv efi_selftest list')
+ output = ubman.run_command('bootefi selftest')
assert '\'tcg2\'' in output
- u_boot_console.run_command(cmd='setenv efi_selftest tcg2')
- u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
- if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+ ubman.run_command(cmd='setenv efi_selftest tcg2')
+ ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+ if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
raise Exception('Failures occurred during the EFI selftest')
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_eficonfig/test_eficonfig.py b/test/py/tests/test_eficonfig/test_eficonfig.py
index d98de52..3ca8e27 100644
--- a/test/py/tests/test_eficonfig/test_eficonfig.py
+++ b/test/py/tests/test_eficonfig/test_eficonfig.py
@@ -8,47 +8,47 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_eficonfig')
@pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
-def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
+def test_efi_eficonfig(ubman, efi_eficonfig_data):
def send_user_input_and_wait(user_str, expect_str):
time.sleep(0.1) # TODO: does not work correctly without sleep
- u_boot_console.run_command(cmd=user_str, wait_for_prompt=False,
+ ubman.run_command(cmd=user_str, wait_for_prompt=False,
wait_for_echo=True, send_nl=False)
- u_boot_console.run_command(cmd='\x0d', wait_for_prompt=False,
+ ubman.run_command(cmd='\x0d', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
if expect_str is not None:
for i in expect_str:
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
def press_up_down_enter_and_wait(up_count, down_count, enter, expect_str):
# press UP key
for i in range(up_count):
- u_boot_console.run_command(cmd='\x1b\x5b\x41', wait_for_prompt=False,
+ ubman.run_command(cmd='\x1b\x5b\x41', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
# press DOWN key
for i in range(down_count):
- u_boot_console.run_command(cmd='\x1b\x5b\x42', wait_for_prompt=False,
+ ubman.run_command(cmd='\x1b\x5b\x42', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
# press ENTER if requested
if enter:
- u_boot_console.run_command(cmd='\x0d', wait_for_prompt=False,
+ ubman.run_command(cmd='\x0d', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
# wait expected output
if expect_str is not None:
for i in expect_str:
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
def press_escape_key(wait_prompt):
- u_boot_console.run_command(cmd='\x1b', wait_for_prompt=wait_prompt, wait_for_echo=False, send_nl=False)
+ ubman.run_command(cmd='\x1b', wait_for_prompt=wait_prompt, wait_for_echo=False, send_nl=False)
def press_enter_key(wait_prompt):
- u_boot_console.run_command(cmd='\x0d', wait_for_prompt=wait_prompt,
+ ubman.run_command(cmd='\x0d', wait_for_prompt=wait_prompt,
wait_for_echo=False, send_nl=False)
def check_current_is_maintenance_menu():
for i in ('UEFI Maintenance Menu', 'Add Boot Option', 'Edit Boot Option',
'Change Boot Order', 'Delete Boot Option', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
""" Unit test for "eficonfig" command
The menu-driven interface is used to set up UEFI load options.
@@ -56,7 +56,7 @@
The crc32 of the loaded initrd.img is checked
Args:
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
efi__data -- Path to the disk image used for testing.
Test disk image has following files.
initrd-1.img
@@ -69,21 +69,21 @@
return
# Restart the system to clean the previous state
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
- with u_boot_console.temporary_timeout(500):
+ with ubman.temporary_timeout(500):
#
# Test Case 1: Check the menu is displayed
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
for i in ('UEFI Maintenance Menu', 'Add Boot Option', 'Edit Boot Option',
'Change Boot Order', 'Delete Boot Option', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Select "Add Boot Option"
press_enter_key(False)
for i in ('Add Boot Option', 'Description:', 'File', 'Initrd File', 'Optional Data',
'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
press_escape_key(False)
check_current_is_maintenance_menu()
# return to U-Boot console
@@ -94,16 +94,16 @@
#
# bind the test disk image for succeeding tests
- u_boot_console.run_command(cmd = f'host bind 0 {efi_eficonfig_data}')
+ ubman.run_command(cmd = f'host bind 0 {efi_eficonfig_data}')
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Change the Boot Order
press_up_down_enter_and_wait(0, 2, True, 'Quit')
for i in ('host 0:1', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# disable auto generated boot option for succeeding test
- u_boot_console.run_command(cmd=' ', wait_for_prompt=False,
+ ubman.run_command(cmd=' ', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
# Save the BootOrder
press_up_down_enter_and_wait(0, 1, True, None)
@@ -143,7 +143,7 @@
send_user_input_and_wait('nocolor', None)
for i in ('Description: test 1', 'File: host 0:1/initrddump.efi',
'Initrd File: host 0:1/initrd-1.img', 'Optional Data: nocolor', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Save the Boot Option
press_up_down_enter_and_wait(0, 4, True, None)
@@ -152,15 +152,15 @@
# Check the newly added Boot Option is handled correctly
# Return to U-Boot console
press_escape_key(True)
- u_boot_console.run_command(cmd = 'bootefi bootmgr')
- response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ ubman.run_command(cmd = 'bootefi bootmgr')
+ response = ubman.run_command(cmd = 'load', wait_for_echo=False)
assert 'crc32: 0x181464af' in response
- u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+ ubman.run_command(cmd = 'exit', wait_for_echo=False)
#
# Test Case 4: Add second Boot Option and load it
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Select 'Add Boot Option'
press_up_down_enter_and_wait(0, 0, True, 'Quit')
@@ -192,7 +192,7 @@
send_user_input_and_wait('nocolor', None)
for i in ('Description: test 2', 'File: host 0:1/initrddump.efi',
'Initrd File: host 0:1/initrd-2.img', 'Optional Data: nocolor', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Save the Boot Option
press_up_down_enter_and_wait(0, 4, True, 'Quit')
@@ -201,10 +201,10 @@
press_up_down_enter_and_wait(0, 2, True, 'Quit')
press_up_down_enter_and_wait(0, 1, False, 'Quit')
# move 'test 1' to the second entry
- u_boot_console.run_command(cmd='+', wait_for_prompt=False,
+ ubman.run_command(cmd='+', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
for i in ('test 2', 'test 1', 'host 0:1', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Save the BootOrder
press_up_down_enter_and_wait(0, 3, True, None)
check_current_is_maintenance_menu()
@@ -212,52 +212,52 @@
# Check the newly added Boot Option is handled correctly
# Return to U-Boot console
press_escape_key(True)
- u_boot_console.run_command(cmd = 'bootefi bootmgr')
- response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ ubman.run_command(cmd = 'bootefi bootmgr')
+ response = ubman.run_command(cmd = 'load', wait_for_echo=False)
assert 'crc32: 0x811d3515' in response
- u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+ ubman.run_command(cmd = 'exit', wait_for_echo=False)
#
# Test Case 5: Change BootOrder and load it
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Change the Boot Order
press_up_down_enter_and_wait(0, 2, True, None)
# Check the current BootOrder
for i in ('test 2', 'test 1', 'host 0:1', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# move 'test 2' to the second entry
- u_boot_console.run_command(cmd='-', wait_for_prompt=False,
+ ubman.run_command(cmd='-', wait_for_prompt=False,
wait_for_echo=False, send_nl=False)
for i in ('test 1', 'test 2', 'host 0:1', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Save the BootOrder
press_up_down_enter_and_wait(0, 2, True, None)
check_current_is_maintenance_menu()
# Return to U-Boot console
press_escape_key(True)
- u_boot_console.run_command(cmd = 'bootefi bootmgr')
- response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ ubman.run_command(cmd = 'bootefi bootmgr')
+ response = ubman.run_command(cmd = 'load', wait_for_echo=False)
assert 'crc32: 0x181464af' in response
- u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+ ubman.run_command(cmd = 'exit', wait_for_echo=False)
#
# Test Case 6: Delete Boot Option(label:test 2)
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Select 'Delete Boot Option'
press_up_down_enter_and_wait(0, 3, True, None)
# Check the current BootOrder
for i in ('test 1', 'test 2', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Delete 'test 2'
press_up_down_enter_and_wait(0, 1, True, None)
for i in ('test 1', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
press_escape_key(False)
check_current_is_maintenance_menu()
# Return to U-Boot console
@@ -266,16 +266,16 @@
#
# Test Case 7: Edit Boot Option
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Select 'Edit Boot Option'
press_up_down_enter_and_wait(0, 1, True, None)
# Check the current BootOrder
for i in ('test 1', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
press_up_down_enter_and_wait(0, 0, True, None)
for i in ('Description: test 1', 'File: host 0:1/initrddump.efi',
'Initrd File: host 0:1/initrd-1.img', 'Optional Data: nocolor', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Press the enter key to select 'Description:' entry, then enter Description
press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
@@ -304,7 +304,7 @@
send_user_input_and_wait('', None)
for i in ('Description: test 3', 'File: host 0:1/initrddump.efi',
'Initrd File: host 0:1/initrd-2.img', 'Optional Data:', 'Save', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Save the Boot Option
press_up_down_enter_and_wait(0, 4, True, 'Quit')
@@ -314,21 +314,21 @@
# Check the updated Boot Option is handled correctly
# Return to U-Boot console
press_escape_key(True)
- u_boot_console.run_command(cmd = 'bootefi bootmgr')
- response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+ ubman.run_command(cmd = 'bootefi bootmgr')
+ response = ubman.run_command(cmd = 'load', wait_for_echo=False)
assert 'crc32: 0x811d3515' in response
- u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+ ubman.run_command(cmd = 'exit', wait_for_echo=False)
#
# Test Case 8: Delete Boot Option(label:test 3)
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Select 'Delete Boot Option'
press_up_down_enter_and_wait(0, 3, True, None)
# Check the current BootOrder
for i in ('test 3', 'Quit'):
- u_boot_console.p.expect([i])
+ ubman.p.expect([i])
# Delete 'test 3'
press_up_down_enter_and_wait(0, 0, True, 'Quit')
@@ -338,12 +338,12 @@
press_escape_key(True)
# remove the host device
- u_boot_console.run_command(cmd = f'host bind -r 0')
+ ubman.run_command(cmd = f'host bind -r 0')
#
# Test Case 9: No block device found
#
- u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+ ubman.run_command('eficonfig', wait_for_prompt=False)
# Select 'Add Boot Option'
press_up_down_enter_and_wait(0, 0, True, 'Quit')
diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index 4471db7..383e26c 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -13,7 +13,7 @@
import tempfile
import pytest
-import u_boot_utils
+import utils
# FIXME: This might be useful for other tests;
# perhaps refactor it into ConsoleBase or some other state object?
@@ -23,17 +23,17 @@
names.
"""
- def __init__(self, u_boot_console):
+ def __init__(self, ubman):
"""Initialize a new StateTestEnv object.
Args:
- u_boot_console: A U-Boot console.
+ ubman: A U-Boot console.
Returns:
Nothing.
"""
- self.u_boot_console = u_boot_console
+ self.ubman = ubman
self.get_env()
self.set_var = self.get_non_existent_var()
@@ -47,12 +47,12 @@
Nothing.
"""
- if self.u_boot_console.config.buildconfig.get(
+ if self.ubman.config.buildconfig.get(
'config_version_variable', 'n') == 'y':
- with self.u_boot_console.disable_check('main_signon'):
- response = self.u_boot_console.run_command('printenv')
+ with self.ubman.disable_check('main_signon'):
+ response = self.ubman.run_command('printenv')
else:
- response = self.u_boot_console.run_command('printenv')
+ response = self.ubman.run_command('printenv')
self.env = {}
for l in response.splitlines():
if not '=' in l:
@@ -92,12 +92,12 @@
ste = None
@pytest.fixture(scope='function')
-def state_test_env(u_boot_console):
+def state_test_env(ubman):
"""pytest fixture to provide a StateTestEnv object to tests."""
global ste
if not ste:
- ste = StateTestEnv(u_boot_console)
+ ste = StateTestEnv(ubman)
return ste
def unset_var(state_test_env, var):
@@ -114,7 +114,7 @@
Nothing.
"""
- state_test_env.u_boot_console.run_command('setenv %s' % var)
+ state_test_env.ubman.run_command('setenv %s' % var)
if var in state_test_env.env:
del state_test_env.env[var]
@@ -133,7 +133,7 @@
Nothing.
"""
- bc = state_test_env.u_boot_console.config.buildconfig
+ bc = state_test_env.ubman.config.buildconfig
if bc.get('config_hush_parser', None):
quote = '"'
else:
@@ -141,7 +141,7 @@
if ' ' in value:
pytest.skip('Space in variable value on non-Hush shell')
- state_test_env.u_boot_console.run_command(
+ state_test_env.ubman.run_command(
'setenv %s %s%s%s' % (var, quote, value, quote))
state_test_env.env[var] = value
@@ -155,7 +155,7 @@
Nothing.
"""
- response = state_test_env.u_boot_console.run_command('echo ${%s}' % var)
+ response = state_test_env.ubman.run_command('echo ${%s}' % var)
assert response == ''
def validate_set(state_test_env, var, value):
@@ -171,15 +171,14 @@
# echo does not preserve leading, internal, or trailing whitespace in the
# value. printenv does, and hence allows more complete testing.
- response = state_test_env.u_boot_console.run_command('printenv %s' % var)
+ response = state_test_env.ubman.run_command('printenv %s' % var)
assert response == ('%s=%s' % (var, value))
@pytest.mark.boardspec('sandbox')
-def test_env_initial_env_file(u_boot_console):
+def test_env_initial_env_file(ubman):
"""Test that the u-boot-initial-env make target works"""
- cons = u_boot_console
- builddir = 'O=' + cons.config.build_dir
- envfile = cons.config.build_dir + '/u-boot-initial-env'
+ builddir = 'O=' + ubman.config.build_dir
+ envfile = ubman.config.build_dir + '/u-boot-initial-env'
# remove if already exists from an older run
try:
@@ -187,7 +186,7 @@
except:
pass
- u_boot_utils.run_and_log(cons, ['make', builddir, 'u-boot-initial-env'])
+ utils.run_and_log(ubman, ['make', builddir, 'u-boot-initial-env'])
assert os.path.exists(envfile)
@@ -215,7 +214,7 @@
"""Test printenv error message for non-existant variables."""
var = state_test_env.set_var
- c = state_test_env.u_boot_console
+ c = state_test_env.ubman
with c.disable_check('error_notification'):
response = c.run_command('printenv %s' % var)
assert response == '## Error: "%s" not defined' % var
@@ -277,8 +276,8 @@
"""Test that omitted ('-') size parameter with checksum validation fails the
env import function.
"""
- c = state_test_env.u_boot_console
- ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+ c = state_test_env.ubman
+ ram_base = utils.find_ram_base(state_test_env.ubman)
addr = '%08x' % ram_base
with c.disable_check('error_notification'):
@@ -290,8 +289,8 @@
"""Test that omitted ('-') size parameter with checksum validation fails the
env import function when variables are passed as parameters.
"""
- c = state_test_env.u_boot_console
- ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+ c = state_test_env.ubman
+ ram_base = utils.find_ram_base(state_test_env.ubman)
addr = '%08x' % ram_base
with c.disable_check('error_notification'):
@@ -302,8 +301,8 @@
@pytest.mark.buildconfigspec('cmd_importenv')
def test_env_import_whitelist(state_test_env):
"""Test importing only a handful of env variables from an environment."""
- c = state_test_env.u_boot_console
- ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+ c = state_test_env.ubman
+ ram_base = utils.find_ram_base(state_test_env.ubman)
addr = '%08x' % ram_base
set_var(state_test_env, 'foo1', 'bar1')
@@ -339,8 +338,8 @@
deletion if a var A that is passed to env import is not in the
environment to be imported.
"""
- c = state_test_env.u_boot_console
- ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+ c = state_test_env.ubman
+ ram_base = utils.find_ram_base(state_test_env.ubman)
addr = '%08x' % ram_base
set_var(state_test_env, 'foo1', 'bar1')
@@ -373,7 +372,7 @@
"""Test 'env info' command with all possible options.
"""
- c = state_test_env.u_boot_console
+ c = state_test_env.ubman
response = c.run_command('env info')
nb_line = 0
@@ -410,7 +409,7 @@
"""Test 'env info' command result with several options on sandbox
with a known ENV configuration: ready & default & persistent
"""
- c = state_test_env.u_boot_console
+ c = state_test_env.ubman
response = c.run_command('env info')
assert 'env_ready = true' in response
@@ -435,7 +434,7 @@
def mk_env_ext4(state_test_env):
"""Create a empty ext4 file system volume."""
- c = state_test_env.u_boot_console
+ c = state_test_env.ubman
filename = 'env.ext4.img'
persistent = c.config.persistent_data_dir + '/' + filename
fs_img = c.config.result_dir + '/' + filename
@@ -446,16 +445,16 @@
# Some distributions do not add /sbin to the default PATH, where mkfs.ext4 lives
os.environ["PATH"] += os.pathsep + '/sbin'
try:
- u_boot_utils.run_and_log(c, 'dd if=/dev/zero of=%s bs=1M count=16' % persistent)
- u_boot_utils.run_and_log(c, 'mkfs.ext4 %s' % persistent)
- sb_content = u_boot_utils.run_and_log(c, 'tune2fs -l %s' % persistent)
+ utils.run_and_log(c, 'dd if=/dev/zero of=%s bs=1M count=16' % persistent)
+ utils.run_and_log(c, 'mkfs.ext4 %s' % persistent)
+ sb_content = utils.run_and_log(c, 'tune2fs -l %s' % persistent)
if 'metadata_csum' in sb_content:
- u_boot_utils.run_and_log(c, 'tune2fs -O ^metadata_csum %s' % persistent)
+ utils.run_and_log(c, 'tune2fs -O ^metadata_csum %s' % persistent)
except CalledProcessError:
call('rm -f %s' % persistent, shell=True)
raise
- u_boot_utils.run_and_log(c, ['cp', '-f', persistent, fs_img])
+ utils.run_and_log(c, ['cp', '-f', persistent, fs_img])
return fs_img
@pytest.mark.boardspec('sandbox')
@@ -467,7 +466,7 @@
def test_env_ext4(state_test_env):
"""Test ENV in EXT4 on sandbox."""
- c = state_test_env.u_boot_console
+ c = state_test_env.ubman
fs_img = ''
try:
fs_img = mk_env_ext4(state_test_env)
@@ -545,7 +544,7 @@
if fs_img:
call('rm -f %s' % fs_img, shell=True)
-def test_env_text(u_boot_console):
+def test_env_text(ubman):
"""Test the script that converts the environment to a text file"""
def check_script(intext, expect_val):
@@ -560,15 +559,14 @@
fname = os.path.join(path, 'infile')
with open(fname, 'w') as inf:
print(intext, file=inf)
- result = u_boot_utils.run_and_log(cons, ['awk', '-f', script, fname])
+ result = utils.run_and_log(ubman, ['awk', '-f', script, fname])
if expect_val is not None:
expect = '#define CONFIG_EXTRA_ENV_TEXT "%s"\n' % expect_val
assert result == expect
else:
assert result == ''
- cons = u_boot_console
- script = os.path.join(cons.config.source_dir, 'scripts', 'env2string.awk')
+ script = os.path.join(ubman.config.source_dir, 'scripts', 'env2string.awk')
# simple script with a single var
check_script('fred=123', 'fred=123\\0')
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
index 177b982..b9d48f5 100644
--- a/test/py/tests/test_event_dump.py
+++ b/test/py/tests/test_event_dump.py
@@ -4,16 +4,15 @@
import pytest
import re
-import u_boot_utils as util
+import utils
# This is only a partial test - coverting 64-bit sandbox. It does not test
# big-endian images, nor 32-bit images
@pytest.mark.boardspec('sandbox')
-def test_event_dump(u_boot_console):
+def test_event_dump(ubman):
"""Test that the "help" command can be executed."""
- cons = u_boot_console
- sandbox = cons.config.build_dir + '/u-boot'
- out = util.run_and_log(cons, ['scripts/event_dump.py', sandbox])
+ sandbox = ubman.config.build_dir + '/u-boot'
+ out = utils.run_and_log(ubman, ['scripts/event_dump.py', sandbox])
expect = '''.*Event type Id Source location
-------------------- ------------------------------ ------------------------------
EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.*
diff --git a/test/py/tests/test_extension.py b/test/py/tests/test_extension.py
index 2a3c511..6122349 100644
--- a/test/py/tests/test_extension.py
+++ b/test/py/tests/test_extension.py
@@ -6,50 +6,50 @@
import os
import pytest
-import u_boot_utils
+import utils
overlay_addr = 0x1000
SANDBOX_DTB='arch/sandbox/dts/sandbox.dtb'
OVERLAY_DIR='arch/sandbox/dts/'
-def load_dtb(u_boot_console):
- u_boot_console.log.action('Loading devicetree to RAM...')
- u_boot_console.run_command('host load hostfs - $fdt_addr_r %s' % (os.path.join(u_boot_console.config.build_dir, SANDBOX_DTB)))
- u_boot_console.run_command('fdt addr $fdt_addr_r')
+def load_dtb(ubman):
+ ubman.log.action('Loading devicetree to RAM...')
+ ubman.run_command('host load hostfs - $fdt_addr_r %s' % (os.path.join(ubman.config.build_dir, SANDBOX_DTB)))
+ ubman.run_command('fdt addr $fdt_addr_r')
@pytest.mark.buildconfigspec('cmd_fdt')
@pytest.mark.boardspec('sandbox')
-def test_extension(u_boot_console):
+def test_extension(ubman):
"""Test the 'extension' command."""
- load_dtb(u_boot_console)
+ load_dtb(ubman)
- output = u_boot_console.run_command('extension list')
+ output = ubman.run_command('extension list')
# extension_bootdev_hunt may have already run.
# Without reboot we cannot make any assumption here.
# assert('No extension' in output)
- output = u_boot_console.run_command('extension scan')
+ output = ubman.run_command('extension scan')
assert output == 'Found 2 extension board(s).'
- output = u_boot_console.run_command('extension list')
+ output = ubman.run_command('extension list')
assert('overlay0.dtbo' in output)
assert('overlay1.dtbo' in output)
- u_boot_console.run_command_list([
+ ubman.run_command_list([
'setenv extension_overlay_addr %s' % (overlay_addr),
- 'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(u_boot_console.config.build_dir, OVERLAY_DIR))])
+ 'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(ubman.config.build_dir, OVERLAY_DIR))])
- output = u_boot_console.run_command('extension apply 0')
+ output = ubman.run_command('extension apply 0')
assert('bytes read' in output)
- output = u_boot_console.run_command('fdt print')
+ output = ubman.run_command('fdt print')
assert('button3' in output)
- output = u_boot_console.run_command('extension apply all')
+ output = ubman.run_command('extension apply all')
assert('bytes read' in output)
- output = u_boot_console.run_command('fdt print')
+ output = ubman.run_command('fdt print')
assert('button4' in output)
diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py
index 8f9c4b2..619f731 100755
--- a/test/py/tests/test_fit.py
+++ b/test/py/tests/test_fit.py
@@ -6,7 +6,7 @@
import os
import pytest
import struct
-import u_boot_utils as util
+import utils
import fit_util
# Define a base ITS which we can adjust using % and a dictionary
@@ -118,7 +118,7 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('fit_signature')
@pytest.mark.requiredtool('dtc')
-def test_fit(u_boot_console):
+def test_fit(ubman):
def make_fname(leaf):
"""Make a temporary filename
@@ -127,7 +127,7 @@
Return:
Temporary filename
"""
- return os.path.join(cons.config.build_dir, leaf)
+ return os.path.join(ubman.config.build_dir, leaf)
def filesize(fname):
"""Get the size of a file
@@ -165,7 +165,7 @@
return fname
def make_compressed(filename):
- util.run_and_log(cons, ['gzip', '-f', '-k', filename])
+ utils.run_and_log(ubman, ['gzip', '-f', '-k', filename])
return filename + '.gz'
def find_matching(text, match):
@@ -260,10 +260,10 @@
- run code coverage to make sure we are testing all the code
"""
# Set up invariant files
- control_dtb = fit_util.make_dtb(cons, base_fdt, 'u-boot')
- kernel = fit_util.make_kernel(cons, 'test-kernel.bin', 'kernel')
+ control_dtb = fit_util.make_dtb(ubman, base_fdt, 'u-boot')
+ kernel = fit_util.make_kernel(ubman, 'test-kernel.bin', 'kernel')
ramdisk = make_ramdisk('test-ramdisk.bin', 'ramdisk')
- loadables1 = fit_util.make_kernel(cons, 'test-loadables1.bin', 'lenrek')
+ loadables1 = fit_util.make_kernel(ubman, 'test-loadables1.bin', 'lenrek')
loadables2 = make_ramdisk('test-loadables2.bin', 'ksidmar')
kernel_out = make_fname('kernel-out.bin')
fdt = make_fname('u-boot.dtb')
@@ -311,16 +311,16 @@
}
# Make a basic FIT and a script to load it
- fit = fit_util.make_fit(cons, mkimage, base_its, params)
+ fit = fit_util.make_fit(ubman, mkimage, base_its, params)
params['fit'] = fit
cmd = base_script % params
# First check that we can load a kernel
# We could perhaps reduce duplication with some loss of readability
- cons.config.dtb = control_dtb
- cons.restart_uboot()
- with cons.log.section('Kernel load'):
- output = cons.run_command_list(cmd.splitlines())
+ ubman.config.dtb = control_dtb
+ ubman.restart_uboot()
+ with ubman.log.section('Kernel load'):
+ output = ubman.run_command_list(cmd.splitlines())
check_equal(kernel, kernel_out, 'Kernel not loaded')
check_not_equal(control_dtb, fdt_out,
'FDT loaded but should be ignored')
@@ -340,7 +340,7 @@
(fit_offset, real_fit_offset))
# Check if bootargs strings substitution works
- output = cons.run_command_list([
+ output = ubman.run_command_list([
'env set bootargs \\\"\'my_boot_var=${foo}\'\\\"',
'env set foo bar',
'bootm prep',
@@ -348,63 +348,62 @@
assert 'bootargs="my_boot_var=bar"' in output, "Bootargs strings not substituted"
# Now a kernel and an FDT
- with cons.log.section('Kernel + FDT load'):
+ with ubman.log.section('Kernel + FDT load'):
params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr']
- fit = fit_util.make_fit(cons, mkimage, base_its, params)
- cons.restart_uboot()
- output = cons.run_command_list(cmd.splitlines())
+ fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+ ubman.restart_uboot()
+ output = ubman.run_command_list(cmd.splitlines())
check_equal(kernel, kernel_out, 'Kernel not loaded')
check_equal(control_dtb, fdt_out, 'FDT not loaded')
check_not_equal(ramdisk, ramdisk_out,
'Ramdisk loaded but should not be')
# Try a ramdisk
- with cons.log.section('Kernel + FDT + Ramdisk load'):
+ with ubman.log.section('Kernel + FDT + Ramdisk load'):
params['ramdisk_config'] = 'ramdisk = "ramdisk-1";'
params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr']
- fit = fit_util.make_fit(cons, mkimage, base_its, params)
- cons.restart_uboot()
- output = cons.run_command_list(cmd.splitlines())
+ fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+ ubman.restart_uboot()
+ output = ubman.run_command_list(cmd.splitlines())
check_equal(ramdisk, ramdisk_out, 'Ramdisk not loaded')
# Configuration with some Loadables
- with cons.log.section('Kernel + FDT + Ramdisk load + Loadables'):
+ with ubman.log.section('Kernel + FDT + Ramdisk load + Loadables'):
params['loadables_config'] = 'loadables = "kernel-2", "ramdisk-2";'
params['loadables1_load'] = ('load = <%#x>;' %
params['loadables1_addr'])
params['loadables2_load'] = ('load = <%#x>;' %
params['loadables2_addr'])
- fit = fit_util.make_fit(cons, mkimage, base_its, params)
- cons.restart_uboot()
- output = cons.run_command_list(cmd.splitlines())
+ fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+ ubman.restart_uboot()
+ output = ubman.run_command_list(cmd.splitlines())
check_equal(loadables1, loadables1_out,
'Loadables1 (kernel) not loaded')
check_equal(loadables2, loadables2_out,
'Loadables2 (ramdisk) not loaded')
# Kernel, FDT and Ramdisk all compressed
- with cons.log.section('(Kernel + FDT + Ramdisk) compressed'):
+ with ubman.log.section('(Kernel + FDT + Ramdisk) compressed'):
params['compression'] = 'gzip'
params['kernel'] = make_compressed(kernel)
params['fdt'] = make_compressed(fdt)
params['ramdisk'] = make_compressed(ramdisk)
- fit = fit_util.make_fit(cons, mkimage, base_its, params)
- cons.restart_uboot()
- output = cons.run_command_list(cmd.splitlines())
+ fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+ ubman.restart_uboot()
+ output = ubman.run_command_list(cmd.splitlines())
check_equal(kernel, kernel_out, 'Kernel not loaded')
check_equal(control_dtb, fdt_out, 'FDT not loaded')
check_not_equal(ramdisk, ramdisk_out, 'Ramdisk got decompressed?')
check_equal(ramdisk + '.gz', ramdisk_out, 'Ramdist not loaded')
- cons = u_boot_console
# We need to use our own device tree file. Remember to restore it
# afterwards.
- old_dtb = cons.config.dtb
+ old_dtb = ubman.config.dtb
try:
- mkimage = cons.config.build_dir + '/tools/mkimage'
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
run_fit_test(mkimage)
finally:
# Go back to the original U-Boot with the correct dtb.
- cons.config.dtb = old_dtb
- cons.restart_uboot()
+ ubman.config.dtb = old_dtb
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_fit_auto_signed.py b/test/py/tests/test_fit_auto_signed.py
index 9ea3351..cdfd341 100644
--- a/test/py/tests/test_fit_auto_signed.py
+++ b/test/py/tests/test_fit_auto_signed.py
@@ -17,7 +17,7 @@
import os
import pytest
-import u_boot_utils as util
+import utils
import binascii
from Cryptodome.Hash import SHA1
from Cryptodome.Hash import SHA256
@@ -26,22 +26,22 @@
class SignedFitHelper(object):
"""Helper to manipulate a FIT with signed/hashed images/configs."""
- def __init__(self, cons, file_name):
+ def __init__(self, ubman, file_name):
self.fit = file_name
- self.cons = cons
+ self.ubman = ubman
self.images_nodes = set()
self.confgs_nodes = set()
def __fdt_list(self, path):
- return util.run_and_log(self.cons,
+ return utils.run_and_log(self.ubman,
f'fdtget -l {self.fit} {path}')
def __fdt_get_string(self, node, prop):
- return util.run_and_log(self.cons,
+ return utils.run_and_log(self.ubman,
f'fdtget -ts {self.fit} {node} {prop}')
def __fdt_get_binary(self, node, prop):
- numbers = util.run_and_log(self.cons,
+ numbers = utils.run_and_log(self.ubman,
f'fdtget -tbi {self.fit} {node} {prop}')
bignum = bytearray()
@@ -120,7 +120,7 @@
@pytest.mark.buildconfigspec('fit_signature')
@pytest.mark.requiredtool('fdtget')
-def test_fit_auto_signed(u_boot_console):
+def test_fit_auto_signed(ubman):
"""Test that mkimage generates auto-FIT with signatures/hashes as expected.
The mkimage tool can create auto generated (i.e. without an ITS file
@@ -133,9 +133,8 @@
The test does not run the sandbox. It only checks the host tool mkimage.
"""
- cons = u_boot_console
- mkimage = cons.config.build_dir + '/tools/mkimage'
- tempdir = os.path.join(cons.config.result_dir, 'auto_fit')
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ tempdir = os.path.join(ubman.config.result_dir, 'auto_fit')
os.makedirs(tempdir, exist_ok=True)
kernel_file = f'{tempdir}/vmlinuz'
dt1_file = f'{tempdir}/dt-1.dtb'
@@ -166,29 +165,29 @@
s_args = " -k" + tempdir + " -g" + key_name + " -o" + sign_algo
# 1 - Create auto FIT with images crc32 checksum, and verify it
- util.run_and_log(cons, mkimage + ' -fauto' + b_args + " " + fit_file)
+ utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + " " + fit_file)
- fit = SignedFitHelper(cons, fit_file)
+ fit = SignedFitHelper(ubman, fit_file)
if fit.build_nodes_sets() == 0:
raise ValueError('FIT-1 has no "/image" nor "/configuration" nodes')
fit.check_fit_crc32_images()
# 2 - Create auto FIT with signed images, and verify it
- util.run_and_log(cons, mkimage + ' -fauto' + b_args + s_args + " " +
- fit_file)
+ utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + s_args + " " +
+ fit_file)
- fit = SignedFitHelper(cons, fit_file)
+ fit = SignedFitHelper(ubman, fit_file)
if fit.build_nodes_sets() == 0:
raise ValueError('FIT-2 has no "/image" nor "/configuration" nodes')
fit.check_fit_signed_images(key_name, sign_algo, verifier)
# 3 - Create auto FIT with signed configs and hashed images, and verify it
- util.run_and_log(cons, mkimage + ' -fauto-conf' + b_args + s_args + " " +
- fit_file)
+ utils.run_and_log(ubman, mkimage + ' -fauto-conf' + b_args + s_args + " " +
+ fit_file)
- fit = SignedFitHelper(cons, fit_file)
+ fit = SignedFitHelper(ubman, fit_file)
if fit.build_nodes_sets() == 0:
raise ValueError('FIT-3 has no "/image" nor "/configuration" nodes')
diff --git a/test/py/tests/test_fit_ecdsa.py b/test/py/tests/test_fit_ecdsa.py
index cc6c0c4..3e816d6 100644
--- a/test/py/tests/test_fit_ecdsa.py
+++ b/test/py/tests/test_fit_ecdsa.py
@@ -12,27 +12,29 @@
import os
import pytest
-import u_boot_utils as util
+import utils
from Cryptodome.Hash import SHA256
from Cryptodome.PublicKey import ECC
from Cryptodome.Signature import DSS
class SignableFitImage(object):
""" Helper to manipulate a FIT image on disk """
- def __init__(self, cons, file_name):
+ def __init__(self, ubman, file_name):
self.fit = file_name
- self.cons = cons
+ self.ubman = ubman
self.signable_nodes = set()
def __fdt_list(self, path):
- return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}')
+ return utils.run_and_log(self.ubman, f'fdtget -l {self.fit} {path}')
def __fdt_set(self, node, **prop_value):
for prop, value in prop_value.items():
- util.run_and_log(self.cons, f'fdtput -ts {self.fit} {node} {prop} {value}')
+ utils.run_and_log(self.ubman,
+ f'fdtput -ts {self.fit} {node} {prop} {value}')
def __fdt_get_binary(self, node, prop):
- numbers = util.run_and_log(self.cons, f'fdtget -tbi {self.fit} {node} {prop}')
+ numbers = utils.run_and_log(self.ubman,
+ f'fdtget -tbi {self.fit} {node} {prop}')
bignum = bytearray()
for little_num in numbers.split():
@@ -53,7 +55,7 @@
self.__fdt_set(f'{image}/signature', algo='sha256,ecdsa256')
def sign(self, mkimage, key_file):
- util.run_and_log(self.cons, [mkimage, '-F', self.fit, f'-G{key_file}'])
+ utils.run_and_log(self.ubman, [mkimage, '-F', self.fit, f'-G{key_file}'])
def check_signatures(self, key):
for image in self.signable_nodes:
@@ -69,23 +71,22 @@
@pytest.mark.requiredtool('dtc')
@pytest.mark.requiredtool('fdtget')
@pytest.mark.requiredtool('fdtput')
-def test_fit_ecdsa(u_boot_console):
+def test_fit_ecdsa(ubman):
""" Test that signatures generated by mkimage are legible. """
def generate_ecdsa_key():
return ECC.generate(curve='prime256v1')
def assemble_fit_image(dest_fit, its, destdir):
dtc_args = f'-I dts -O dtb -i {destdir}'
- util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
+ utils.run_and_log(ubman, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
def dtc(dts):
dtb = dts.replace('.dts', '.dtb')
- util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
+ utils.run_and_log(ubman, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
- cons = u_boot_console
- mkimage = cons.config.build_dir + '/tools/mkimage'
- datadir = cons.config.source_dir + '/test/py/tests/vboot/'
- tempdir = os.path.join(cons.config.result_dir, 'ecdsa')
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
+ tempdir = os.path.join(ubman.config.result_dir, 'ecdsa')
os.makedirs(tempdir, exist_ok=True)
key_file = f'{tempdir}/ecdsa-test-key.pem'
fit_file = f'{tempdir}/test.fit'
@@ -103,7 +104,7 @@
assemble_fit_image(fit_file, f'{datadir}/sign-images-sha256.its', tempdir)
- fit = SignableFitImage(cons, fit_file)
+ fit = SignableFitImage(ubman, fit_file)
nodes = fit.find_signable_image_nodes()
if len(nodes) == 0:
raise ValueError('FIT image has no "/image" nodes with "signature"')
diff --git a/test/py/tests/test_fit_hashes.py b/test/py/tests/test_fit_hashes.py
index 4891e77..07bf0fd 100644
--- a/test/py/tests/test_fit_hashes.py
+++ b/test/py/tests/test_fit_hashes.py
@@ -12,7 +12,7 @@
import os
import pytest
-import u_boot_utils as util
+import utils
kernel_hashes = {
"sha512" : "f18c1486a2c29f56360301576cdfce4dfd8e8e932d0ed8e239a1f314b8ae1d77b2a58cd7fe32e4075e69448e623ce53b0b6aa6ce5626d2c189a5beae29a68d93",
@@ -26,20 +26,21 @@
class ReadonlyFitImage(object):
""" Helper to manipulate a FIT image on disk """
- def __init__(self, cons, file_name):
+ def __init__(self, ubman, file_name):
self.fit = file_name
- self.cons = cons
+ self.ubman = ubman
self.hashable_nodes = set()
def __fdt_list(self, path):
- return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}')
+ return utils.run_and_log(self.ubman, f'fdtget -l {self.fit} {path}')
def __fdt_get(self, node, prop):
- val = util.run_and_log(self.cons, f'fdtget {self.fit} {node} {prop}')
+ val = utils.run_and_log(self.ubman, f'fdtget {self.fit} {node} {prop}')
return val.rstrip('\n')
def __fdt_get_sexadecimal(self, node, prop):
- numbers = util.run_and_log(self.cons, f'fdtget -tbx {self.fit} {node} {prop}')
+ numbers = utils.run_and_log(self.ubman,
+ f'fdtget -tbx {self.fit} {node} {prop}')
sexadecimal = ''
for num in numbers.rstrip('\n').split(' '):
@@ -80,21 +81,21 @@
@pytest.mark.requiredtool('dtc')
@pytest.mark.requiredtool('fdtget')
@pytest.mark.requiredtool('fdtput')
-def test_mkimage_hashes(u_boot_console):
+def test_mkimage_hashes(ubman):
""" Test that hashes generated by mkimage are correct. """
def assemble_fit_image(dest_fit, its, destdir):
dtc_args = f'-I dts -O dtb -i {destdir}'
- util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
+ utils.run_and_log(ubman, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
def dtc(dts):
dtb = dts.replace('.dts', '.dtb')
- util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
+ utils.run_and_log(ubman,
+ f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
- cons = u_boot_console
- mkimage = cons.config.build_dir + '/tools/mkimage'
- datadir = cons.config.source_dir + '/test/py/tests/vboot/'
- tempdir = os.path.join(cons.config.result_dir, 'hashes')
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
+ tempdir = os.path.join(ubman.config.result_dir, 'hashes')
os.makedirs(tempdir, exist_ok=True)
fit_file = f'{tempdir}/test.fit'
@@ -106,7 +107,7 @@
assemble_fit_image(fit_file, f'{datadir}/hash-images.its', tempdir)
- fit = ReadonlyFitImage(cons, fit_file)
+ fit = ReadonlyFitImage(ubman, fit_file)
nodes = fit.find_hashable_image_nodes()
if len(nodes) == 0:
raise ValueError('FIT image has no "/image" nodes with "hash-..."')
diff --git a/test/py/tests/test_fpga.py b/test/py/tests/test_fpga.py
index 460ff22..74cd42b 100644
--- a/test/py/tests/test_fpga.py
+++ b/test/py/tests/test_fpga.py
@@ -8,7 +8,7 @@
import pytest
import re
import random
-import u_boot_utils
+import utils
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -63,8 +63,8 @@
import test_net
-def check_dev(u_boot_console):
- f = u_boot_console.config.env.get('env__fpga_under_test', None)
+def check_dev(ubman):
+ f = ubman.config.env.get('env__fpga_under_test', None)
if not f:
pytest.skip('No FPGA to test')
@@ -74,20 +74,20 @@
return dev, f
-def load_file_from_var(u_boot_console, name):
- dev, f = check_dev(u_boot_console)
+def load_file_from_var(ubman, name):
+ dev, f = check_dev(ubman)
addr = f.get('addr', -1)
if addr < 0:
pytest.fail('No address specified via env__fpga_under_test')
- test_net.test_net_dhcp(u_boot_console)
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_dhcp(ubman)
+ test_net.test_net_setup_static(ubman)
bit = f['%s' % (name)]
bit_size = f['%s_size' % (name)]
expected_tftp = 'Bytes transferred = %d' % bit_size
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, bit))
+ output = ubman.run_command('tftpboot %x %s' % (addr, bit))
assert expected_tftp in output
return f, dev, addr, bit, bit_size
@@ -97,158 +97,158 @@
@pytest.mark.xfail
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_fail(u_boot_console):
+def test_fpga_fail(ubman):
# Test non valid fpga subcommand
expected = 'fpga: non existing command'
- output = u_boot_console.run_command('fpga broken 0')
+ output = ubman.run_command('fpga broken 0')
#assert expected in output
assert expected_usage in output
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_help(u_boot_console):
+def test_fpga_help(ubman):
# Just show help
- output = u_boot_console.run_command('fpga')
+ output = ubman.run_command('fpga')
assert expected_usage in output
###### FPGA DUMP tests ######
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_dump(u_boot_console):
+def test_fpga_dump(ubman):
pytest.skip('Not implemented now')
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_dump_variable(u_boot_console):
+def test_fpga_dump_variable(ubman):
# Same as above but via "fpga" variable
pytest.skip('Not implemented now')
###### FPGA INFO tests ######
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info_fail(u_boot_console):
+def test_fpga_info_fail(ubman):
# Maybe this can be skipped completely
- dev, f = check_dev(u_boot_console)
+ dev, f = check_dev(ubman)
# Multiple parameters to fpga info should fail
expected = 'fpga: more parameters passed'
- output = u_boot_console.run_command('fpga info 0 0')
+ output = ubman.run_command('fpga info 0 0')
#assert expected in output
assert expected_usage in output
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info_list(u_boot_console):
+def test_fpga_info_list(ubman):
# Maybe this can be skipped completely
- dev, f = check_dev(u_boot_console)
+ dev, f = check_dev(ubman)
# Code is design in a way that if fpga dev is not passed it should
# return list of all fpga devices in the system
- u_boot_console.run_command('setenv fpga')
- output = u_boot_console.run_command('fpga info')
+ ubman.run_command('setenv fpga')
+ output = ubman.run_command('fpga info')
assert expected_usage not in output
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info(u_boot_console):
- dev, f = check_dev(u_boot_console)
+def test_fpga_info(ubman):
+ dev, f = check_dev(ubman)
- output = u_boot_console.run_command('fpga info %x' % (dev))
+ output = ubman.run_command('fpga info %x' % (dev))
assert expected_usage not in output
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info_variable(u_boot_console):
- dev, f = check_dev(u_boot_console)
+def test_fpga_info_variable(ubman):
+ dev, f = check_dev(ubman)
#
# fpga variable is storing device number which doesn't need to be passed
#
- u_boot_console.run_command('setenv fpga %x' % (dev))
+ ubman.run_command('setenv fpga %x' % (dev))
- output = u_boot_console.run_command('fpga info')
+ output = ubman.run_command('fpga info')
# Variable cleanup
- u_boot_console.run_command('setenv fpga')
+ ubman.run_command('setenv fpga')
assert expected_usage not in output
###### FPGA LOAD tests ######
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_load_fail(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
+def test_fpga_load_fail(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_load')
for cmd in ['dump', 'load', 'loadb']:
# missing dev parameter
expected = 'fpga: incorrect parameters passed'
- output = u_boot_console.run_command('fpga %s %x $filesize' % (cmd, addr))
+ output = ubman.run_command('fpga %s %x $filesize' % (cmd, addr))
#assert expected in output
assert expected_usage in output
# more parameters - 0 at the end
expected = 'fpga: more parameters passed'
- output = u_boot_console.run_command('fpga %s %x %x $filesize 0' % (cmd, dev, addr))
+ output = ubman.run_command('fpga %s %x %x $filesize 0' % (cmd, dev, addr))
#assert expected in output
assert expected_usage in output
# 0 address
expected = 'fpga: zero fpga_data address'
- output = u_boot_console.run_command('fpga %s %x 0 $filesize' % (cmd, dev))
+ output = ubman.run_command('fpga %s %x 0 $filesize' % (cmd, dev))
#assert expected in output
assert expected_usage in output
# 0 filesize
expected = 'fpga: zero size'
- output = u_boot_console.run_command('fpga %s %x %x 0' % (cmd, dev, addr))
+ output = ubman.run_command('fpga %s %x %x 0' % (cmd, dev, addr))
#assert expected in output
assert expected_usage in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_load(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
+def test_fpga_load(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_load')
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadp')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadp(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
+def test_fpga_loadp(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_load')
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
assert expected_text in output
# And load also partial bistream
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadp')
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadp')
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadp %x %x $filesize && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadp %x %x $filesize && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadb(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadb')
+def test_fpga_loadb(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadb')
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadbp')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadbp(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadb')
+def test_fpga_loadbp(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadb')
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
assert expected_text in output
# And load also partial bistream in bit format
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadbp')
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadbp')
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadbp %x %x $filesize && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadbp %x %x $filesize && echo %s' % (dev, addr, expected_text))
assert expected_text in output
###### FPGA LOADMK tests ######
@@ -257,18 +257,18 @@
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_fail(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_fail(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
# load image but pass incorrect address to show error message
expected = 'Unknown image type'
- output = u_boot_console.run_command('fpga loadmk %x %x' % (dev, addr + 0x10))
+ output = ubman.run_command('fpga loadmk %x %x' % (dev, addr + 0x10))
assert expected in output
# Pass more parameters then command expects - 0 at the end
- output = u_boot_console.run_command('fpga loadmk %x %x 0' % (dev, addr))
+ output = ubman.run_command('fpga loadmk %x %x 0' % (dev, addr))
#assert expected in output
assert expected_usage in output
@@ -276,13 +276,13 @@
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.xfail
@@ -290,53 +290,53 @@
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy_variable_fpga(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy_variable_fpga(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
- u_boot_console.run_command('setenv fpga %x' % (dev))
+ ubman.run_command('setenv fpga %x' % (dev))
# this testcase should cover case which looks like it is supported but dev pointer is broken by loading mkimage address
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x && echo %s' % (addr, expected_text))
- u_boot_console.run_command('setenv fpga')
+ output = ubman.run_command('fpga loadmk %x && echo %s' % (addr, expected_text))
+ ubman.run_command('setenv fpga')
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy_variable_fpgadata(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy_variable_fpgadata(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
- u_boot_console.run_command('setenv fpgadata %x' % (addr))
+ ubman.run_command('setenv fpgadata %x' % (addr))
# this testcase should cover case which looks like it is supported but dev pointer is broken by loading mkimage address
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
- u_boot_console.run_command('setenv fpgadata')
+ output = ubman.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
+ ubman.run_command('setenv fpgadata')
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy_variable(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy_variable(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
- u_boot_console.run_command('setenv fpga %x' % (dev))
- u_boot_console.run_command('setenv fpgadata %x' % (addr))
+ ubman.run_command('setenv fpga %x' % (dev))
+ ubman.run_command('setenv fpgadata %x' % (addr))
# this testcase should cover case which looks like it is supported but dev pointer is broken by loading mkimage address
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk && echo %s' % (expected_text))
- u_boot_console.run_command('setenv fpga')
- u_boot_console.run_command('setenv fpgadata')
+ output = ubman.run_command('fpga loadmk && echo %s' % (expected_text))
+ ubman.run_command('setenv fpga')
+ ubman.run_command('setenv fpgadata')
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@@ -344,96 +344,96 @@
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('legacy_image_format')
@pytest.mark.buildconfigspec('gzip')
-def test_fpga_loadmk_legacy_gz(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy_gz')
+def test_fpga_loadmk_legacy_gz(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy_gz')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('fit')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_external(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit_external')
+def test_fpga_loadmk_fit_external(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit_external')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('fit')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+ output = ubman.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('fit')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_variable_fpga(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit_variable_fpga(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
# FIXME this should fail - broken support in past
- u_boot_console.run_command('setenv fpga %x' % (dev))
+ ubman.run_command('setenv fpga %x' % (dev))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x:fpga && echo %s' % (addr, expected_text))
- u_boot_console.run_command('setenv fpga')
+ output = ubman.run_command('fpga loadmk %x:fpga && echo %s' % (addr, expected_text))
+ ubman.run_command('setenv fpga')
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('fit')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_variable_fpgadata(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit_variable_fpgadata(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
# FIXME this should fail - broken support in past
- u_boot_console.run_command('setenv fpgadata %x:fpga' % (addr))
+ ubman.run_command('setenv fpgadata %x:fpga' % (addr))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
- u_boot_console.run_command('setenv fpgadata')
+ output = ubman.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
+ ubman.run_command('setenv fpgadata')
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
@pytest.mark.buildconfigspec('fit')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_variable(u_boot_console):
- f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit_variable(ubman):
+ f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
- u_boot_console.run_command('imi %x' % (addr))
+ ubman.run_command('imi %x' % (addr))
- u_boot_console.run_command('setenv fpga %x' % (dev))
- u_boot_console.run_command('setenv fpgadata %x:fpga' % (addr))
+ ubman.run_command('setenv fpga %x' % (dev))
+ ubman.run_command('setenv fpgadata %x:fpga' % (addr))
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadmk && echo %s' % (expected_text))
- u_boot_console.run_command('setenv fpga')
- u_boot_console.run_command('setenv fpgadata')
+ output = ubman.run_command('fpga loadmk && echo %s' % (expected_text))
+ ubman.run_command('setenv fpga')
+ ubman.run_command('setenv fpgadata')
assert expected_text in output
###### FPGA LOAD tests ######
@pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_loadfs_fail(u_boot_console):
- dev, f = check_dev(u_boot_console)
+def test_fpga_loadfs_fail(ubman):
+ dev, f = check_dev(ubman)
addr = f.get('addr', -1)
if addr < 0:
@@ -445,49 +445,49 @@
# less params - dev number removed
expected = 'fpga: incorrect parameters passed'
- output = u_boot_console.run_command('fpga loadfs %x %x %x %s' % (addr, bit_size, block_size, bit))
+ output = ubman.run_command('fpga loadfs %x %x %x %s' % (addr, bit_size, block_size, bit))
#assert expected in output
assert expected_usage in output
# one more param - 0 at the end
# This is the longest command that's why there is no message from cmd/fpga.c
- output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s 0' % (dev, addr, bit_size, block_size, bit))
+ output = ubman.run_command('fpga loadfs %x %x %x %x %s 0' % (dev, addr, bit_size, block_size, bit))
assert expected_usage in output
# zero address 0
expected = 'fpga: zero fpga_data address'
- output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s' % (dev, 0, bit_size, block_size, bit))
+ output = ubman.run_command('fpga loadfs %x %x %x %x %s' % (dev, 0, bit_size, block_size, bit))
#assert expected in output
assert expected_usage in output
# bit_size 0
expected = 'fpga: zero size'
- output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, 0, block_size, bit))
+ output = ubman.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, 0, block_size, bit))
#assert expected in output
assert expected_usage in output
# block size 0
# FIXME this should pass but it failing too
- output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, bit_size, 0, bit))
+ output = ubman.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, bit_size, 0, bit))
assert expected_usage in output
# non existing bitstream name
expected = 'Unable to read file noname'
- output = u_boot_console.run_command('fpga loadfs %x %x %x %x mmc 0 noname' % (dev, addr, bit_size, block_size))
+ output = ubman.run_command('fpga loadfs %x %x %x %x mmc 0 noname' % (dev, addr, bit_size, block_size))
assert expected in output
assert expected_usage in output
# -1 dev number
expected = 'fpga_fsload: Invalid device number -1'
- output = u_boot_console.run_command('fpga loadfs %d %x %x %x mmc 0 noname' % (-1, addr, bit_size, block_size))
+ output = ubman.run_command('fpga loadfs %d %x %x %x mmc 0 noname' % (-1, addr, bit_size, block_size))
assert expected in output
assert expected_usage in output
@pytest.mark.buildconfigspec('cmd_fpga')
@pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadfs(u_boot_console):
- dev, f = check_dev(u_boot_console)
+def test_fpga_loadfs(ubman):
+ dev, f = check_dev(ubman)
addr = f.get('addr', -1)
if addr < 0:
@@ -499,7 +499,7 @@
# This should be done better
expected_text = 'FPGA loaded successfully'
- output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s && echo %s' % (dev, addr, bit_size, block_size, bit, expected_text))
+ output = ubman.run_command('fpga loadfs %x %x %x %x %s && echo %s' % (dev, addr, bit_size, block_size, bit, expected_text))
assert expected_text in output
@pytest.mark.buildconfigspec('cmd_fpga')
@@ -507,26 +507,26 @@
@pytest.mark.buildconfigspec('cmd_net')
@pytest.mark.buildconfigspec('cmd_dhcp')
@pytest.mark.buildconfigspec('net')
-def test_fpga_secure_bit_auth(u_boot_console):
+def test_fpga_secure_bit_auth(ubman):
- test_net.test_net_dhcp(u_boot_console)
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_dhcp(ubman)
+ test_net.test_net_setup_static(ubman)
- f = u_boot_console.config.env.get('env__fpga_secure_readable_file', None)
+ f = ubman.config.env.get('env__fpga_secure_readable_file', None)
if not f:
pytest.skip('No TFTP readable file to read')
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['fn']
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (addr, fn))
assert expected_tftp in output
expected_zynqmpsecure = 'Bitstream successfully loaded'
- output = u_boot_console.run_command('fpga loads 0 %x $filesize 0 2' % (addr))
+ output = ubman.run_command('fpga loads 0 %x $filesize 0 2' % (addr))
assert expected_zynqmpsecure in output
@@ -535,31 +535,31 @@
@pytest.mark.buildconfigspec('cmd_net')
@pytest.mark.buildconfigspec('cmd_dhcp')
@pytest.mark.buildconfigspec('net')
-def test_fpga_secure_bit_img_auth_kup(u_boot_console):
+def test_fpga_secure_bit_img_auth_kup(ubman):
- test_net.test_net_dhcp(u_boot_console)
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_dhcp(ubman)
+ test_net.test_net_setup_static(ubman)
- f = u_boot_console.config.env.get('env__fpga_secure_readable_file', None)
+ f = ubman.config.env.get('env__fpga_secure_readable_file', None)
if not f:
pytest.skip('No TFTP readable file to read')
keyaddr = f.get('keyaddr', None)
if not keyaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
keyfn = f['keyfn']
- output = u_boot_console.run_command('tftpboot %x %s' % (keyaddr, keyfn))
+ output = ubman.run_command('tftpboot %x %s' % (keyaddr, keyfn))
assert expected_tftp in output
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['enckupfn']
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (addr, fn))
assert expected_tftp in output
expected_zynqmpsecure = 'Bitstream successfully loaded'
- output = u_boot_console.run_command('fpga loads 0 %x $filesize 0 1 %x' % (addr, keyaddr))
+ output = ubman.run_command('fpga loads 0 %x $filesize 0 1 %x' % (addr, keyaddr))
assert expected_zynqmpsecure in output
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 7bfcf41..47a584f 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -8,7 +8,6 @@
import re
from subprocess import call, check_call, check_output, CalledProcessError
from fstest_defs import *
-import u_boot_utils as util
# pylint: disable=E0611
from tests import fs_helper
diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py
index b5f4704..5a02348 100644
--- a/test/py/tests/test_fs/test_basic.py
+++ b/test/py/tests/test_fs/test_basic.py
@@ -16,110 +16,110 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestFsBasic(object):
- def test_fs1(self, u_boot_console, fs_obj_basic):
+ def test_fs1(self, ubman, fs_obj_basic):
"""
Test Case 1 - ls command, listing a root directory and invalid directory
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 1a - ls'):
+ with ubman.log.section('Test Case 1a - ls'):
# Test Case 1 - ls
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sls host 0:0' % fs_type])
assert(re.search('2621440000 *%s' % BIG_FILE, ''.join(output)))
assert(re.search('1048576 *%s' % SMALL_FILE, ''.join(output)))
- with u_boot_console.log.section('Test Case 1b - ls (invalid dir)'):
+ with ubman.log.section('Test Case 1b - ls (invalid dir)'):
# In addition, test with a nonexistent directory to see if we crash.
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 invalid_d' % fs_type)
assert('' == output)
- def test_fs2(self, u_boot_console, fs_obj_basic):
+ def test_fs2(self, ubman, fs_obj_basic):
"""
Test Case 2 - size command for a small file
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 2a - size (small)'):
+ with ubman.log.section('Test Case 2a - size (small)'):
# 1MB is 0x0010 0000
# Test Case 2a - size of small file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%ssize host 0:0 /%s' % (fs_type, SMALL_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=100000' in ''.join(output))
- with u_boot_console.log.section('Test Case 2b - size (/../<file>)'):
+ with ubman.log.section('Test Case 2b - size (/../<file>)'):
# Test Case 2b - size of small file via a path using '..'
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%ssize host 0:0 /SUBDIR/../%s' % (fs_type, SMALL_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=100000' in ''.join(output))
- def test_fs3(self, u_boot_console, fs_obj_basic):
+ def test_fs3(self, ubman, fs_obj_basic):
"""
Test Case 3 - size command for a large file
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 3 - size (large)'):
+ with ubman.log.section('Test Case 3 - size (large)'):
# 2.5GB (1024*1024*2500) is 0x9C40 0000
# Test Case 3 - size of big file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%ssize host 0:0 /%s' % (fs_type, BIG_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=9c400000' in ''.join(output))
- def test_fs4(self, u_boot_console, fs_obj_basic):
+ def test_fs4(self, ubman, fs_obj_basic):
"""
Test Case 4 - load a small file, 1MB
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 4 - load (small)'):
+ with ubman.log.section('Test Case 4 - load (small)'):
# Test Case 4a - Read full 1MB of small file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
'printenv filesize'])
assert('filesize=100000' in ''.join(output))
# Test Case 4b - Read full 1MB of small file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[0] in ''.join(output))
- def test_fs5(self, u_boot_console, fs_obj_basic):
+ def test_fs5(self, ubman, fs_obj_basic):
"""
Test Case 5 - load, reading first 1MB of 3GB file
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 5 - load (first 1MB)'):
+ with ubman.log.section('Test Case 5 - load (first 1MB)'):
# Test Case 5a - First 1MB of big file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s %x 0x0' % (fs_type, ADDR, BIG_FILE, LENGTH),
'printenv filesize'])
assert('filesize=100000' in ''.join(output))
# Test Case 5b - First 1MB of big file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[1] in ''.join(output))
- def test_fs6(self, u_boot_console, fs_obj_basic):
+ def test_fs6(self, ubman, fs_obj_basic):
"""
Test Case 6 - load, reading last 1MB of 3GB file
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 6 - load (last 1MB)'):
+ with ubman.log.section('Test Case 6 - load (last 1MB)'):
# fails for ext as no offset support
# Test Case 6a - Last 1MB of big file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s %x 0x9c300000'
% (fs_type, ADDR, BIG_FILE, LENGTH),
@@ -127,20 +127,20 @@
assert('filesize=100000' in ''.join(output))
# Test Case 6b - Last 1MB of big file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[2] in ''.join(output))
- def test_fs7(self, u_boot_console, fs_obj_basic):
+ def test_fs7(self, ubman, fs_obj_basic):
"""
Test Case 7 - load, 1MB from the last 1MB in 2GB
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 7 - load (last 1MB in 2GB)'):
+ with ubman.log.section('Test Case 7 - load (last 1MB in 2GB)'):
# fails for ext as no offset support
# Test Case 7a - One from the last 1MB chunk of 2GB
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s %x 0x7ff00000'
% (fs_type, ADDR, BIG_FILE, LENGTH),
@@ -148,20 +148,20 @@
assert('filesize=100000' in ''.join(output))
# Test Case 7b - One from the last 1MB chunk of 2GB
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[3] in ''.join(output))
- def test_fs8(self, u_boot_console, fs_obj_basic):
+ def test_fs8(self, ubman, fs_obj_basic):
"""
Test Case 8 - load, reading first 1MB in 2GB
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 8 - load (first 1MB in 2GB)'):
+ with ubman.log.section('Test Case 8 - load (first 1MB in 2GB)'):
# fails for ext as no offset support
# Test Case 8a - One from the start 1MB chunk from 2GB
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s %x 0x80000000'
% (fs_type, ADDR, BIG_FILE, LENGTH),
@@ -169,20 +169,20 @@
assert('filesize=100000' in ''.join(output))
# Test Case 8b - One from the start 1MB chunk from 2GB
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[4] in ''.join(output))
- def test_fs9(self, u_boot_console, fs_obj_basic):
+ def test_fs9(self, ubman, fs_obj_basic):
"""
Test Case 9 - load, 1MB crossing 2GB boundary
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 9 - load (crossing 2GB boundary)'):
+ with ubman.log.section('Test Case 9 - load (crossing 2GB boundary)'):
# fails for ext as no offset support
# Test Case 9a - One 1MB chunk crossing the 2GB boundary
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s %x 0x7ff80000'
% (fs_type, ADDR, BIG_FILE, LENGTH),
@@ -190,20 +190,20 @@
assert('filesize=100000' in ''.join(output))
# Test Case 9b - One 1MB chunk crossing the 2GB boundary
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[5] in ''.join(output))
- def test_fs10(self, u_boot_console, fs_obj_basic):
+ def test_fs10(self, ubman, fs_obj_basic):
"""
Test Case 10 - load, reading beyond file end'):
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 10 - load (beyond file end)'):
+ with ubman.log.section('Test Case 10 - load (beyond file end)'):
# Generic failure case
# Test Case 10 - 2MB chunk from the last 1MB of big file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s 0x00200000 0x9c300000'
% (fs_type, ADDR, BIG_FILE),
@@ -212,16 +212,16 @@
'setenv filesize'])
assert('filesize=100000' in ''.join(output))
- def test_fs11(self, u_boot_console, fs_obj_basic):
+ def test_fs11(self, ubman, fs_obj_basic):
"""
Test Case 11 - write'
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 11 - write'):
+ with ubman.log.section('Test Case 11 - write'):
# Read 1MB from small file
# Write it back to test the writes
# Test Case 11a - Check that the write succeeded
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
'%swrite host 0:0 %x /%s.w $filesize'
@@ -230,39 +230,39 @@
# Test Case 11b - Check md5 of written to is same
# as the one read from
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%sload host 0:0 %x /%s.w' % (fs_type, ADDR, SMALL_FILE),
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[0] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs12(self, u_boot_console, fs_obj_basic):
+ def test_fs12(self, ubman, fs_obj_basic):
"""
Test Case 12 - write to "." directory
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 12 - write (".")'):
+ with ubman.log.section('Test Case 12 - write (".")'):
# Next test case checks writing a file whose dirent
# is the first in the block, which is always true for "."
# The write should fail, but the lookup should work
# Test Case 12 - Check directory traversal
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%swrite host 0:0 %x /. 0x10' % (fs_type, ADDR)])
assert('Unable to write' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs13(self, u_boot_console, fs_obj_basic):
+ def test_fs13(self, ubman, fs_obj_basic):
"""
Test Case 13 - write to a file with "/./<filename>"
"""
fs_type,fs_img,md5val = fs_obj_basic
- with u_boot_console.log.section('Test Case 13 - write ("./<file>")'):
+ with ubman.log.section('Test Case 13 - write ("./<file>")'):
# Read 1MB from small file
# Write it via "same directory", i.e. "." dirent
# Test Case 13a - Check directory traversal
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
'%swrite host 0:0 %x /./%s2 $filesize'
@@ -271,7 +271,7 @@
# Test Case 13b - Check md5 of written to is same
# as the one read from
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x /./%s2' % (fs_type, ADDR, SMALL_FILE),
'md5sum %x $filesize' % ADDR,
@@ -280,7 +280,7 @@
# Test Case 13c - Check md5 of written to is same
# as the one read from
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x /%s2' % (fs_type, ADDR, SMALL_FILE),
'md5sum %x $filesize' % ADDR,
diff --git a/test/py/tests/test_fs/test_erofs.py b/test/py/tests/test_fs/test_erofs.py
index 87ad8f2..a2bb6b5 100644
--- a/test/py/tests/test_fs/test_erofs.py
+++ b/test/py/tests/test_fs/test_erofs.py
@@ -65,64 +65,64 @@
image_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
os.remove(image_path)
-def erofs_ls_at_root(u_boot_console):
+def erofs_ls_at_root(ubman):
"""
Test if all the present files and directories were listed.
"""
- no_slash = u_boot_console.run_command('erofsls host 0')
- slash = u_boot_console.run_command('erofsls host 0 /')
+ no_slash = ubman.run_command('erofsls host 0')
+ slash = ubman.run_command('erofsls host 0 /')
assert no_slash == slash
expected_lines = ['./', '../', '4096 f4096', '7812 f7812', 'subdir/',
'<SYM> symdir', '<SYM> symfile', '4 file(s), 3 dir(s)']
- output = u_boot_console.run_command('erofsls host 0')
+ output = ubman.run_command('erofsls host 0')
for line in expected_lines:
assert line in output
-def erofs_ls_at_subdir(u_boot_console):
+def erofs_ls_at_subdir(ubman):
"""
Test if the path resolution works.
"""
expected_lines = ['./', '../', '100 subdir-file', '1 file(s), 2 dir(s)']
- output = u_boot_console.run_command('erofsls host 0 subdir')
+ output = ubman.run_command('erofsls host 0 subdir')
for line in expected_lines:
assert line in output
-def erofs_ls_at_symlink(u_boot_console):
+def erofs_ls_at_symlink(ubman):
"""
Test if the symbolic link's target resolution works.
"""
- output = u_boot_console.run_command('erofsls host 0 symdir')
- output_subdir = u_boot_console.run_command('erofsls host 0 subdir')
+ output = ubman.run_command('erofsls host 0 symdir')
+ output_subdir = ubman.run_command('erofsls host 0 subdir')
assert output == output_subdir
expected_lines = ['./', '../', '100 subdir-file', '1 file(s), 2 dir(s)']
for line in expected_lines:
assert line in output
-def erofs_ls_at_non_existent_dir(u_boot_console):
+def erofs_ls_at_non_existent_dir(ubman):
"""
Test if the EROFS support will crash when get a nonexistent directory.
"""
- out_non_existent = u_boot_console.run_command('erofsls host 0 fff')
- out_not_dir = u_boot_console.run_command('erofsls host 0 f1000')
+ out_non_existent = ubman.run_command('erofsls host 0 fff')
+ out_not_dir = ubman.run_command('erofsls host 0 f1000')
assert out_non_existent == out_not_dir
assert '' in out_non_existent
-def erofs_load_files(u_boot_console, files, sizes, address):
+def erofs_load_files(ubman, files, sizes, address):
"""
Loads files and asserts their checksums.
"""
- build_dir = u_boot_console.config.build_dir
+ build_dir = ubman.config.build_dir
for (file, size) in zip(files, sizes):
- out = u_boot_console.run_command('erofsload host 0 {} {}'.format(address, file))
+ out = ubman.run_command('erofsload host 0 {} {}'.format(address, file))
# check if the right amount of bytes was read
assert size in out
# calculate u-boot file's checksum
- out = u_boot_console.run_command('md5sum {} {}'.format(address, hex(int(size))))
+ out = ubman.run_command('md5sum {} {}'.format(address, hex(int(size))))
u_boot_checksum = out.split()[-1]
# calculate original file's checksum
@@ -134,54 +134,54 @@
# compare checksum
assert u_boot_checksum == original_checksum
-def erofs_load_files_at_root(u_boot_console):
+def erofs_load_files_at_root(ubman):
"""
Test load file from the root directory.
"""
files = ['f4096', 'f7812']
sizes = ['4096', '7812']
address = '$kernel_addr_r'
- erofs_load_files(u_boot_console, files, sizes, address)
+ erofs_load_files(ubman, files, sizes, address)
-def erofs_load_files_at_subdir(u_boot_console):
+def erofs_load_files_at_subdir(ubman):
"""
Test load file from the subdirectory.
"""
files = ['subdir/subdir-file']
sizes = ['100']
address = '$kernel_addr_r'
- erofs_load_files(u_boot_console, files, sizes, address)
+ erofs_load_files(ubman, files, sizes, address)
-def erofs_load_files_at_symlink(u_boot_console):
+def erofs_load_files_at_symlink(ubman):
"""
Test load file from the symlink.
"""
files = ['symfile']
sizes = ['7812']
address = '$kernel_addr_r'
- erofs_load_files(u_boot_console, files, sizes, address)
+ erofs_load_files(ubman, files, sizes, address)
-def erofs_load_non_existent_file(u_boot_console):
+def erofs_load_non_existent_file(ubman):
"""
Test if the EROFS support will crash when load a nonexistent file.
"""
address = '$kernel_addr_r'
file = 'non-existent'
- out = u_boot_console.run_command('erofsload host 0 {} {}'.format(address, file))
+ out = ubman.run_command('erofsload host 0 {} {}'.format(address, file))
assert 'Failed to load' in out
-def erofs_run_all_tests(u_boot_console):
+def erofs_run_all_tests(ubman):
"""
Runs all test cases.
"""
- erofs_ls_at_root(u_boot_console)
- erofs_ls_at_subdir(u_boot_console)
- erofs_ls_at_symlink(u_boot_console)
- erofs_ls_at_non_existent_dir(u_boot_console)
- erofs_load_files_at_root(u_boot_console)
- erofs_load_files_at_subdir(u_boot_console)
- erofs_load_files_at_symlink(u_boot_console)
- erofs_load_non_existent_file(u_boot_console)
+ erofs_ls_at_root(ubman)
+ erofs_ls_at_subdir(ubman)
+ erofs_ls_at_symlink(ubman)
+ erofs_ls_at_non_existent_dir(ubman)
+ erofs_load_files_at_root(ubman)
+ erofs_load_files_at_subdir(ubman)
+ erofs_load_files_at_symlink(ubman)
+ erofs_load_non_existent_file(ubman)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_fs_generic')
@@ -190,11 +190,11 @@
@pytest.mark.requiredtool('mkfs.erofs')
@pytest.mark.requiredtool('md5sum')
-def test_erofs(u_boot_console):
+def test_erofs(ubman):
"""
Executes the erofs test suite.
"""
- build_dir = u_boot_console.config.build_dir
+ build_dir = ubman.config.build_dir
# If the EFI subsystem is enabled and initialized, EFI subsystem tries to
# add EFI boot option when the new disk is detected. If there is no EFI
@@ -203,15 +203,15 @@
# Restart U-Boot to clear the previous state.
# TODO: Ideally EFI test cases need to be fixed, but it will
# increase the number of system reset.
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
try:
# setup test environment
make_erofs_image(build_dir)
image_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
- u_boot_console.run_command('host bind 0 {}'.format(image_path))
+ ubman.run_command('host bind 0 {}'.format(image_path))
# run all tests
- erofs_run_all_tests(u_boot_console)
+ erofs_run_all_tests(ubman)
except:
clean_erofs_image(build_dir)
raise AssertionError
diff --git a/test/py/tests/test_fs/test_ext.py b/test/py/tests/test_fs/test_ext.py
index 05fefa5..9c213f2 100644
--- a/test/py/tests/test_fs/test_ext.py
+++ b/test/py/tests/test_fs/test_ext.py
@@ -29,14 +29,14 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestFsExt(object):
- def test_fs_ext1(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext1(self, ubman, fs_obj_ext):
"""
Test Case 1 - write a file with absolute path
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 1 - write with abs path'):
+ with ubman.log.section('Test Case 1 - write with abs path'):
# Test Case 1a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w1 $filesize'
@@ -44,7 +44,7 @@
assert('20480 bytes written' in ''.join(output))
# Test Case 1b - Check md5 of file content
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x /dir1/%s.w1' % (fs_type, ADDR, MIN_FILE),
'md5sum %x $filesize' % ADDR,
@@ -52,14 +52,14 @@
assert(md5val[0] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext2(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext2(self, ubman, fs_obj_ext):
"""
Test Case 2 - write to a file with relative path
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 2 - write with rel path'):
+ with ubman.log.section('Test Case 2 - write with rel path'):
# Test Case 2a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x dir1/%s.w2 $filesize'
@@ -67,7 +67,7 @@
assert('20480 bytes written' in ''.join(output))
# Test Case 2b - Check md5 of file content
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x dir1/%s.w2' % (fs_type, ADDR, MIN_FILE),
'md5sum %x $filesize' % ADDR,
@@ -75,14 +75,14 @@
assert(md5val[0] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext3(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext3(self, ubman, fs_obj_ext):
"""
Test Case 3 - write to a file with invalid path
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 3 - write with invalid path'):
+ with ubman.log.section('Test Case 3 - write with invalid path'):
# Test Case 3 - Check if command expectedly failed
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/none/%s.w3 $filesize'
@@ -90,32 +90,32 @@
assert('Unable to write file /dir1/none/' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext4(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext4(self, ubman, fs_obj_ext):
"""
Test Case 4 - write at non-zero offset, enlarging file size
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 4 - write at non-zero offset, enlarging file size'):
+ with ubman.log.section('Test Case 4 - write at non-zero offset, enlarging file size'):
# Test Case 4a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w4 $filesize'
% (fs_type, ADDR, MIN_FILE)])
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/%s.w4 $filesize 0x1400'
% (fs_type, ADDR, MIN_FILE))
assert('20480 bytes written' in output)
# Test Case 4b - Check size of written file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%ssize host 0:0 /dir1/%s.w4' % (fs_type, MIN_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=6400' in ''.join(output))
# Test Case 4c - Check md5 of file content
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x /dir1/%s.w4' % (fs_type, ADDR, MIN_FILE),
'md5sum %x $filesize' % ADDR,
@@ -123,32 +123,32 @@
assert(md5val[1] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext5(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext5(self, ubman, fs_obj_ext):
"""
Test Case 5 - write at non-zero offset, shrinking file size
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 5 - write at non-zero offset, shrinking file size'):
+ with ubman.log.section('Test Case 5 - write at non-zero offset, shrinking file size'):
# Test Case 5a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w5 $filesize'
% (fs_type, ADDR, MIN_FILE)])
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/%s.w5 0x1400 0x1400'
% (fs_type, ADDR, MIN_FILE))
assert('5120 bytes written' in output)
# Test Case 5b - Check size of written file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%ssize host 0:0 /dir1/%s.w5' % (fs_type, MIN_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=2800' in ''.join(output))
# Test Case 5c - Check md5 of file content
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x /dir1/%s.w5' % (fs_type, ADDR, MIN_FILE),
'md5sum %x $filesize' % ADDR,
@@ -156,57 +156,57 @@
assert(md5val[2] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext6(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext6(self, ubman, fs_obj_ext):
"""
Test Case 6 - write nothing at the start, truncating to zero
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 6 - write nothing at the start, truncating to zero'):
+ with ubman.log.section('Test Case 6 - write nothing at the start, truncating to zero'):
# Test Case 6a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w6 $filesize'
% (fs_type, ADDR, MIN_FILE)])
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/%s.w6 0 0'
% (fs_type, ADDR, MIN_FILE))
assert('0 bytes written' in output)
# Test Case 6b - Check size of written file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%ssize host 0:0 /dir1/%s.w6' % (fs_type, MIN_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=0' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext7(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext7(self, ubman, fs_obj_ext):
"""
Test Case 7 - write at the end (append)
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 7 - write at the end (append)'):
+ with ubman.log.section('Test Case 7 - write at the end (append)'):
# Test Case 7a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w7 $filesize'
% (fs_type, ADDR, MIN_FILE)])
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/%s.w7 $filesize $filesize'
% (fs_type, ADDR, MIN_FILE))
assert('20480 bytes written' in output)
# Test Case 7b - Check size of written file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%ssize host 0:0 /dir1/%s.w7' % (fs_type, MIN_FILE),
'printenv filesize',
'setenv filesize'])
assert('filesize=a000' in ''.join(output))
# Test Case 7c - Check md5 of file content
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'mw.b %x 00 100' % ADDR,
'%sload host 0:0 %x /dir1/%s.w7' % (fs_type, ADDR, MIN_FILE),
'md5sum %x $filesize' % ADDR,
@@ -214,32 +214,32 @@
assert(md5val[3] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext8(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext8(self, ubman, fs_obj_ext):
"""
Test Case 8 - write at offset beyond the end of file
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 8 - write beyond the end'):
+ with ubman.log.section('Test Case 8 - write beyond the end'):
# Test Case 8a - Check if command expectedly failed
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w8 $filesize'
% (fs_type, ADDR, MIN_FILE)])
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/%s.w8 0x1400 %x'
% (fs_type, ADDR, MIN_FILE, 0x100000 + 0x1400))
assert('Unable to write file /dir1' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext9(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext9(self, ubman, fs_obj_ext):
"""
Test Case 9 - write to a non-existing file at non-zero offset
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 9 - write to non-existing file with non-zero offset'):
+ with ubman.log.section('Test Case 9 - write to non-existing file with non-zero offset'):
# Test Case 9a - Check if command expectedly failed
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
'%swrite host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
@@ -247,98 +247,98 @@
assert('Unable to write file /dir1' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext10(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext10(self, ubman, fs_obj_ext):
"""
'Test Case 10 - create/delete as many directories under root directory
as amount of directory entries goes beyond one cluster size)'
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 10 - create/delete (many)'):
+ with ubman.log.section('Test Case 10 - create/delete (many)'):
# Test Case 10a - Create many files
# Please note that the size of directory entry is 32 bytes.
# So one typical cluster may holds 64 (2048/32) entries.
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'host bind 0 %s' % fs_img)
for i in range(0, 66):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /FILE0123456789_%02x 100'
% (fs_type, ADDR, i))
- output = u_boot_console.run_command('%sls host 0:0 /' % fs_type)
+ output = ubman.run_command('%sls host 0:0 /' % fs_type)
assert('FILE0123456789_00' in output)
assert('FILE0123456789_41' in output)
# Test Case 10b - Delete many files
for i in range(0, 66):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%srm host 0:0 /FILE0123456789_%02x'
% (fs_type, i))
- output = u_boot_console.run_command('%sls host 0:0 /' % fs_type)
+ output = ubman.run_command('%sls host 0:0 /' % fs_type)
assert(not 'FILE0123456789_00' in output)
assert(not 'FILE0123456789_41' in output)
# Test Case 10c - Create many files again
# Please note no.64 and 65 are intentionally re-created
for i in range(64, 128):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /FILE0123456789_%02x 100'
% (fs_type, ADDR, i))
- output = u_boot_console.run_command('%sls host 0:0 /' % fs_type)
+ output = ubman.run_command('%sls host 0:0 /' % fs_type)
assert('FILE0123456789_40' in output)
assert('FILE0123456789_79' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext11(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext11(self, ubman, fs_obj_ext):
"""
'Test Case 11 - create/delete as many directories under non-root
directory as amount of directory entries goes beyond one cluster size)'
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 11 - create/delete (many)'):
+ with ubman.log.section('Test Case 11 - create/delete (many)'):
# Test Case 11a - Create many files
# Please note that the size of directory entry is 32 bytes.
# So one typical cluster may holds 64 (2048/32) entries.
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'host bind 0 %s' % fs_img)
for i in range(0, 66):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100'
% (fs_type, ADDR, i))
- output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type)
+ output = ubman.run_command('%sls host 0:0 /dir1' % fs_type)
assert('FILE0123456789_00' in output)
assert('FILE0123456789_41' in output)
# Test Case 11b - Delete many files
for i in range(0, 66):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%srm host 0:0 /dir1/FILE0123456789_%02x'
% (fs_type, i))
- output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type)
+ output = ubman.run_command('%sls host 0:0 /dir1' % fs_type)
assert(not 'FILE0123456789_00' in output)
assert(not 'FILE0123456789_41' in output)
# Test Case 11c - Create many files again
# Please note no.64 and 65 are intentionally re-created
for i in range(64, 128):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100'
% (fs_type, ADDR, i))
- output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type)
+ output = ubman.run_command('%sls host 0:0 /dir1' % fs_type)
assert('FILE0123456789_40' in output)
assert('FILE0123456789_79' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_fs_ext12(self, u_boot_console, fs_obj_ext):
+ def test_fs_ext12(self, ubman, fs_obj_ext):
"""
Test Case 12 - write plain and mangle file
"""
fs_type,fs_img,md5val = fs_obj_ext
- with u_boot_console.log.section('Test Case 12 - write plain and mangle file'):
+ with ubman.log.section('Test Case 12 - write plain and mangle file'):
# Test Case 12a - Check if command successfully returned
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%swrite host 0:0 %x /%s 0'
% (fs_type, ADDR, PLAIN_FILE),
diff --git a/test/py/tests/test_fs/test_fs_cmd.py b/test/py/tests/test_fs/test_fs_cmd.py
index 700cf35..c925547 100644
--- a/test/py/tests/test_fs/test_fs_cmd.py
+++ b/test/py/tests/test_fs/test_fs_cmd.py
@@ -6,8 +6,8 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_fstypes(u_boot_console):
+def test_fstypes(ubman):
"""Test that `fstypes` prints a result which includes `sandbox`."""
- output = u_boot_console.run_command('fstypes')
+ output = ubman.run_command('fstypes')
assert "Supported filesystems:" in output
assert "sandbox" in output
diff --git a/test/py/tests/test_fs/test_fs_fat.py b/test/py/tests/test_fs/test_fs_fat.py
index 4009d0b..b61d8ab 100644
--- a/test/py/tests/test_fs/test_fs_fat.py
+++ b/test/py/tests/test_fs/test_fs_fat.py
@@ -14,12 +14,12 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestFsFat(object):
- def test_fs_fat1(self, u_boot_console, fs_obj_fat):
+ def test_fs_fat1(self, ubman, fs_obj_fat):
"""Test that `fstypes` prints a result which includes `sandbox`."""
fs_type,fs_img = fs_obj_fat
- with u_boot_console.log.section('Test Case 1 - fatinfo'):
+ with ubman.log.section('Test Case 1 - fatinfo'):
# Test Case 1 - ls
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'fatinfo host 0:0'])
assert(re.search('Filesystem: %s' % fs_type.upper(), ''.join(output)))
diff --git a/test/py/tests/test_fs/test_mkdir.py b/test/py/tests/test_fs/test_mkdir.py
index fa9561e..df680a8 100644
--- a/test/py/tests/test_fs/test_mkdir.py
+++ b/test/py/tests/test_fs/test_mkdir.py
@@ -14,107 +14,107 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestMkdir(object):
- def test_mkdir1(self, u_boot_console, fs_obj_mkdir):
+ def test_mkdir1(self, ubman, fs_obj_mkdir):
"""
Test Case 1 - create a directory under a root
"""
fs_type,fs_img = fs_obj_mkdir
- with u_boot_console.log.section('Test Case 1 - mkdir'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 1 - mkdir'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%smkdir host 0:0 dir1' % fs_type,
'%sls host 0:0 /' % fs_type])
assert('dir1/' in ''.join(output))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 dir1' % fs_type)
assert('./' in output)
assert('../' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_mkdir2(self, u_boot_console, fs_obj_mkdir):
+ def test_mkdir2(self, ubman, fs_obj_mkdir):
"""
Test Case 2 - create a directory under a sub-directory
"""
fs_type,fs_img = fs_obj_mkdir
- with u_boot_console.log.section('Test Case 2 - mkdir (sub-sub directory)'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 2 - mkdir (sub-sub directory)'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%smkdir host 0:0 dir1/dir2' % fs_type,
'%sls host 0:0 dir1' % fs_type])
assert('dir2/' in ''.join(output))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 dir1/dir2' % fs_type)
assert('./' in output)
assert('../' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_mkdir3(self, u_boot_console, fs_obj_mkdir):
+ def test_mkdir3(self, ubman, fs_obj_mkdir):
"""
Test Case 3 - trying to create a directory with a non-existing
path should fail
"""
fs_type,fs_img = fs_obj_mkdir
- with u_boot_console.log.section('Test Case 3 - mkdir (non-existing path)'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 3 - mkdir (non-existing path)'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%smkdir host 0:0 none/dir3' % fs_type])
assert('Unable to create a directory' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_mkdir4(self, u_boot_console, fs_obj_mkdir):
+ def test_mkdir4(self, ubman, fs_obj_mkdir):
"""
Test Case 4 - trying to create "." should fail
"""
fs_type,fs_img = fs_obj_mkdir
- with u_boot_console.log.section('Test Case 4 - mkdir (".")'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 4 - mkdir (".")'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%smkdir host 0:0 .' % fs_type])
assert('Unable to create a directory' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_mkdir5(self, u_boot_console, fs_obj_mkdir):
+ def test_mkdir5(self, ubman, fs_obj_mkdir):
"""
Test Case 5 - trying to create ".." should fail
"""
fs_type,fs_img = fs_obj_mkdir
- with u_boot_console.log.section('Test Case 5 - mkdir ("..")'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 5 - mkdir ("..")'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%smkdir host 0:0 ..' % fs_type])
assert('Unable to create a directory' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_mkdir6(self, u_boot_console, fs_obj_mkdir):
+ def test_mkdir6(self, ubman, fs_obj_mkdir):
"""
'Test Case 6 - create as many directories as amount of directory
entries goes beyond a cluster size)'
"""
fs_type,fs_img = fs_obj_mkdir
- with u_boot_console.log.section('Test Case 6 - mkdir (create many)'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 6 - mkdir (create many)'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%smkdir host 0:0 dir6' % fs_type,
'%sls host 0:0 /' % fs_type])
assert('dir6/' in ''.join(output))
for i in range(0, 20):
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%smkdir host 0:0 dir6/0123456789abcdef%02x'
% (fs_type, i))
- output = u_boot_console.run_command('%sls host 0:0 dir6' % fs_type)
+ output = ubman.run_command('%sls host 0:0 dir6' % fs_type)
assert('0123456789abcdef00/' in output)
assert('0123456789abcdef13/' in output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 dir6/0123456789abcdef13/.' % fs_type)
assert('./' in output)
assert('../' in output)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 dir6/0123456789abcdef13/..' % fs_type)
assert('0123456789abcdef00/' in output)
assert('0123456789abcdef13/' in output)
diff --git a/test/py/tests/test_fs/test_rename.py b/test/py/tests/test_fs/test_rename.py
index df2b2fd..e36cff9 100644
--- a/test/py/tests/test_fs/test_rename.py
+++ b/test/py/tests/test_fs/test_rename.py
@@ -12,360 +12,360 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestRename(object):
- def test_rename1(self, u_boot_console, fs_obj_rename):
+ def test_rename1(self, ubman, fs_obj_rename):
"""
Test Case 1 - rename a file (successful mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 1 - rename a file'):
+ with ubman.log.section('Test Case 1 - rename a file'):
d = 'test1'
src = '%s/file1' % d
dst = '%s/file2' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s' % (ADDR, dst),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('file1' not in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test1'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename2(self, u_boot_console, fs_obj_rename):
+ def test_rename2(self, ubman, fs_obj_rename):
"""
Test Case 2 - rename a file to an existing file (successful mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 2 - rename a file to an existing file'):
+ with ubman.log.section('Test Case 2 - rename a file to an existing file'):
d = 'test2'
src = '%s/file1' % d
dst = '%s/file_exist' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s' % (ADDR, dst),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('file1' not in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test2'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename3(self, u_boot_console, fs_obj_rename):
+ def test_rename3(self, ubman, fs_obj_rename):
"""
Test Case 3 - rename a directory (successful mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 3 - rename a directory'):
+ with ubman.log.section('Test Case 3 - rename a directory'):
d = 'test3'
src = '%s/dir1' % d
dst = '%s/dir2' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s/file1' % (ADDR, dst),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir1' not in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test3'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename4(self, u_boot_console, fs_obj_rename):
+ def test_rename4(self, ubman, fs_obj_rename):
"""
Test Case 4 - rename a directory to an existing directory (successful
mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 4 - rename a directory to an existing directory'):
+ with ubman.log.section('Test Case 4 - rename a directory to an existing directory'):
d = 'test4'
src = '%s/dir1' % d
dst = '%s/dir2' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s/dir1/file1' % (ADDR, dst),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir1' not in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test4'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename5(self, u_boot_console, fs_obj_rename):
+ def test_rename5(self, ubman, fs_obj_rename):
"""
Test Case 5 - rename a directory to an existing file (failed mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 5 - rename a directory to an existing file'):
+ with ubman.log.section('Test Case 5 - rename a directory to an existing file'):
d = 'test5'
src = '%s/dir1' % d
dst = '%s/file2' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir1' in ''.join(output))
assert('file2' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s' % (ADDR, dst),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test5'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename6(self, u_boot_console, fs_obj_rename):
+ def test_rename6(self, ubman, fs_obj_rename):
"""
Test Case 6 - rename a file to an existing empty directory (failed mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 6 - rename a file to an existing empty directory'):
+ with ubman.log.section('Test Case 6 - rename a file to an existing empty directory'):
d = 'test6'
src = '%s/existing' % d
dst = '%s/dir2' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s' % (ADDR, src),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir2' in ''.join(output))
assert('existing' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test6'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename7(self, u_boot_console, fs_obj_rename):
+ def test_rename7(self, ubman, fs_obj_rename):
"""
Test Case 7 - rename a directory to a non-empty directory (failed mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 7 - rename a directory to a non-empty directory'):
+ with ubman.log.section('Test Case 7 - rename a directory to a non-empty directory'):
d = 'test7'
src = '%s/dir1' % d
dst = '%s/dir2' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s/dir1/file1' % (ADDR, dst),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir1' in ''.join(output))
assert('dir2' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test7'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename8(self, u_boot_console, fs_obj_rename):
+ def test_rename8(self, ubman, fs_obj_rename):
"""
Test Case 8 - rename a directory inside itself (failed mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 8 - rename a directory inside itself'):
+ with ubman.log.section('Test Case 8 - rename a directory inside itself'):
d = 'test8'
src = '%s/dir1' % d
dst = '%s/dir1/dir1' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s/file1' % (ADDR, src),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir1' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (src),
])
assert('file1' in ''.join(output))
assert('dir1' not in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test8'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename9(self, u_boot_console, fs_obj_rename):
+ def test_rename9(self, ubman, fs_obj_rename):
"""
Test Case 9 - rename a directory inside itself with backtracks (failed
mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 9 - rename a directory inside itself with backtracks'):
+ with ubman.log.section('Test Case 9 - rename a directory inside itself with backtracks'):
d = 'test9'
src = '%s/dir1/nested' % d
dst = '%s/dir1/nested/inner/./../../../dir1/nested/inner/another' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, dst),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s/dir1' % (d),
])
assert('nested' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (src),
])
assert('inner' in ''.join(output))
assert('nested' not in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename10(self, u_boot_console, fs_obj_rename):
+ def test_rename10(self, ubman, fs_obj_rename):
"""
Test Case 10 - rename a file to itself (successful mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 10 - rename a file to itself'):
+ with ubman.log.section('Test Case 10 - rename a file to itself'):
d = 'test10'
src = '%s/file1' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, src),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s' % (ADDR, src),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('file1' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test10'] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_rename11(self, u_boot_console, fs_obj_rename):
+ def test_rename11(self, ubman, fs_obj_rename):
"""
Test Case 11 - rename a directory to itself (successful mv)
"""
fs_type, fs_img, md5val = fs_obj_rename
- with u_boot_console.log.section('Test Case 11 - rename a directory to itself'):
+ with ubman.log.section('Test Case 11 - rename a directory to itself'):
# / at the end here is intentional. Ensures trailing / doesn't
# affect mv producing an updated dst path for fs_rename
d = 'test11/'
src = '%sdir1' % d
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'mv host 0:0 %s %s' % (src, d),
])
assert('' == ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load host 0:0 %x /%s/file1' % (ADDR, src),
'printenv filesize'])
assert('filesize=400' in output)
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ls host 0:0 %s' % (d),
])
assert('dir1' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val['test11'] in ''.join(output))
diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py b/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
index 6ec6cce..33093f6 100644
--- a/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
+++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
@@ -27,11 +27,11 @@
return checksum
-def uboot_md5sum(u_boot_console, address, count):
+def uboot_md5sum(ubman, address, count):
""" Runs U-Boot's md5sum command.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
address: address where the file was loaded (e.g.: $kernel_addr_r).
count: file's size. It was named 'count' to match md5sum's respective
argument name.
@@ -39,89 +39,89 @@
The checksum of the file loaded with sqfsload as a string.
"""
- out = u_boot_console.run_command('md5sum {} {}'.format(address, count))
+ out = ubman.run_command('md5sum {} {}'.format(address, count))
checksum = out.split()[-1]
return checksum
-def sqfs_load_files(u_boot_console, files, sizes, address):
+def sqfs_load_files(ubman, files, sizes, address):
""" Loads files and asserts their checksums.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
files: list of files to be loaded.
sizes: the sizes of each file.
address: the address where the files should be loaded.
"""
- build_dir = u_boot_console.config.build_dir
+ build_dir = ubman.config.build_dir
for (file, size) in zip(files, sizes):
- out = u_boot_console.run_command('sqfsload host 0 {} {}'.format(address, file))
+ out = ubman.run_command('sqfsload host 0 {} {}'.format(address, file))
# check if the right amount of bytes was read
assert size in out
# compare original file's checksum against u-boot's
- u_boot_checksum = uboot_md5sum(u_boot_console, address, hex(int(size)))
+ u_boot_checksum = uboot_md5sum(ubman, address, hex(int(size)))
original_file_path = os.path.join(build_dir, SQFS_SRC_DIR + '/' + file)
original_checksum = original_md5sum(original_file_path)
assert u_boot_checksum == original_checksum
-def sqfs_load_files_at_root(u_boot_console):
+def sqfs_load_files_at_root(ubman):
""" Calls sqfs_load_files passing the files at the SquashFS image's root.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
files = ['f4096', 'f5096', 'f1000']
sizes = ['4096', '5096', '1000']
address = '$kernel_addr_r'
- sqfs_load_files(u_boot_console, files, sizes, address)
+ sqfs_load_files(ubman, files, sizes, address)
-def sqfs_load_files_at_subdir(u_boot_console):
+def sqfs_load_files_at_subdir(ubman):
""" Calls sqfs_load_files passing the files at the SquashFS image's subdir.
This test checks if the path resolution works, since the file is not at the
root directory.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
files = ['subdir/subdir-file']
sizes = ['100']
address = '$kernel_addr_r'
- sqfs_load_files(u_boot_console, files, sizes, address)
+ sqfs_load_files(ubman, files, sizes, address)
-def sqfs_load_non_existent_file(u_boot_console):
+def sqfs_load_non_existent_file(ubman):
""" Calls sqfs_load_files passing an non-existent file to raise an error.
This test checks if the SquashFS support won't crash if it doesn't find the
specified file.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
address = '$kernel_addr_r'
file = 'non-existent'
- out = u_boot_console.run_command('sqfsload host 0 {} {}'.format(address, file))
+ out = ubman.run_command('sqfsload host 0 {} {}'.format(address, file))
assert 'Failed to load' in out
-def sqfs_run_all_load_tests(u_boot_console):
+def sqfs_run_all_load_tests(ubman):
""" Runs all the previously defined test cases.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- sqfs_load_files_at_root(u_boot_console)
- sqfs_load_files_at_subdir(u_boot_console)
- sqfs_load_non_existent_file(u_boot_console)
+ sqfs_load_files_at_root(ubman)
+ sqfs_load_files_at_subdir(ubman)
+ sqfs_load_non_existent_file(ubman)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_fs_generic')
@pytest.mark.buildconfigspec('cmd_squashfs')
@pytest.mark.buildconfigspec('fs_squashfs')
@pytest.mark.requiredtool('mksquashfs')
-def test_sqfs_load(u_boot_console):
+def test_sqfs_load(ubman):
""" Executes the sqfsload test suite.
First, it generates the SquashFS images, then it runs the test cases and
@@ -129,9 +129,9 @@
cleaned before exiting.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- build_dir = u_boot_console.config.build_dir
+ build_dir = ubman.config.build_dir
# setup test environment
check_mksquashfs_version()
@@ -142,8 +142,8 @@
for image in STANDARD_TABLE:
try:
image_path = os.path.join(build_dir, image)
- u_boot_console.run_command('host bind 0 {}'.format(image_path))
- sqfs_run_all_load_tests(u_boot_console)
+ ubman.run_command('host bind 0 {}'.format(image_path))
+ sqfs_run_all_load_tests(ubman)
except:
clean_all_images(build_dir)
clean_sqfs_src_dir(build_dir)
diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
index a20a7d1..adda3b9 100644
--- a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
+++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
@@ -10,70 +10,70 @@
from sqfs_common import clean_sqfs_src_dir, clean_all_images
from sqfs_common import check_mksquashfs_version
-def sqfs_ls_at_root(u_boot_console):
+def sqfs_ls_at_root(ubman):
""" Runs sqfsls at image's root.
This test checks if all the present files and directories were listed. Also,
it checks if passing the slash or not changes the output, which it shouldn't.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- no_slash = u_boot_console.run_command('sqfsls host 0')
- slash = u_boot_console.run_command('sqfsls host 0 /')
+ no_slash = ubman.run_command('sqfsls host 0')
+ slash = ubman.run_command('sqfsls host 0 /')
assert no_slash == slash
expected_lines = ['empty-dir/', '1000 f1000', '4096 f4096', '5096 f5096',
'subdir/', '<SYM> sym', '4 file(s), 2 dir(s)']
- output = u_boot_console.run_command('sqfsls host 0')
+ output = ubman.run_command('sqfsls host 0')
for line in expected_lines:
assert line in output
-def sqfs_ls_at_empty_dir(u_boot_console):
+def sqfs_ls_at_empty_dir(ubman):
""" Runs sqfsls at an empty directory.
This tests checks if sqfsls will print anything other than the 'Empty directory'
message.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- assert u_boot_console.run_command('sqfsls host 0 empty-dir') == 'Empty directory.'
+ assert ubman.run_command('sqfsls host 0 empty-dir') == 'Empty directory.'
-def sqfs_ls_at_subdir(u_boot_console):
+def sqfs_ls_at_subdir(ubman):
""" Runs sqfsls at the SquashFS image's subdir.
This test checks if the path resolution works, since the directory is not the
root.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
expected_lines = ['100 subdir-file', '1 file(s), 0 dir(s)']
- output = u_boot_console.run_command('sqfsls host 0 subdir')
+ output = ubman.run_command('sqfsls host 0 subdir')
for line in expected_lines:
assert line in output
-def sqfs_ls_at_symlink(u_boot_console):
+def sqfs_ls_at_symlink(ubman):
""" Runs sqfsls at a SquashFS image's symbolic link.
This test checks if the symbolic link's target resolution works.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
# since sym -> subdir, the following outputs must be equal
- output = u_boot_console.run_command('sqfsls host 0 sym')
- output_subdir = u_boot_console.run_command('sqfsls host 0 subdir')
+ output = ubman.run_command('sqfsls host 0 sym')
+ output_subdir = ubman.run_command('sqfsls host 0 subdir')
assert output == output_subdir
expected_lines = ['100 subdir-file', '1 file(s), 0 dir(s)']
for line in expected_lines:
assert line in output
-def sqfs_ls_at_non_existent_dir(u_boot_console):
+def sqfs_ls_at_non_existent_dir(ubman):
""" Runs sqfsls at a file and at a non-existent directory.
This test checks if the SquashFS support won't crash if it doesn't find the
@@ -81,24 +81,24 @@
directory. In both cases, the output should be the same.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- out_non_existent = u_boot_console.run_command('sqfsls host 0 fff')
- out_not_dir = u_boot_console.run_command('sqfsls host 0 f1000')
+ out_non_existent = ubman.run_command('sqfsls host 0 fff')
+ out_not_dir = ubman.run_command('sqfsls host 0 f1000')
assert out_non_existent == out_not_dir
assert '** Cannot find directory. **' in out_non_existent
-def sqfs_run_all_ls_tests(u_boot_console):
+def sqfs_run_all_ls_tests(ubman):
""" Runs all the previously defined test cases.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- sqfs_ls_at_root(u_boot_console)
- sqfs_ls_at_empty_dir(u_boot_console)
- sqfs_ls_at_subdir(u_boot_console)
- sqfs_ls_at_symlink(u_boot_console)
- sqfs_ls_at_non_existent_dir(u_boot_console)
+ sqfs_ls_at_root(ubman)
+ sqfs_ls_at_empty_dir(ubman)
+ sqfs_ls_at_subdir(ubman)
+ sqfs_ls_at_symlink(ubman)
+ sqfs_ls_at_non_existent_dir(ubman)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_fs_generic')
@@ -106,7 +106,7 @@
@pytest.mark.buildconfigspec('fs_squashfs')
@pytest.mark.requiredtool('mksquashfs')
@pytest.mark.singlethread
-def test_sqfs_ls(u_boot_console):
+def test_sqfs_ls(ubman):
""" Executes the sqfsls test suite.
First, it generates the SquashFS images, then it runs the test cases and
@@ -114,9 +114,9 @@
cleaned before exiting.
Args:
- u_boot_console: provides the means to interact with U-Boot's console.
+ ubman: provides the means to interact with U-Boot's console.
"""
- build_dir = u_boot_console.config.build_dir
+ build_dir = ubman.config.build_dir
# If the EFI subsystem is enabled and initialized, EFI subsystem tries to
# add EFI boot option when the new disk is detected. If there is no EFI
@@ -125,7 +125,7 @@
# Restart U-Boot to clear the previous state.
# TODO: Ideally EFI test cases need to be fixed, but it will
# increase the number of system reset.
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
# setup test environment
check_mksquashfs_version()
@@ -136,8 +136,8 @@
for image in STANDARD_TABLE:
try:
image_path = os.path.join(build_dir, image)
- u_boot_console.run_command('host bind 0 {}'.format(image_path))
- sqfs_run_all_ls_tests(u_boot_console)
+ ubman.run_command('host bind 0 {}'.format(image_path))
+ sqfs_run_all_ls_tests(ubman)
except:
clean_all_images(build_dir)
clean_sqfs_src_dir(build_dir)
diff --git a/test/py/tests/test_fs/test_symlink.py b/test/py/tests/test_fs/test_symlink.py
index 9ced101..9ffd7e6 100644
--- a/test/py/tests/test_fs/test_symlink.py
+++ b/test/py/tests/test_fs/test_symlink.py
@@ -18,38 +18,38 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestSymlink(object):
- def test_symlink1(self, u_boot_console, fs_obj_symlink):
+ def test_symlink1(self, ubman, fs_obj_symlink):
"""
Test Case 1 - create a link. and follow it when reading
"""
fs_type, fs_img, md5val = fs_obj_symlink
- with u_boot_console.log.section('Test Case 1 - create link and read'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 1 - create link and read'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'ln host 0:0 %s /%s.link ' % (SMALL_FILE, SMALL_FILE),
])
assert('' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%sload host 0:0 %x /%s.link' % (fs_type, ADDR, SMALL_FILE),
'printenv filesize'])
assert('filesize=100000' in ''.join(output))
# Test Case 4b - Read full 1MB of small file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[0] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_symlink2(self, u_boot_console, fs_obj_symlink):
+ def test_symlink2(self, ubman, fs_obj_symlink):
"""
Test Case 2 - create chained links
"""
fs_type, fs_img, md5val = fs_obj_symlink
- with u_boot_console.log.section('Test Case 2 - create chained links'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 2 - create chained links'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'ln host 0:0 %s /%s.link1 ' % (SMALL_FILE, SMALL_FILE),
@@ -60,25 +60,25 @@
])
assert('' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%sload host 0:0 %x /%s.link3' % (fs_type, ADDR, SMALL_FILE),
'printenv filesize'])
assert('filesize=100000' in ''.join(output))
# Test Case 4b - Read full 1MB of small file
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[0] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_symlink3(self, u_boot_console, fs_obj_symlink):
+ def test_symlink3(self, ubman, fs_obj_symlink):
"""
Test Case 3 - replace file/link with link
"""
fs_type, fs_img, md5val = fs_obj_symlink
- with u_boot_console.log.section('Test Case 1 - create link and read'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 1 - create link and read'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'setenv filesize',
'ln host 0:0 %s /%s ' % (MEDIUM_FILE, SMALL_FILE),
@@ -86,45 +86,45 @@
])
assert('' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
'printenv filesize'])
assert('filesize=a00000' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[1] in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'ln host 0:0 %s.link /%s ' % (MEDIUM_FILE, SMALL_FILE),
'%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
'printenv filesize'])
assert('filesize=a00000' in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(md5val[1] in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_symlink4(self, u_boot_console, fs_obj_symlink):
+ def test_symlink4(self, ubman, fs_obj_symlink):
"""
Test Case 4 - create a broken link
"""
fs_type, fs_img, md5val = fs_obj_symlink
- with u_boot_console.log.section('Test Case 1 - create link and read'):
+ with ubman.log.section('Test Case 1 - create link and read'):
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'setenv filesize',
'ln host 0:0 nowhere /link ',
])
assert('' in ''.join(output))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload host 0:0 %x /link' %
(fs_type, ADDR))
- with u_boot_console.disable_check('error_notification'):
- output = u_boot_console.run_command('printenv filesize')
+ with ubman.disable_check('error_notification'):
+ output = ubman.run_command('printenv filesize')
assert('"filesize" not defined' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_unlink.py b/test/py/tests/test_fs/test_unlink.py
index 97aafc6..7e911f0 100644
--- a/test/py/tests/test_fs/test_unlink.py
+++ b/test/py/tests/test_fs/test_unlink.py
@@ -15,103 +15,103 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.slow
class TestUnlink(object):
- def test_unlink1(self, u_boot_console, fs_obj_unlink):
+ def test_unlink1(self, ubman, fs_obj_unlink):
"""
Test Case 1 - delete a file
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 1 - unlink (file)'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 1 - unlink (file)'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%srm host 0:0 dir1/file1' % fs_type,
'%sls host 0:0 dir1/file1' % fs_type])
assert('' == ''.join(output))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 dir1/' % fs_type)
assert(not 'file1' in output)
assert('file2' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_unlink2(self, u_boot_console, fs_obj_unlink):
+ def test_unlink2(self, ubman, fs_obj_unlink):
"""
Test Case 2 - delete many files
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 2 - unlink (many)'):
- output = u_boot_console.run_command('host bind 0 %s' % fs_img)
+ with ubman.log.section('Test Case 2 - unlink (many)'):
+ output = ubman.run_command('host bind 0 %s' % fs_img)
for i in range(0, 20):
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i),
'%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i)])
assert('' == ''.join(output))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 dir2' % fs_type)
assert('0 file(s), 2 dir(s)' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_unlink3(self, u_boot_console, fs_obj_unlink):
+ def test_unlink3(self, ubman, fs_obj_unlink):
"""
Test Case 3 - trying to delete a non-existing file should fail
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 3 - unlink (non-existing)'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 3 - unlink (non-existing)'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%srm host 0:0 dir1/nofile' % fs_type])
assert('nofile: doesn\'t exist' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_unlink4(self, u_boot_console, fs_obj_unlink):
+ def test_unlink4(self, ubman, fs_obj_unlink):
"""
Test Case 4 - delete an empty directory
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 4 - unlink (directory)'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 4 - unlink (directory)'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%srm host 0:0 dir4' % fs_type])
assert('' == ''.join(output))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls host 0:0 /' % fs_type)
assert(not 'dir4' in output)
assert_fs_integrity(fs_type, fs_img)
- def test_unlink5(self, u_boot_console, fs_obj_unlink):
+ def test_unlink5(self, ubman, fs_obj_unlink):
"""
Test Case 5 - trying to deleting a non-empty directory ".."
should fail
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 5 - unlink ("non-empty directory")'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 5 - unlink ("non-empty directory")'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%srm host 0:0 dir5' % fs_type])
assert('directory is not empty' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_unlink6(self, u_boot_console, fs_obj_unlink):
+ def test_unlink6(self, ubman, fs_obj_unlink):
"""
Test Case 6 - trying to deleting a "." should fail
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 6 - unlink (".")'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 6 - unlink (".")'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%srm host 0:0 dir5/.' % fs_type])
assert('directory is not empty' in ''.join(output))
assert_fs_integrity(fs_type, fs_img)
- def test_unlink7(self, u_boot_console, fs_obj_unlink):
+ def test_unlink7(self, ubman, fs_obj_unlink):
"""
Test Case 7 - trying to deleting a ".." should fail
"""
fs_type,fs_img = fs_obj_unlink
- with u_boot_console.log.section('Test Case 7 - unlink ("..")'):
- output = u_boot_console.run_command_list([
+ with ubman.log.section('Test Case 7 - unlink ("..")'):
+ output = ubman.run_command_list([
'host bind 0 %s' % fs_img,
'%srm host 0:0 dir5/..' % fs_type])
assert('directory is not empty' in ''.join(output))
diff --git a/test/py/tests/test_gpio.py b/test/py/tests/test_gpio.py
index 3e16e63..46b674b 100644
--- a/test/py/tests/test_gpio.py
+++ b/test/py/tests/test_gpio.py
@@ -5,7 +5,7 @@
import pytest
import time
-import u_boot_utils
+import utils
"""
test_gpio_input is intended to test the fix 4dbc107f4683.
@@ -14,51 +14,51 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_input(u_boot_console):
+def test_gpio_input(ubman):
"""Test that gpio input correctly returns the value of a gpio pin."""
- response = u_boot_console.run_command('gpio input 0; echo rc:$?')
+ response = ubman.run_command('gpio input 0; echo rc:$?')
expected_response = 'rc:0'
assert(expected_response in response)
- response = u_boot_console.run_command('gpio toggle 0; gpio input 0; echo rc:$?')
+ response = ubman.run_command('gpio toggle 0; gpio input 0; echo rc:$?')
expected_response = 'rc:1'
assert(expected_response in response)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_exit_statuses(u_boot_console):
+def test_gpio_exit_statuses(ubman):
"""Test that non-input gpio commands correctly return the command
success/failure status."""
expected_response = 'rc:0'
- response = u_boot_console.run_command('gpio clear 0; echo rc:$?')
+ response = ubman.run_command('gpio clear 0; echo rc:$?')
assert(expected_response in response)
- response = u_boot_console.run_command('gpio set 0; echo rc:$?')
+ response = ubman.run_command('gpio set 0; echo rc:$?')
assert(expected_response in response)
- response = u_boot_console.run_command('gpio toggle 0; echo rc:$?')
+ response = ubman.run_command('gpio toggle 0; echo rc:$?')
assert(expected_response in response)
- response = u_boot_console.run_command('gpio status -a; echo rc:$?')
+ response = ubman.run_command('gpio status -a; echo rc:$?')
assert(expected_response in response)
expected_response = 'rc:1'
- response = u_boot_console.run_command('gpio nonexistent-command; echo rc:$?')
+ response = ubman.run_command('gpio nonexistent-command; echo rc:$?')
assert(expected_response in response)
- response = u_boot_console.run_command('gpio input 200; echo rc:$?')
+ response = ubman.run_command('gpio input 200; echo rc:$?')
assert(expected_response in response)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_read(u_boot_console):
+def test_gpio_read(ubman):
"""Test that gpio read correctly sets the variable to the value of a gpio pin."""
- u_boot_console.run_command('gpio clear 0')
- response = u_boot_console.run_command('gpio read var 0; echo val:$var,rc:$?')
+ ubman.run_command('gpio clear 0')
+ response = ubman.run_command('gpio read var 0; echo val:$var,rc:$?')
expected_response = 'val:0,rc:0'
assert(expected_response in response)
- response = u_boot_console.run_command('gpio toggle 0; gpio read var 0; echo val:$var,rc:$?')
+ response = ubman.run_command('gpio toggle 0; gpio read var 0; echo val:$var,rc:$?')
expected_response = 'val:1,rc:0'
assert(expected_response in response)
- response = u_boot_console.run_command('setenv var; gpio read var nonexistent-gpio; echo val:$var,rc:$?')
+ response = ubman.run_command('setenv var; gpio read var nonexistent-gpio; echo val:$var,rc:$?')
expected_response = 'val:,rc:1'
assert(expected_response in response)
@@ -97,7 +97,7 @@
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_status_all_generic(u_boot_console):
+def test_gpio_status_all_generic(ubman):
"""Test the 'gpio status' command.
Displays all gpio pins available on the Board.
@@ -108,7 +108,7 @@
number of such pins and mention that count in 'gpio_str_count'.
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ f = ubman.config.env.get('env__gpio_dev_config',False)
if not f:
pytest.skip("gpio not configured")
@@ -116,14 +116,14 @@
#Display all the GPIO ports
cmd = 'gpio status -a'
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
for str_value in range(1,gpio_str_count + 1):
assert f["gpio_str_%d" %(str_value)] in response
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_set_generic(u_boot_console):
+def test_gpio_set_generic(ubman):
"""Test the 'gpio set' command.
A specific gpio pin configured by user as output
@@ -132,7 +132,7 @@
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ f = ubman.config.env.get('env__gpio_dev_config',False)
if not f:
pytest.skip("gpio not configured")
@@ -141,14 +141,14 @@
cmd = 'gpio set ' + gpio_pin_adr
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = gpio_set_value
assert good_response in response
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_clear_generic(u_boot_console):
+def test_gpio_clear_generic(ubman):
"""Test the 'gpio clear' command.
A specific gpio pin configured by user as output
@@ -156,7 +156,7 @@
'clear' option
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ f = ubman.config.env.get('env__gpio_dev_config',False)
if not f:
pytest.skip("gpio not configured")
@@ -165,13 +165,13 @@
cmd = 'gpio clear ' + gpio_pin_adr
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = gpio_clear_value
assert good_response in response
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_toggle_generic(u_boot_console):
+def test_gpio_toggle_generic(ubman):
"""Test the 'gpio toggle' command.
A specific gpio pin configured by user as output
@@ -180,7 +180,7 @@
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ f = ubman.config.env.get('env__gpio_dev_config',False)
if not f:
pytest.skip("gpio not configured")
@@ -189,18 +189,18 @@
gpio_clear_value = f['gpio_clear_value'];
cmd = 'gpio set ' + gpio_pin_adr
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = gpio_set_value
assert good_response in response
cmd = 'gpio toggle ' + gpio_pin_adr
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = gpio_clear_value
assert good_response in response
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_input_generic(u_boot_console):
+def test_gpio_input_generic(ubman):
"""Test the 'gpio input' command.
Specific gpio pins configured by user as input
@@ -208,7 +208,7 @@
is verified for logic '1' and logic '0' states
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+ f = ubman.config.env.get('env__gpio_dev_config',False)
if not f:
pytest.skip("gpio not configured")
@@ -217,7 +217,7 @@
cmd = 'gpio input ' + gpio_pin_adr
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = gpio_clear_value
assert good_response in response
@@ -227,12 +227,12 @@
cmd = 'gpio input ' + gpio_pin_adr
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = gpio_set_value
assert good_response in response
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_pins_generic(u_boot_console):
+def test_gpio_pins_generic(ubman):
"""Test various gpio related functionality, such as the input, set, clear,
and toggle for the set of gpio pin list.
@@ -241,7 +241,7 @@
commands.
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config', False)
+ f = ubman.config.env.get('env__gpio_dev_config', False)
if not f:
pytest.skip('gpio not configured')
@@ -251,31 +251,31 @@
for gpin in gpio_pins:
# gpio input
- u_boot_console.run_command(f'gpio input {gpin}')
+ ubman.run_command(f'gpio input {gpin}')
expected_response = f'{gpin}: input:'
- response = u_boot_console.run_command(f'gpio status -a {gpin}')
+ response = ubman.run_command(f'gpio status -a {gpin}')
assert expected_response in response
# gpio set
- u_boot_console.run_command(f'gpio set {gpin}')
+ ubman.run_command(f'gpio set {gpin}')
expected_response = f'{gpin}: output: 1'
- response = u_boot_console.run_command(f'gpio status -a {gpin}')
+ response = ubman.run_command(f'gpio status -a {gpin}')
assert expected_response in response
# gpio clear
- u_boot_console.run_command(f'gpio clear {gpin}')
+ ubman.run_command(f'gpio clear {gpin}')
expected_response = f'{gpin}: output: 0'
- response = u_boot_console.run_command(f'gpio status -a {gpin}')
+ response = ubman.run_command(f'gpio status -a {gpin}')
assert expected_response in response
# gpio toggle
- u_boot_console.run_command(f'gpio toggle {gpin}')
+ ubman.run_command(f'gpio toggle {gpin}')
expected_response = f'{gpin}: output: 1'
- response = u_boot_console.run_command(f'gpio status -a {gpin}')
+ response = ubman.run_command(f'gpio status -a {gpin}')
assert expected_response in response
@pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_pins_input_output_generic(u_boot_console):
+def test_gpio_pins_input_output_generic(ubman):
"""Test gpio related functionality such as input and output for the list of
shorted gpio pins provided as a pair of input and output pins. This test
will fail, if the gpio pins are not shorted properly.
@@ -285,7 +285,7 @@
pair to be tested for gpio input output case.
"""
- f = u_boot_console.config.env.get('env__gpio_dev_config', False)
+ f = ubman.config.env.get('env__gpio_dev_config', False)
if not f:
pytest.skip('gpio not configured')
@@ -294,22 +294,22 @@
pytest.skip('gpio pin list for input and output are not configured')
for gpins in gpio_pins:
- u_boot_console.run_command(f'gpio input {gpins[0]}')
+ ubman.run_command(f'gpio input {gpins[0]}')
expected_response = f'{gpins[0]}: input:'
- response = u_boot_console.run_command(f'gpio status -a {gpins[0]}')
+ response = ubman.run_command(f'gpio status -a {gpins[0]}')
assert expected_response in response
- u_boot_console.run_command(f'gpio set {gpins[1]}')
+ ubman.run_command(f'gpio set {gpins[1]}')
expected_response = f'{gpins[1]}: output:'
- response = u_boot_console.run_command(f'gpio status -a {gpins[1]}')
+ response = ubman.run_command(f'gpio status -a {gpins[1]}')
assert expected_response in response
- u_boot_console.run_command(f'gpio clear {gpins[1]}')
+ ubman.run_command(f'gpio clear {gpins[1]}')
expected_response = f'{gpins[0]}: input: 0'
- response = u_boot_console.run_command(f'gpio status -a {gpins[0]}')
+ response = ubman.run_command(f'gpio status -a {gpins[0]}')
assert expected_response in response
- u_boot_console.run_command(f'gpio set {gpins[1]}')
+ ubman.run_command(f'gpio set {gpins[1]}')
expected_response = f'{gpins[0]}: input: 1'
- response = u_boot_console.run_command(f'gpio status -a {gpins[0]}')
+ response = ubman.run_command(f'gpio status -a {gpins[0]}')
assert expected_response in response
diff --git a/test/py/tests/test_gpt.py b/test/py/tests/test_gpt.py
index 6e135b6..cfc8f13 100644
--- a/test/py/tests/test_gpt.py
+++ b/test/py/tests/test_gpt.py
@@ -6,7 +6,7 @@
import os
import pytest
-import u_boot_utils
+import utils
"""
These tests rely on a 4 MB disk image, which is automatically created by
@@ -48,11 +48,11 @@
class GptTestDiskImage(object):
"""Disk Image used by the GPT tests."""
- def __init__(self, u_boot_console):
+ def __init__(self, ubman):
"""Initialize a new GptTestDiskImage object.
Args:
- u_boot_console: A U-Boot console.
+ ubman: A U-Boot console.
Returns:
Nothing.
@@ -60,62 +60,62 @@
filename = 'test_gpt_disk_image.bin'
- persistent = u_boot_console.config.persistent_data_dir + '/' + filename
- self.path = u_boot_console.config.result_dir + '/' + filename
+ persistent = ubman.config.persistent_data_dir + '/' + filename
+ self.path = ubman.config.result_dir + '/' + filename
- with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
+ with utils.persistent_file_helper(ubman.log, persistent):
if os.path.exists(persistent):
- u_boot_console.log.action('Disk image file ' + persistent +
+ ubman.log.action('Disk image file ' + persistent +
' already exists')
else:
- u_boot_console.log.action('Generating ' + persistent)
+ ubman.log.action('Generating ' + persistent)
fd = os.open(persistent, os.O_RDWR | os.O_CREAT)
os.ftruncate(fd, 4194304)
os.close(fd)
cmd = ('sgdisk',
'--disk-guid=375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
persistent)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
# part1 offset 1MB size 1MB
cmd = ('sgdisk', '--new=1:2048:4095', '--change-name=1:part1',
'--partition-guid=1:33194895-67f6-4561-8457-6fdeed4f50a3',
'-A 1:set:2',
persistent)
# part2 offset 2MB size 1.5MB
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('sgdisk', '--new=2:4096:7167', '--change-name=2:part2',
'--partition-guid=2:cc9c6e4a-6551-4cb5-87be-3210f96c86fb',
persistent)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('sgdisk', '--load-backup=' + persistent)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
cmd = ('cp', persistent, self.path)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
@pytest.fixture(scope='function')
-def state_disk_image(u_boot_console):
+def state_disk_image(ubman):
"""pytest fixture to provide a GptTestDiskImage object to tests.
- This is function-scoped because it uses u_boot_console, which is also
+ This is function-scoped because it uses ubman, which is also
function-scoped. A new disk is returned each time to prevent tests from
interfering with each other."""
- return GptTestDiskImage(u_boot_console)
+ return GptTestDiskImage(ubman)
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_read(state_disk_image, u_boot_console):
+def test_gpt_read(state_disk_image, ubman):
"""Test the gpt read command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt read host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt read host 0')
assert 'Start 1MiB, size 1MiB' in output
assert 'Block size 512, name part1' in output
assert 'Start 2MiB, size 1MiB' in output
assert 'Block size 512, name part2' in output
- output = u_boot_console.run_command('part list host 0')
+ output = ubman.run_command('part list host 0')
assert '0x00000800 0x00000fff "part1"' in output
assert '0x00001000 0x00001bff "part2"' in output
@@ -123,14 +123,14 @@
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.buildconfigspec('partition_type_guid')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_read_var(state_disk_image, u_boot_console):
+def test_gpt_read_var(state_disk_image, ubman):
"""Test the gpt read command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt read host 0 gpt_parts')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt read host 0 gpt_parts')
assert 'success!' in output
- output = u_boot_console.run_command('echo ${gpt_parts}')
+ output = ubman.run_command('echo ${gpt_parts}')
parts = parse_gpt_parts(output.rstrip())
assert parts == [
@@ -157,99 +157,99 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_verify(state_disk_image, u_boot_console):
+def test_gpt_verify(state_disk_image, ubman):
"""Test the gpt verify command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt verify host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt verify host 0')
assert 'Verify GPT: success!' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_repair(state_disk_image, u_boot_console):
+def test_gpt_repair(state_disk_image, ubman):
"""Test the gpt repair command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt repair host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt repair host 0')
assert 'Repairing GPT: success!' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_guid(state_disk_image, u_boot_console):
+def test_gpt_guid(state_disk_image, ubman):
"""Test the gpt guid command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt guid host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt guid host 0')
assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_setenv(state_disk_image, u_boot_console):
+def test_gpt_setenv(state_disk_image, ubman):
"""Test the gpt setenv command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt setenv host 0 part1')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt setenv host 0 part1')
assert 'success!' in output
- output = u_boot_console.run_command('echo ${gpt_partition_addr}')
+ output = ubman.run_command('echo ${gpt_partition_addr}')
assert output.rstrip() == '800'
- output = u_boot_console.run_command('echo ${gpt_partition_size}')
+ output = ubman.run_command('echo ${gpt_partition_size}')
assert output.rstrip() == '800'
- output = u_boot_console.run_command('echo ${gpt_partition_name}')
+ output = ubman.run_command('echo ${gpt_partition_name}')
assert output.rstrip() == 'part1'
- output = u_boot_console.run_command('echo ${gpt_partition_entry}')
+ output = ubman.run_command('echo ${gpt_partition_entry}')
assert output.rstrip() == '1'
- output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+ output = ubman.run_command('echo ${gpt_partition_bootable}')
assert output.rstrip() == '1'
- output = u_boot_console.run_command('gpt setenv host 0 part2')
+ output = ubman.run_command('gpt setenv host 0 part2')
assert 'success!' in output
- output = u_boot_console.run_command('echo ${gpt_partition_addr}')
+ output = ubman.run_command('echo ${gpt_partition_addr}')
assert output.rstrip() == '1000'
- output = u_boot_console.run_command('echo ${gpt_partition_size}')
+ output = ubman.run_command('echo ${gpt_partition_size}')
assert output.rstrip() == 'c00'
- output = u_boot_console.run_command('echo ${gpt_partition_name}')
+ output = ubman.run_command('echo ${gpt_partition_name}')
assert output.rstrip() == 'part2'
- output = u_boot_console.run_command('echo ${gpt_partition_entry}')
+ output = ubman.run_command('echo ${gpt_partition_entry}')
assert output.rstrip() == '2'
- output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+ output = ubman.run_command('echo ${gpt_partition_bootable}')
assert output.rstrip() == '0'
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_save_guid(state_disk_image, u_boot_console):
+def test_gpt_save_guid(state_disk_image, ubman):
"""Test the gpt guid command to save GUID into a string."""
- if u_boot_console.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
pytest.skip('gpt command not supported')
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt guid host 0 newguid')
- output = u_boot_console.run_command('printenv newguid')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt guid host 0 newguid')
+ output = ubman.run_command('printenv newguid')
assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_part_type_uuid(state_disk_image, u_boot_console):
+def test_gpt_part_type_uuid(state_disk_image, ubman):
"""Test the gpt partittion type UUID command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('part type host 0:1')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('part type host 0:1')
assert '0fc63daf-8483-4772-8e79-3d69d8477de4' in output
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_part_type_save_uuid(state_disk_image, u_boot_console):
+def test_gpt_part_type_save_uuid(state_disk_image, ubman):
"""Test the gpt partittion type to save UUID into a string."""
- if u_boot_console.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
pytest.skip('gpt command not supported')
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('part type host 0:1 newguid')
- output = u_boot_console.run_command('printenv newguid')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('part type host 0:1 newguid')
+ output = ubman.run_command('printenv newguid')
assert '0fc63daf-8483-4772-8e79-3d69d8477de4' in output
@pytest.mark.boardspec('sandbox')
@@ -257,17 +257,17 @@
@pytest.mark.buildconfigspec('cmd_gpt_rename')
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_rename_partition(state_disk_image, u_boot_console):
+def test_gpt_rename_partition(state_disk_image, ubman):
"""Test the gpt rename command to write partition names."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- u_boot_console.run_command('gpt rename host 0 1 first')
- output = u_boot_console.run_command('gpt read host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ ubman.run_command('gpt rename host 0 1 first')
+ output = ubman.run_command('gpt read host 0')
assert 'name first' in output
- u_boot_console.run_command('gpt rename host 0 2 second')
- output = u_boot_console.run_command('gpt read host 0')
+ ubman.run_command('gpt rename host 0 2 second')
+ output = ubman.run_command('gpt read host 0')
assert 'name second' in output
- output = u_boot_console.run_command('part list host 0')
+ output = ubman.run_command('part list host 0')
assert '0x00000800 0x00000fff "first"' in output
assert '0x00001000 0x00001bff "second"' in output
@@ -276,15 +276,15 @@
@pytest.mark.buildconfigspec('cmd_gpt_rename')
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_swap_partitions(state_disk_image, u_boot_console):
+def test_gpt_swap_partitions(state_disk_image, ubman):
"""Test the gpt swap command to exchange two partition names."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('part list host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('part list host 0')
assert '0x00000800 0x00000fff "part1"' in output
assert '0x00001000 0x00001bff "part2"' in output
- u_boot_console.run_command('gpt swap host 0 part1 part2')
- output = u_boot_console.run_command('part list host 0')
+ ubman.run_command('gpt swap host 0 part1 part2')
+ output = ubman.run_command('part list host 0')
assert '0x00000800 0x00000fff "part2"' in output
assert '0x00001000 0x00001bff "part1"' in output
@@ -292,19 +292,19 @@
@pytest.mark.buildconfigspec('cmd_gpt_rename')
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_set_bootable(state_disk_image, u_boot_console):
+def test_gpt_set_bootable(state_disk_image, ubman):
"""Test the gpt set-bootable command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
parts = ('part2', 'part1')
for bootable in parts:
- output = u_boot_console.run_command(f'gpt set-bootable host 0 {bootable}')
+ output = ubman.run_command(f'gpt set-bootable host 0 {bootable}')
assert 'success!' in output
for p in parts:
- output = u_boot_console.run_command(f'gpt setenv host 0 {p}')
+ output = ubman.run_command(f'gpt setenv host 0 {p}')
assert 'success!' in output
- output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+ output = ubman.run_command('echo ${gpt_partition_bootable}')
if p == bootable:
assert output.rstrip() == '1'
else:
@@ -314,37 +314,37 @@
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_write(state_disk_image, u_boot_console):
+def test_gpt_write(state_disk_image, ubman):
"""Test the gpt write command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('gpt write host 0 "name=all,size=0"')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('gpt write host 0 "name=all,size=0"')
assert 'Writing GPT: success!' in output
- output = u_boot_console.run_command('part list host 0')
+ output = ubman.run_command('part list host 0')
assert '0x00000022 0x00001fde "all"' in output
- output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=1M,size=1M;name=second,start=0x200000,size=0x180000;"')
+ output = ubman.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=1M,size=1M;name=second,start=0x200000,size=0x180000;"')
assert 'Writing GPT: success!' in output
- output = u_boot_console.run_command('part list host 0')
+ output = ubman.run_command('part list host 0')
assert '0x00000800 0x00000fff "first"' in output
assert '0x00001000 0x00001bff "second"' in output
- output = u_boot_console.run_command('gpt guid host 0')
+ output = ubman.run_command('gpt guid host 0')
assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
@pytest.mark.buildconfigspec('cmd_gpt')
@pytest.mark.buildconfigspec('cmd_gpt_rename')
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.requiredtool('sgdisk')
-def test_gpt_transpose(state_disk_image, u_boot_console):
+def test_gpt_transpose(state_disk_image, ubman):
"""Test the gpt transpose command."""
- u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
- output = u_boot_console.run_command('part list host 0')
+ ubman.run_command('host bind 0 ' + state_disk_image.path)
+ output = ubman.run_command('part list host 0')
assert '1\t0x00000800\t0x00000fff\t"part1"' in output
assert '2\t0x00001000\t0x00001bff\t"part2"' in output
- output = u_boot_console.run_command('gpt transpose host 0 1 2')
+ output = ubman.run_command('gpt transpose host 0 1 2')
assert 'success!' in output
- output = u_boot_console.run_command('part list host 0')
+ output = ubman.run_command('part list host 0')
assert '2\t0x00000800\t0x00000fff\t"part1"' in output
assert '1\t0x00001000\t0x00001bff\t"part2"' in output
diff --git a/test/py/tests/test_handoff.py b/test/py/tests/test_handoff.py
index 038f030..becd7d7 100644
--- a/test/py/tests/test_handoff.py
+++ b/test/py/tests/test_handoff.py
@@ -8,8 +8,7 @@
@pytest.mark.boardspec('sandbox_spl')
@pytest.mark.buildconfigspec('spl')
-def test_handoff(u_boot_console):
+def test_handoff(ubman):
"""Test that of-platdata can be generated and used in sandbox"""
- cons = u_boot_console
- response = cons.run_command('sb handoff')
+ response = ubman.run_command('sb handoff')
assert ('SPL handoff magic %x' % TEST_HANDOFF_MAGIC) in response
diff --git a/test/py/tests/test_help.py b/test/py/tests/test_help.py
index 2325ff6..12cb36b 100644
--- a/test/py/tests/test_help.py
+++ b/test/py/tests/test_help.py
@@ -4,35 +4,33 @@
import pytest
-def test_help(u_boot_console):
+def test_help(ubman):
"""Test that the "help" command can be executed."""
- lines = u_boot_console.run_command('help')
- if u_boot_console.config.buildconfig.get('config_cmd_2048', 'n') == 'y':
+ lines = ubman.run_command('help')
+ if ubman.config.buildconfig.get('config_cmd_2048', 'n') == 'y':
assert lines.splitlines()[0] == "2048 - The 2048 game"
else:
assert lines.splitlines()[0] == "? - alias for 'help'"
@pytest.mark.boardspec('sandbox')
-def test_help_no_devicetree(u_boot_console):
+def test_help_no_devicetree(ubman):
try:
- cons = u_boot_console
- cons.restart_uboot_with_flags([], use_dtb=False)
- cons.run_command('help')
- output = cons.get_spawn_output().replace('\r', '')
+ ubman.restart_uboot_with_flags([], use_dtb=False)
+ ubman.run_command('help')
+ output = ubman.get_spawn_output().replace('\r', '')
assert 'print command description/usage' in output
finally:
# Restart afterward to get the normal device tree back
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
@pytest.mark.boardspec('sandbox_vpl')
-def test_vpl_help(u_boot_console):
+def test_vpl_help(ubman):
try:
- cons = u_boot_console
- cons.restart_uboot()
- cons.run_command('help')
- output = cons.get_spawn_output().replace('\r', '')
+ ubman.restart_uboot()
+ ubman.run_command('help')
+ output = ubman.get_spawn_output().replace('\r', '')
assert 'print command description/usage' in output
finally:
# Restart afterward to get the normal device tree back
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_i2c.py b/test/py/tests/test_i2c.py
index 825d0c2..69b1193 100644
--- a/test/py/tests/test_i2c.py
+++ b/test/py/tests/test_i2c.py
@@ -31,8 +31,8 @@
}
"""
-def get_i2c_test_env(u_boot_console):
- f = u_boot_console.config.env.get("env__i2c_device_test", None)
+def get_i2c_test_env(ubman):
+ f = ubman.config.env.get("env__i2c_device_test", None)
if not f:
pytest.skip("No I2C device to test!")
else:
@@ -43,34 +43,34 @@
return bus_list, probe_all
@pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_bus(u_boot_console):
- bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_bus(ubman):
+ bus_list, probe = get_i2c_test_env(ubman)
bus = random.choice(bus_list)
expected_response = f"Bus {bus}:"
- response = u_boot_console.run_command("i2c bus")
+ response = ubman.run_command("i2c bus")
assert expected_response in response
@pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_dev(u_boot_console):
- bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_dev(ubman):
+ bus_list, probe = get_i2c_test_env(ubman)
expected_response = "Current bus is"
- response = u_boot_console.run_command("i2c dev")
+ response = ubman.run_command("i2c dev")
assert expected_response in response
@pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_probe(u_boot_console):
- bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_probe(ubman):
+ bus_list, probe = get_i2c_test_env(ubman)
bus = random.choice(bus_list)
expected_response = f"Setting bus to {bus}"
- response = u_boot_console.run_command(f"i2c dev {bus}")
+ response = ubman.run_command(f"i2c dev {bus}")
assert expected_response in response
expected_response = "Valid chip addresses:"
- response = u_boot_console.run_command("i2c probe")
+ response = ubman.run_command("i2c probe")
assert expected_response in response
@pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_eeprom(u_boot_console):
- f = u_boot_console.config.env.get("env__i2c_eeprom_device_test", None)
+def test_i2c_eeprom(ubman):
+ f = ubman.config.env.get("env__i2c_eeprom_device_test", None)
if not f:
pytest.skip("No I2C eeprom to test!")
@@ -89,17 +89,17 @@
)
# Enable i2c mux bridge
- u_boot_console.run_command("i2c dev %x" % bus)
- u_boot_console.run_command("i2c probe")
- output = u_boot_console.run_command("i2c md %x 0 5" % addr)
+ ubman.run_command("i2c dev %x" % bus)
+ ubman.run_command("i2c probe")
+ output = ubman.run_command("i2c md %x 0 5" % addr)
assert value in output
@pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_probe_all_buses(u_boot_console):
- bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_probe_all_buses(ubman):
+ bus_list, probe = get_i2c_test_env(ubman)
bus = random.choice(bus_list)
expected_response = f"Bus {bus}:"
- response = u_boot_console.run_command("i2c bus")
+ response = ubman.run_command("i2c bus")
assert expected_response in response
# Get all the bus list
@@ -109,8 +109,8 @@
for dev in bus_list:
expected_response = f"Setting bus to {dev}"
- response = u_boot_console.run_command(f"i2c dev {dev}")
+ response = ubman.run_command(f"i2c dev {dev}")
assert expected_response in response
expected_response = "Valid chip addresses:"
- response = u_boot_console.run_command("i2c probe")
+ response = ubman.run_command("i2c probe")
assert expected_response in response
diff --git a/test/py/tests/test_kconfig.py b/test/py/tests/test_kconfig.py
index 0b9e6bc..0c261d4 100644
--- a/test/py/tests/test_kconfig.py
+++ b/test/py/tests/test_kconfig.py
@@ -4,33 +4,31 @@
import pytest
-import u_boot_utils as util
+import utils
# This is needed for Azure, since the default '..' directory is not writeable
TMPDIR = '/tmp/test_kconfig'
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
-def test_kconfig(u_boot_console):
+def test_kconfig(ubman):
"""Test build failures when IF_ENABLED_INT() option is not enabled"""
- cons = u_boot_console
# This detects build errors in test/lib/kconfig.c
- out = util.run_and_log(
- cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ out = utils.run_and_log(
+ ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
'-a', 'TEST_KCONFIG', '-o', TMPDIR], ignore_errors=True)
assert 'invalid_use_of_IF_ENABLED_INT' in out
assert 'invalid_use_of_CONFIG_IF_ENABLED_INT' in out
@pytest.mark.slow
@pytest.mark.boardspec('sandbox_spl')
-def test_kconfig_spl(u_boot_console):
+def test_kconfig_spl(ubman):
"""Test build failures when IF_ENABLED_INT() option is not enabled"""
- cons = u_boot_console
# This detects build errors in test/lib/kconfig_spl.c
- out = util.run_and_log(
- cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox_spl',
+ out = utils.run_and_log(
+ ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox_spl',
'-a', 'TEST_KCONFIG', '-o', TMPDIR], ignore_errors=True)
assert 'invalid_use_of_IF_ENABLED_INT' in out
diff --git a/test/py/tests/test_log.py b/test/py/tests/test_log.py
index 7980867..4558b03 100644
--- a/test/py/tests/test_log.py
+++ b/test/py/tests/test_log.py
@@ -11,7 +11,7 @@
import pytest
@pytest.mark.buildconfigspec('cmd_log')
-def test_log_format(u_boot_console):
+def test_log_format(ubman):
"""Test the 'log format' and 'log rec' commands"""
def run_with_format(fmt, expected_output):
"""Set up the log format and then write a log record
@@ -20,18 +20,17 @@
fmt: Format to use for 'log format'
expected_output: Expected output from the 'log rec' command
"""
- output = cons.run_command('log format %s' % fmt)
+ output = ubman.run_command('log format %s' % fmt)
assert output == ''
- output = cons.run_command('log rec arch notice file.c 123 func msg')
+ output = ubman.run_command('log rec arch notice file.c 123 func msg')
assert output == expected_output
- cons = u_boot_console
- with cons.log.section('format'):
- pad = int(u_boot_console.config.buildconfig.get('config_logf_func_pad'))
+ with ubman.log.section('format'):
+ pad = int(ubman.config.buildconfig.get('config_logf_func_pad'))
padding = ' ' * (pad - len('func'))
run_with_format('all', f'NOTICE.arch,file.c:123-{padding}func() msg')
- output = cons.run_command('log format')
+ output = ubman.run_command('log format')
assert output == 'Log format: clFLfm'
run_with_format('fm', f'{padding}func() msg')
@@ -42,10 +41,9 @@
@pytest.mark.buildconfigspec('debug_uart')
@pytest.mark.boardspec('sandbox')
-def test_log_dropped(u_boot_console):
+def test_log_dropped(ubman):
"""Test dropped 'log' message when debug_uart is activated"""
- cons = u_boot_console
- cons.restart_uboot()
- output = cons.get_spawn_output().replace('\r', '')
+ ubman.restart_uboot()
+ output = ubman.get_spawn_output().replace('\r', '')
assert (not 'debug: main' in output)
diff --git a/test/py/tests/test_lsblk.py b/test/py/tests/test_lsblk.py
index a719a48..babd4f9 100644
--- a/test/py/tests/test_lsblk.py
+++ b/test/py/tests/test_lsblk.py
@@ -7,8 +7,8 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('blk')
@pytest.mark.buildconfigspec('cmd_lsblk')
-def test_lsblk(u_boot_console):
+def test_lsblk(ubman):
"""Test that `lsblk` prints a result which includes `host`."""
- output = u_boot_console.run_command('lsblk')
+ output = ubman.run_command('lsblk')
assert "Block Driver" in output
assert "sandbox_host_blk" in output
diff --git a/test/py/tests/test_md.py b/test/py/tests/test_md.py
index 83e3c54..5c7bcbd 100644
--- a/test/py/tests/test_md.py
+++ b/test/py/tests/test_md.py
@@ -3,34 +3,34 @@
# Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
import pytest
-import u_boot_utils
+import utils
@pytest.mark.buildconfigspec('cmd_memory')
-def test_md(u_boot_console):
+def test_md(ubman):
"""Test that md reads memory as expected, and that memory can be modified
using the mw command."""
- ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ ram_base = utils.find_ram_base(ubman)
addr = '%08x' % ram_base
val = 'a5f09876'
expected_response = addr + ': ' + val
- u_boot_console.run_command('mw ' + addr + ' 0 10')
- response = u_boot_console.run_command('md ' + addr + ' 10')
+ ubman.run_command('mw ' + addr + ' 0 10')
+ response = ubman.run_command('md ' + addr + ' 10')
assert(not (expected_response in response))
- u_boot_console.run_command('mw ' + addr + ' ' + val)
- response = u_boot_console.run_command('md ' + addr + ' 10')
+ ubman.run_command('mw ' + addr + ' ' + val)
+ response = ubman.run_command('md ' + addr + ' 10')
assert(expected_response in response)
@pytest.mark.buildconfigspec('cmd_memory')
-def test_md_repeat(u_boot_console):
+def test_md_repeat(ubman):
"""Test command repeat (via executing an empty command) operates correctly
for "md"; the command must repeat and dump an incrementing address."""
- ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ ram_base = utils.find_ram_base(ubman)
addr_base = '%08x' % ram_base
words = 0x10
addr_repeat = '%08x' % (ram_base + (words * 4))
- u_boot_console.run_command('md %s %x' % (addr_base, words))
- response = u_boot_console.run_command('')
+ ubman.run_command('md %s %x' % (addr_base, words))
+ response = ubman.run_command('')
expected_response = addr_repeat + ': '
assert(expected_response in response)
diff --git a/test/py/tests/test_mdio.py b/test/py/tests/test_mdio.py
index 89711e7..5345f1f 100644
--- a/test/py/tests/test_mdio.py
+++ b/test/py/tests/test_mdio.py
@@ -22,8 +22,8 @@
}
"""
-def get_mdio_test_env(u_boot_console):
- f = u_boot_console.config.env.get("env__mdio_util_test", None)
+def get_mdio_test_env(ubman):
+ f = ubman.config.env.get("env__mdio_util_test", None)
if not f or len(f) == 0:
pytest.skip("No PHY device to test!")
else:
@@ -31,9 +31,9 @@
@pytest.mark.buildconfigspec("cmd_mii")
@pytest.mark.buildconfigspec("phylib")
-def test_mdio_list(u_boot_console):
- f = get_mdio_test_env(u_boot_console)
- output = u_boot_console.run_command("mdio list")
+def test_mdio_list(ubman):
+ f = get_mdio_test_env(ubman)
+ output = ubman.run_command("mdio list")
for dev, val in f.items():
phy_addr = val.get("phy_addr")
dev_name = val.get("device_name")
@@ -43,24 +43,24 @@
@pytest.mark.buildconfigspec("cmd_mii")
@pytest.mark.buildconfigspec("phylib")
-def test_mdio_read(u_boot_console):
- f = get_mdio_test_env(u_boot_console)
- output = u_boot_console.run_command("mdio list")
+def test_mdio_read(ubman):
+ f = get_mdio_test_env(ubman)
+ output = ubman.run_command("mdio list")
for dev, val in f.items():
phy_addr = hex(val.get("phy_addr"))
dev_name = val.get("device_name")
reg = hex(val.get("reg"))
reg_val = hex(val.get("reg_val"))
- output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+ output = ubman.run_command(f"mdio read {phy_addr} {reg}")
assert f"PHY at address {int(phy_addr, 16):x}:" in output
assert f"{int(reg, 16):x} - {reg_val}" in output
@pytest.mark.buildconfigspec("cmd_mii")
@pytest.mark.buildconfigspec("phylib")
-def test_mdio_write(u_boot_console):
- f = get_mdio_test_env(u_boot_console)
- output = u_boot_console.run_command("mdio list")
+def test_mdio_write(ubman):
+ f = get_mdio_test_env(ubman)
+ output = ubman.run_command("mdio list")
for dev, val in f.items():
phy_addr = hex(val.get("phy_addr"))
dev_name = val.get("device_name")
@@ -68,12 +68,12 @@
reg_val = hex(val.get("reg_val"))
wr_val = hex(val.get("write_val"))
- u_boot_console.run_command(f"mdio write {phy_addr} {reg} {wr_val}")
- output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+ ubman.run_command(f"mdio write {phy_addr} {reg} {wr_val}")
+ output = ubman.run_command(f"mdio read {phy_addr} {reg}")
assert f"PHY at address {int(phy_addr, 16):x}:" in output
assert f"{int(reg, 16):x} - {wr_val}" in output
- u_boot_console.run_command(f"mdio write {phy_addr} {reg} {reg_val}")
- output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+ ubman.run_command(f"mdio write {phy_addr} {reg} {reg_val}")
+ output = ubman.run_command(f"mdio read {phy_addr} {reg}")
assert f"PHY at address {int(phy_addr, 16):x}:" in output
assert f"{int(reg, 16):x} - {reg_val}" in output
diff --git a/test/py/tests/test_memtest.py b/test/py/tests/test_memtest.py
index 0618d96..0340edb 100644
--- a/test/py/tests/test_memtest.py
+++ b/test/py/tests/test_memtest.py
@@ -24,8 +24,8 @@
}
"""
-def get_memtest_env(u_boot_console):
- f = u_boot_console.config.env.get("env__memtest", None)
+def get_memtest_env(ubman):
+ f = ubman.config.env.get("env__memtest", None)
if not f:
pytest.skip("memtest is not enabled!")
else:
@@ -38,31 +38,31 @@
return start, end, pattern, iteration, timeout
@pytest.mark.buildconfigspec("cmd_memtest")
-def test_memtest_negative(u_boot_console):
+def test_memtest_negative(ubman):
"""Negative testcase where end address is smaller than starting address and
pattern is invalid."""
- start, end, pattern, iteration, timeout = get_memtest_env(u_boot_console)
+ start, end, pattern, iteration, timeout = get_memtest_env(ubman)
expected_response = "Refusing to do empty test"
- response = u_boot_console.run_command(
+ response = ubman.run_command(
f"mtest 2000 1000 {pattern} {hex(iteration)}"
)
assert expected_response in response
- output = u_boot_console.run_command("echo $?")
+ output = ubman.run_command("echo $?")
assert not output.endswith("0")
- u_boot_console.run_command(f"mtest {start} {end} 'xyz' {hex(iteration)}")
- output = u_boot_console.run_command("echo $?")
+ ubman.run_command(f"mtest {start} {end} 'xyz' {hex(iteration)}")
+ output = ubman.run_command("echo $?")
assert not output.endswith("0")
@pytest.mark.buildconfigspec("cmd_memtest")
-def test_memtest_ddr(u_boot_console):
+def test_memtest_ddr(ubman):
"""Test that md reads memory as expected, and that memory can be modified
using the mw command."""
- start, end, pattern, iteration, timeout = get_memtest_env(u_boot_console)
+ start, end, pattern, iteration, timeout = get_memtest_env(ubman)
expected_response = f"Tested {str(iteration)} iteration(s) with 0 errors."
- with u_boot_console.temporary_timeout(timeout):
- response = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ response = ubman.run_command(
f"mtest {start} {end} {pattern} {hex(iteration)}"
)
assert expected_response in response
- output = u_boot_console.run_command("echo $?")
+ output = ubman.run_command("echo $?")
assert output.endswith("0")
diff --git a/test/py/tests/test_mii.py b/test/py/tests/test_mii.py
index 7b6816d..e282add 100644
--- a/test/py/tests/test_mii.py
+++ b/test/py/tests/test_mii.py
@@ -22,21 +22,21 @@
"""
@pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_info(u_boot_console):
- if u_boot_console.config.env.get("env__mii_device_test_skip", False):
+def test_mii_info(ubman):
+ if ubman.config.env.get("env__mii_device_test_skip", False):
pytest.skip("MII device test is not enabled!")
expected_output = "PHY"
- output = u_boot_console.run_command("mii info")
+ output = ubman.run_command("mii info")
if not re.search(r"PHY (.+?):", output):
pytest.skip("PHY device does not exist!")
assert expected_output in output
@pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_list(u_boot_console):
- if u_boot_console.config.env.get("env__mii_device_test_skip", False):
+def test_mii_list(ubman):
+ if ubman.config.env.get("env__mii_device_test_skip", False):
pytest.skip("MII device test is not enabled!")
- f = u_boot_console.config.env.get("env__mii_device_test", None)
+ f = ubman.config.env.get("env__mii_device_test", None)
if not f:
pytest.skip("No MII device to test!")
@@ -45,7 +45,7 @@
pytest.fail("No MII device list provided via env__mii_device_test!")
expected_output = "Current device"
- output = u_boot_console.run_command("mii device")
+ output = ubman.run_command("mii device")
mii_devices = (
re.search(r"MII devices: '(.+)'", output).groups()[0].replace("'", "").split()
)
@@ -54,39 +54,39 @@
assert expected_output in output
@pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_set_device(u_boot_console):
- test_mii_list(u_boot_console)
- f = u_boot_console.config.env.get("env__mii_device_test", None)
+def test_mii_set_device(ubman):
+ test_mii_list(ubman)
+ f = ubman.config.env.get("env__mii_device_test", None)
dev_list = f.get("device_list")
- output = u_boot_console.run_command("mii device")
+ output = ubman.run_command("mii device")
current_dev = re.search(r"Current device: '(.+?)'", output).groups()[0]
for dev in dev_list:
- u_boot_console.run_command(f"mii device {dev}")
- output = u_boot_console.run_command("echo $?")
+ ubman.run_command(f"mii device {dev}")
+ output = ubman.run_command("echo $?")
assert output.endswith("0")
- u_boot_console.run_command(f"mii device {current_dev}")
- output = u_boot_console.run_command("mii device")
+ ubman.run_command(f"mii device {current_dev}")
+ output = ubman.run_command("mii device")
dev = re.search(r"Current device: '(.+?)'", output).groups()[0]
assert current_dev == dev
@pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_read(u_boot_console):
- test_mii_list(u_boot_console)
- output = u_boot_console.run_command("mii info")
+def test_mii_read(ubman):
+ test_mii_list(ubman)
+ output = ubman.run_command("mii info")
eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
- u_boot_console.run_command(f"mii read {eth_addr} 0")
- output = u_boot_console.run_command("echo $?")
+ ubman.run_command(f"mii read {eth_addr} 0")
+ output = ubman.run_command("echo $?")
assert output.endswith("0")
@pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_dump(u_boot_console):
- test_mii_list(u_boot_console)
+def test_mii_dump(ubman):
+ test_mii_list(ubman)
expected_response = "PHY control register"
- output = u_boot_console.run_command("mii info")
+ output = ubman.run_command("mii info")
eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
- response = u_boot_console.run_command(f"mii dump {eth_addr} 0")
+ response = ubman.run_command(f"mii dump {eth_addr} 0")
assert expected_response in response
- output = u_boot_console.run_command("echo $?")
+ output = ubman.run_command("echo $?")
assert output.endswith("0")
diff --git a/test/py/tests/test_mmc.py b/test/py/tests/test_mmc.py
index 4624043..e751a3b 100644
--- a/test/py/tests/test_mmc.py
+++ b/test/py/tests/test_mmc.py
@@ -4,7 +4,7 @@
import pytest
import random
import re
-import u_boot_utils
+import utils
"""
Note: This test doesn't rely on boardenv_* configuration values but it can
@@ -32,19 +32,19 @@
mmc_modes_name = []
mmc_modes = []
-def setup_mmc_modes(cons):
+def setup_mmc_modes(ubman):
global mmc_modes, mmc_modes_name
- f = cons.config.env.get('env__mmc_device', None)
+ f = ubman.config.env.get('env__mmc_device', None)
if f:
mmc_modes_name = f.get('mmc_modes', None)
# Set mmc mode to default mode (legacy), if speed mode config isn't enabled
- if cons.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y':
mmc_modes = [0]
return
if mmc_modes_name:
- mmc_help = cons.run_command('mmc -help')
+ mmc_help = ubman.run_command('mmc -help')
m = re.search(r"\[MMC_LEGACY(.*\n.+])", mmc_help)
modes = [
x.strip()
@@ -61,16 +61,16 @@
# Set mmc mode to default mode (legacy), if it is not defined in env
mmc_modes = [0]
-def setup_mmc(u_boot_console):
- if u_boot_console.config.env.get('env__mmc_device_test_skip', True):
+def setup_mmc(ubman):
+ if ubman.config.env.get('env__mmc_device_test_skip', True):
pytest.skip('MMC device test is not enabled')
- setup_mmc_modes(u_boot_console)
+ setup_mmc_modes(ubman)
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_list(u_boot_console):
- setup_mmc(u_boot_console)
- output = u_boot_console.run_command('mmc list')
+def test_mmc_list(ubman):
+ setup_mmc(ubman)
+ output = ubman.run_command('mmc list')
if 'No MMC device available' in output:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -90,7 +90,7 @@
mmc_set_up = True
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_dev(u_boot_console):
+def test_mmc_dev(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -99,7 +99,7 @@
devices[x]['detected'] = 'yes'
for y in mmc_modes:
- output = u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+ output = ubman.run_command('mmc dev %d 0 %d' % x, y)
if 'Card did not respond to voltage select' in output:
fail = 1
@@ -115,15 +115,15 @@
pytest.fail('Card not present')
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmcinfo(u_boot_console):
+def test_mmcinfo(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
- output = u_boot_console.run_command('mmcinfo')
+ ubman.run_command('mmc dev %d 0 %d' % x, y)
+ output = ubman.run_command('mmcinfo')
if 'busy timeout' in output:
pytest.skip('No SD/MMC/eMMC device present')
@@ -139,16 +139,16 @@
pytest.fail('MMC capacity not recognized')
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_info(u_boot_console):
+def test_mmc_info(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+ ubman.run_command('mmc dev %d 0 %d' % x, y)
- output = u_boot_console.run_command('mmc info')
+ output = ubman.run_command('mmc info')
assert mmc_modes_name[mmc_modes.index(y)] in output
obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
@@ -162,7 +162,7 @@
pytest.fail('MMC capacity not recognized')
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rescan(u_boot_console):
+def test_mmc_rescan(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -172,15 +172,15 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
- output = u_boot_console.run_command('mmc rescan')
+ ubman.run_command('mmc dev %d 0 %d' % x, y)
+ output = ubman.run_command('mmc rescan')
if output:
pytest.fail('mmc rescan has something to check')
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_part(u_boot_console):
+def test_mmc_part(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -189,8 +189,8 @@
for x in range(0, controllers):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('mmc dev %d' % x)
- output = u_boot_console.run_command('mmc part')
+ ubman.run_command('mmc dev %d' % x)
+ output = ubman.run_command('mmc part')
lines = output.split('\n')
part_fat = []
@@ -209,7 +209,7 @@
part_fat.append(part_id)
elif part_type == '83':
print('ext(2/4) detected')
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'fstype mmc %d:%d' % x, part_id
)
if 'ext2' in output:
@@ -227,7 +227,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_fat')
-def test_mmc_fatls_fatinfo(u_boot_console):
+def test_mmc_fatls_fatinfo(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -246,8 +246,8 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
- output = u_boot_console.run_command(
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
+ output = ubman.run_command(
'fatls mmc %d:%s' % (x, part))
if 'Unrecognized filesystem type' in output:
partitions.remove(part)
@@ -255,7 +255,7 @@
if not re.search(r'\d file\(s\), \d dir\(s\)', output):
pytest.fail('%s read failed on device %d' % (fs.upper, x))
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'fatinfo mmc %d:%s' % (x, part))
string = 'Filesystem: %s' % fs.upper
if re.search(string, output):
@@ -269,7 +269,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_fat')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_fatload_fatwrite(u_boot_console):
+def test_mmc_fatload_fatwrite(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -288,14 +288,14 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
devices[x]['addr_%d' % part] = addr
size = random.randint(4, 1 * 1024 * 1024)
devices[x]['size_%d' % part] = size
# count CRC32
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ output = ubman.run_command('crc32 %x %x' % (addr, size))
m = re.search('==> (.+?)', output)
if not m:
pytest.fail('CRC32 failed')
@@ -304,7 +304,7 @@
# do write
file = '%s_%d' % ('uboot_test', size)
devices[x]['file_%d' % part] = file
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size)
)
assert 'Unable to write' not in output
@@ -314,12 +314,12 @@
assert expected_text in output
alignment = int(
- u_boot_console.config.buildconfig.get(
+ ubman.config.buildconfig.get(
'config_sys_cacheline_size', 128
)
)
offset = random.randrange(alignment, 1024, alignment)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file)
)
assert 'Invalid FAT entry' not in output
@@ -328,7 +328,7 @@
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -338,7 +338,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_ext4')
-def test_mmc_ext4ls(u_boot_console):
+def test_mmc_ext4ls(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -357,8 +357,8 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
- output = u_boot_console.run_command(
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
+ output = ubman.run_command(
'%sls mmc %d:%s' % (fs, x, part)
)
if 'Unrecognized filesystem type' in output:
@@ -373,7 +373,7 @@
@pytest.mark.buildconfigspec('cmd_ext4')
@pytest.mark.buildconfigspec('ext4_write')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_ext4load_ext4write(u_boot_console):
+def test_mmc_ext4load_ext4write(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -392,14 +392,14 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
devices[x]['addr_%d' % part] = addr
size = random.randint(4, 1 * 1024 * 1024)
devices[x]['size_%d' % part] = size
# count CRC32
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ output = ubman.run_command('crc32 %x %x' % (addr, size))
m = re.search('==> (.+?)', output)
if not m:
pytest.fail('CRC32 failed')
@@ -409,7 +409,7 @@
# do write
file = '%s_%d' % ('uboot_test', size)
devices[x]['file_%d' % part] = file
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
)
assert 'Unable to write' not in output
@@ -419,13 +419,13 @@
assert expected_text in output
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
)
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -435,7 +435,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_ext2')
-def test_mmc_ext2ls(u_boot_console):
+def test_mmc_ext2ls(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -454,9 +454,9 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sls mmc %d:%s' % (fs, x, part)
)
if 'Unrecognized filesystem type' in output:
@@ -472,7 +472,7 @@
@pytest.mark.buildconfigspec('cmd_ext4')
@pytest.mark.buildconfigspec('ext4_write')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_ext2load(u_boot_console):
+def test_mmc_ext2load(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -491,7 +491,7 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
addr = devices[x]['addr_%d' % part]
size = devices[x]['size_%d' % part]
@@ -499,13 +499,13 @@
file = devices[x]['file_%d' % part]
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
)
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -515,7 +515,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_mmc_ls(u_boot_console):
+def test_mmc_ls(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -534,9 +534,9 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
- output = u_boot_console.run_command('ls mmc %d:%s' % (x, part))
+ output = ubman.run_command('ls mmc %d:%s' % (x, part))
if re.search(r'No \w+ table on this device', output):
pytest.fail(
'%s: Partition table not found %d' % (fs.upper(), x)
@@ -547,7 +547,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_mmc_load(u_boot_console):
+def test_mmc_load(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -566,7 +566,7 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
addr = devices[x]['addr_%d' % part]
size = devices[x]['size_%d' % part]
@@ -574,13 +574,13 @@
file = devices[x]['file_%d' % part]
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'load mmc %d:%s %x /%s' % (x, part, addr + offset, file)
)
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -590,7 +590,7 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_mmc_save(u_boot_console):
+def test_mmc_save(ubman):
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -609,14 +609,14 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
addr = devices[x]['addr_%d' % part]
size = 0
file = devices[x]['file_%d' % part]
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'save mmc %d:%s %x /%s %d'
% (x, part, addr + offset, file, size)
)
@@ -629,11 +629,11 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_fat')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_fat_read_write_files(u_boot_console):
- test_mmc_list(u_boot_console)
- test_mmc_dev(u_boot_console)
- test_mmcinfo(u_boot_console)
- test_mmc_part(u_boot_console)
+def test_mmc_fat_read_write_files(ubman):
+ test_mmc_list(ubman)
+ test_mmc_dev(ubman)
+ test_mmcinfo(ubman)
+ test_mmc_part(ubman)
if not mmc_set_up:
pytest.skip('No SD/MMC/eMMC controller available')
@@ -656,9 +656,9 @@
for part in partitions:
for y in mmc_modes:
- u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+ ubman.run_command('mmc dev %d %d %d' % x, part, y)
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
count_f = 0
addr_l = []
size_l = []
@@ -671,7 +671,7 @@
size_l.append(random.randint(4, 1 * 1024 * 1024))
# CRC32 count
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x %x' % (addr_l[count_f], size_l[count_f])
)
m = re.search('==> (.+?)', output)
@@ -683,7 +683,7 @@
file_l.append(
'%s_%d_%d' % ('uboot_test', count_f, size_l[count_f])
)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite mmc %d:%s %x %s %x'
% (
fs,
@@ -706,14 +706,14 @@
count_f = 0
while count_f < num_files:
alignment = int(
- u_boot_console.config.buildconfig.get(
+ ubman.config.buildconfig.get(
'config_sys_cacheline_size', 128
)
)
offset_l.append(random.randrange(alignment, 1024, alignment))
# Read operation
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload mmc %d:%s %x %s'
% (
fs,
@@ -729,7 +729,7 @@
expected_text = '%d bytes read' % size_l[count_f]
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f])
)
assert crc32_l[count_f] in output
diff --git a/test/py/tests/test_mmc_rd.py b/test/py/tests/test_mmc_rd.py
index ea652f9..cd1e299 100644
--- a/test/py/tests/test_mmc_rd.py
+++ b/test/py/tests/test_mmc_rd.py
@@ -7,7 +7,7 @@
import pytest
import time
-import u_boot_utils
+import utils
"""
This test relies on boardenv_* to containing configuration values to define
@@ -105,11 +105,11 @@
)
"""
-def mmc_dev(u_boot_console, is_emmc, devid, partid):
+def mmc_dev(ubman, is_emmc, devid, partid):
"""Run the "mmc dev" command.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
is_emmc: Whether the device is eMMC
devid: Device ID
partid: Partition ID
@@ -122,7 +122,7 @@
cmd = 'mmc dev %d' % devid
if is_emmc:
cmd += ' %d' % partid
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert 'no card present' not in response
if is_emmc:
partid_response = '(part %d)' % partid
@@ -132,11 +132,11 @@
assert good_response in response
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_dev(u_boot_console, env__mmc_dev_config):
+def test_mmc_dev(ubman, env__mmc_dev_config):
"""Test the "mmc dev" command.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__mmc_dev_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
@@ -150,14 +150,14 @@
partid = env__mmc_dev_config.get('partid', 0)
# Select MMC device
- mmc_dev(u_boot_console, is_emmc, devid, partid)
+ mmc_dev(ubman, is_emmc, devid, partid)
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rescan(u_boot_console, env__mmc_dev_config):
+def test_mmc_rescan(ubman, env__mmc_dev_config):
"""Test the "mmc rescan" command.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__mmc_dev_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
@@ -171,19 +171,19 @@
partid = env__mmc_dev_config.get('partid', 0)
# Select MMC device
- mmc_dev(u_boot_console, is_emmc, devid, partid)
+ mmc_dev(ubman, is_emmc, devid, partid)
# Rescan MMC device
cmd = 'mmc rescan'
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert 'no card present' not in response
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_info(u_boot_console, env__mmc_dev_config):
+def test_mmc_info(ubman, env__mmc_dev_config):
"""Test the "mmc info" command.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__mmc_dev_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
@@ -201,11 +201,11 @@
info_buswidth = env__mmc_dev_config['info_buswidth']
# Select MMC device
- mmc_dev(u_boot_console, is_emmc, devid, partid)
+ mmc_dev(ubman, is_emmc, devid, partid)
# Read MMC device information
cmd = 'mmc info'
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = "Device: %s" % info_device
assert good_response in response
good_response = "Bus Speed: %s" % info_speed
@@ -216,11 +216,11 @@
assert good_response in response
@pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rd(u_boot_console, env__mmc_rd_config):
+def test_mmc_rd(ubman, env__mmc_rd_config):
"""Test the "mmc read" command.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__mmc_rd_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
@@ -238,32 +238,32 @@
read_duration_max = env__mmc_rd_config.get('read_duration_max', 0)
count_bytes = count_sectors * 512
- bcfg = u_boot_console.config.buildconfig
+ bcfg = ubman.config.buildconfig
has_cmd_memory = bcfg.get('config_cmd_memory', 'n') == 'y'
has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
- ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ ram_base = utils.find_ram_base(ubman)
addr = '0x%08x' % ram_base
# Select MMC device
- mmc_dev(u_boot_console, is_emmc, devid, partid)
+ mmc_dev(ubman, is_emmc, devid, partid)
# Clear target RAM
if expected_crc32:
if has_cmd_memory and has_cmd_crc32:
cmd = 'mw.b %s 0 0x%x' % (addr, count_bytes)
- u_boot_console.run_command(cmd)
+ ubman.run_command(cmd)
cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert expected_crc32 not in response
else:
- u_boot_console.log.warning(
+ ubman.log.warning(
'CONFIG_CMD_MEMORY or CONFIG_CMD_CRC32 != y: Skipping RAM clear')
# Read data
cmd = 'mmc read %s %x %x' % (addr, sector, count_sectors)
tstart = time.time()
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
tend = time.time()
good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (
devid, sector, count_sectors, count_sectors)
@@ -273,14 +273,14 @@
if expected_crc32:
if has_cmd_crc32:
cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert expected_crc32 in response
else:
- u_boot_console.log.warning('CONFIG_CMD_CRC32 != y: Skipping check')
+ ubman.log.warning('CONFIG_CMD_CRC32 != y: Skipping check')
# Check if the command did not take too long
if read_duration_max:
elapsed = tend - tstart
- u_boot_console.log.info('Reading %d bytes took %f seconds' %
+ ubman.log.info('Reading %d bytes took %f seconds' %
(count_bytes, elapsed))
assert elapsed <= (read_duration_max - 0.01)
diff --git a/test/py/tests/test_mmc_wr.py b/test/py/tests/test_mmc_wr.py
index 05e5c1e..41a75f8 100644
--- a/test/py/tests/test_mmc_wr.py
+++ b/test/py/tests/test_mmc_wr.py
@@ -6,7 +6,7 @@
# to the eMMC or SD card, then reads it back and performs a comparison.
import pytest
-import u_boot_utils
+import utils
"""
This test relies on boardenv_* to containing configuration values to define
@@ -38,11 +38,11 @@
@pytest.mark.buildconfigspec('cmd_mmc')
@pytest.mark.buildconfigspec('cmd_memory')
@pytest.mark.buildconfigspec('cmd_random')
-def test_mmc_wr(u_boot_console, env__mmc_wr_config):
+def test_mmc_wr(ubman, env__mmc_wr_config):
"""Test the "mmc write" command.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__mmc_wr_config: The single MMC configuration on which
to run the test. See the file-level comment above for details
of the format.
@@ -60,8 +60,8 @@
count_bytes = count_sectors * 512
- bcfg = u_boot_console.config.buildconfig
- ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ bcfg = ubman.config.buildconfig
+ ram_base = utils.find_ram_base(ubman)
src_addr = '0x%08x' % ram_base
dst_addr = '0x%08x' % (ram_base + count_bytes)
@@ -69,7 +69,7 @@
for i in range(test_iterations):
# Generate random data
cmd = 'random %s %x' % (src_addr, count_bytes)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = '%d bytes filled with random data' % (count_bytes)
assert good_response in response
@@ -77,7 +77,7 @@
cmd = 'mmc dev %d' % devid
if is_emmc:
cmd += ' %d' % partid
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert 'no card present' not in response
if is_emmc:
partid_response = "(part %d)" % partid
@@ -88,18 +88,18 @@
# Write data
cmd = 'mmc write %s %x %x' % (src_addr, sector, count_sectors)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = 'MMC write: dev # %d, block # %d, count %d ... %d blocks written: OK' % (devid, sector, count_sectors, count_sectors)
assert good_response in response
# Read data
cmd = 'mmc read %s %x %x' % (dst_addr, sector, count_sectors)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (devid, sector, count_sectors, count_sectors)
assert good_response in response
# Compare src and dst data
cmd = 'cmp.b %s %s %x' % (src_addr, dst_addr, count_bytes)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
good_response = 'Total of %d byte(s) were the same' % (count_bytes)
assert good_response in response
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index ad143c1..4732e4b 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -5,7 +5,7 @@
# tftpboot commands.
import pytest
-import u_boot_utils
+import utils
import uuid
import datetime
import re
@@ -91,37 +91,39 @@
net_set_up = False
net6_set_up = False
-def test_net_pre_commands(u_boot_console):
+
+@pytest.mark.buildconfigspec('cmd_net')
+def test_net_pre_commands(ubman):
"""Execute any commands required to enable network hardware.
These commands are provided by the boardenv_* file; see the comment at the
beginning of this file.
"""
- init_usb = u_boot_console.config.env.get('env__net_uses_usb', False)
+ init_usb = ubman.config.env.get('env__net_uses_usb', False)
if init_usb:
- u_boot_console.run_command('usb start')
+ ubman.run_command('usb start')
- init_pci = u_boot_console.config.env.get('env__net_uses_pci', False)
+ init_pci = ubman.config.env.get('env__net_uses_pci', False)
if init_pci:
- u_boot_console.run_command('pci enum')
+ ubman.run_command('pci enum')
- u_boot_console.run_command('net list')
+ ubman.run_command('net list')
@pytest.mark.buildconfigspec('cmd_dhcp')
-def test_net_dhcp(u_boot_console):
+def test_net_dhcp(ubman):
"""Test the dhcp command.
The boardenv_* file may be used to enable/disable this test; see the
comment at the beginning of this file.
"""
- test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+ test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
if not test_dhcp:
pytest.skip('No DHCP server available')
- u_boot_console.run_command('setenv autoload no')
- output = u_boot_console.run_command('dhcp')
+ ubman.run_command('setenv autoload no')
+ output = ubman.run_command('dhcp')
assert 'DHCP client bound to address ' in output
global net_set_up
@@ -129,43 +131,43 @@
@pytest.mark.buildconfigspec('cmd_dhcp')
@pytest.mark.buildconfigspec('cmd_mii')
-def test_net_dhcp_abort(u_boot_console):
+def test_net_dhcp_abort(ubman):
"""Test the dhcp command by pressing ctrl+c in the middle of dhcp request
The boardenv_* file may be used to enable/disable this test; see the
comment at the beginning of this file.
"""
- test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+ test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
if not test_dhcp:
pytest.skip('No DHCP server available')
- if u_boot_console.config.env.get('env__dhcp_abort_test_skip', True):
+ if ubman.config.env.get('env__dhcp_abort_test_skip', True):
pytest.skip('DHCP abort test is not enabled!')
- u_boot_console.run_command('setenv autoload no')
+ ubman.run_command('setenv autoload no')
# Phy reset before running dhcp command
- output = u_boot_console.run_command('mii device')
+ output = ubman.run_command('mii device')
if not re.search(r"Current device: '(.+?)'", output):
pytest.skip('PHY device does not exist!')
eth_num = re.search(r"Current device: '(.+?)'", output).groups()[0]
- u_boot_console.run_command(f'mii device {eth_num}')
- output = u_boot_console.run_command('mii info')
+ ubman.run_command(f'mii device {eth_num}')
+ output = ubman.run_command('mii info')
eth_addr = hex(int(re.search(r'PHY (.+?):', output).groups()[0], 16))
- u_boot_console.run_command(f'mii modify {eth_addr} 0 0x8000 0x8000')
+ ubman.run_command(f'mii modify {eth_addr} 0 0x8000 0x8000')
- u_boot_console.run_command('dhcp', wait_for_prompt=False)
+ ubman.run_command('dhcp', wait_for_prompt=False)
try:
- u_boot_console.wait_for('Waiting for PHY auto negotiation to complete')
+ ubman.wait_for('Waiting for PHY auto negotiation to complete')
except:
pytest.skip('Timeout waiting for PHY auto negotiation to complete')
- u_boot_console.wait_for('done')
+ ubman.wait_for('done')
try:
# Sending Ctrl-C
- output = u_boot_console.run_command(
+ output = ubman.run_command(
chr(3), wait_for_echo=False, send_nl=False
)
assert 'TIMEOUT' not in output
@@ -174,49 +176,49 @@
finally:
# Provide a time to recover from Abort - if it is not performed
# There is message like: ethernet@ff0e0000: No link.
- u_boot_console.run_command('sleep 1')
+ ubman.run_command('sleep 1')
# Run the dhcp test to setup the network configuration
- test_net_dhcp(u_boot_console)
+ test_net_dhcp(ubman)
@pytest.mark.buildconfigspec('cmd_dhcp6')
-def test_net_dhcp6(u_boot_console):
+def test_net_dhcp6(ubman):
"""Test the dhcp6 command.
The boardenv_* file may be used to enable/disable this test; see the
comment at the beginning of this file.
"""
- test_dhcp6 = u_boot_console.config.env.get('env__net_dhcp6_server', False)
+ test_dhcp6 = ubman.config.env.get('env__net_dhcp6_server', False)
if not test_dhcp6:
pytest.skip('No DHCP6 server available')
- u_boot_console.run_command('setenv autoload no')
- output = u_boot_console.run_command('dhcp6')
+ ubman.run_command('setenv autoload no')
+ output = ubman.run_command('dhcp6')
assert 'DHCP6 client bound to ' in output
global net6_set_up
net6_set_up = True
@pytest.mark.buildconfigspec('net')
-def test_net_setup_static(u_boot_console):
+def test_net_setup_static(ubman):
"""Set up a static IP configuration.
The configuration is provided by the boardenv_* file; see the comment at
the beginning of this file.
"""
- env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+ env_vars = ubman.config.env.get('env__net_static_env_vars', None)
if not env_vars:
pytest.skip('No static network configuration is defined')
for (var, val) in env_vars:
- u_boot_console.run_command('setenv %s %s' % (var, val))
+ ubman.run_command('setenv %s %s' % (var, val))
global net_set_up
net_set_up = True
@pytest.mark.buildconfigspec('cmd_ping')
-def test_net_ping(u_boot_console):
+def test_net_ping(ubman):
"""Test the ping command.
The $serverip (as set up by either test_net_dhcp or test_net_setup_static)
@@ -227,11 +229,11 @@
if not net_set_up:
pytest.skip('Network not initialized')
- output = u_boot_console.run_command('ping $serverip')
+ output = ubman.run_command('ping $serverip')
assert 'is alive' in output
@pytest.mark.buildconfigspec('IPV6_ROUTER_DISCOVERY')
-def test_net_network_discovery(u_boot_console):
+def test_net_network_discovery(ubman):
"""Test the network discovery feature of IPv6.
An IPv6 network command (ping6 in this case) is run to make U-Boot send a
@@ -244,18 +246,18 @@
the beginning of this file.
"""
- router_on_net = u_boot_console.config.env.get('env__router_on_net', False)
+ router_on_net = ubman.config.env.get('env__router_on_net', False)
if not router_on_net:
pytest.skip('No router on network')
fake_host_ip = 'fe80::215:5dff:fef6:2ec6'
- output = u_boot_console.run_command('ping6 ' + fake_host_ip)
+ output = ubman.run_command('ping6 ' + fake_host_ip)
assert 'ROUTER SOLICITATION 1' in output
assert 'Set gatewayip6:' in output
assert '0000:0000:0000:0000:0000:0000:0000:0000' not in output
@pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_net_tftpboot(u_boot_console):
+def test_net_tftpboot(ubman):
"""Test the tftpboot command.
A file is downloaded from the TFTP server, its size and optionally its
@@ -268,7 +270,7 @@
if not net_set_up:
pytest.skip('Network not initialized')
- f = u_boot_console.config.env.get('env__net_tftp_readable_file', None)
+ f = ubman.config.env.get('env__net_tftp_readable_file', None)
if not f:
pytest.skip('No TFTP readable file to read')
@@ -276,9 +278,9 @@
fn = f['fn']
if not addr:
- output = u_boot_console.run_command('tftpboot %s' % (fn))
+ output = ubman.run_command('tftpboot %s' % (fn))
else:
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (addr, fn))
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
if sz:
@@ -289,14 +291,14 @@
if not expected_crc:
return
- if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
return
- output = u_boot_console.run_command('crc32 $fileaddr $filesize')
+ output = ubman.run_command('crc32 $fileaddr $filesize')
assert expected_crc in output
@pytest.mark.buildconfigspec('cmd_nfs')
-def test_net_nfs(u_boot_console):
+def test_net_nfs(ubman):
"""Test the nfs command.
A file is downloaded from the NFS server, its size and optionally its
@@ -309,16 +311,16 @@
if not net_set_up:
pytest.skip('Network not initialized')
- f = u_boot_console.config.env.get('env__net_nfs_readable_file', None)
+ f = ubman.config.env.get('env__net_nfs_readable_file', None)
if not f:
pytest.skip('No NFS readable file to read')
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
fn = f['fn']
- output = u_boot_console.run_command('nfs %x %s' % (addr, fn))
+ output = ubman.run_command('nfs %x %s' % (addr, fn))
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
if sz:
@@ -329,14 +331,14 @@
if not expected_crc:
return
- if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
return
- output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+ output = ubman.run_command('crc32 %x $filesize' % addr)
assert expected_crc in output
@pytest.mark.buildconfigspec("cmd_pxe")
-def test_net_pxe_get(u_boot_console):
+def test_net_pxe_get(ubman):
"""Test the pxe get command.
A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -349,31 +351,31 @@
if not net_set_up:
pytest.skip("Network not initialized")
- test_net_setup_static(u_boot_console)
+ test_net_setup_static(ubman)
- f = u_boot_console.config.env.get("env__net_pxe_readable_file", None)
+ f = ubman.config.env.get("env__net_pxe_readable_file", None)
if not f:
pytest.skip("No PXE readable file to read")
addr = f.get("addr", None)
- timeout = f.get("timeout", u_boot_console.p.timeout)
+ timeout = f.get("timeout", ubman.p.timeout)
pxeuuid = uuid.uuid1()
- u_boot_console.run_command(f"setenv pxeuuid {pxeuuid}")
+ ubman.run_command(f"setenv pxeuuid {pxeuuid}")
expected_text_uuid = f"Retrieving file: pxelinux.cfg/{pxeuuid}"
- ethaddr = u_boot_console.run_command("echo $ethaddr")
+ ethaddr = ubman.run_command("echo $ethaddr")
ethaddr = ethaddr.replace(':', '-')
expected_text_ethaddr = f"Retrieving file: pxelinux.cfg/01-{ethaddr}"
- ip = u_boot_console.run_command("echo $ipaddr")
+ ip = ubman.run_command("echo $ipaddr")
ip = ip.split('.')
ipaddr_file = "".join(['%02x' % int(x) for x in ip]).upper()
expected_text_ipaddr = f"Retrieving file: pxelinux.cfg/{ipaddr_file}"
expected_text_default = f"Retrieving file: pxelinux.cfg/default"
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command("pxe get")
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command("pxe get")
assert "TIMEOUT" not in output
assert expected_text_uuid in output
@@ -392,7 +394,7 @@
@pytest.mark.buildconfigspec("cmd_crc32")
@pytest.mark.buildconfigspec("cmd_tftpboot")
@pytest.mark.buildconfigspec("cmd_tftpput")
-def test_net_tftpput(u_boot_console):
+def test_net_tftpput(ubman):
"""Test the tftpput command.
A file is downloaded from the TFTP server and then uploaded to the TFTP
@@ -405,35 +407,35 @@
if not net_set_up:
pytest.skip("Network not initialized")
- f = u_boot_console.config.env.get("env__net_tftp_readable_file", None)
+ f = ubman.config.env.get("env__net_tftp_readable_file", None)
if not f:
pytest.skip("No TFTP readable file to read")
addr = f.get("addr", None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
sz = f.get("size", None)
- timeout = f.get("timeout", u_boot_console.p.timeout)
+ timeout = f.get("timeout", ubman.p.timeout)
fn = f["fn"]
fnu = f.get("fnu", "_".join([datetime.datetime.now().strftime("%y%m%d%H%M%S"), fn]))
expected_text = "Bytes transferred = "
if sz:
expected_text += "%d" % sz
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command("tftpboot %x %s" % (addr, fn))
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command("tftpboot %x %s" % (addr, fn))
assert "TIMEOUT" not in output
assert expected_text in output
expected_tftpb_crc = f.get("crc32", None)
- output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+ output = ubman.run_command("crc32 $fileaddr $filesize")
assert expected_tftpb_crc in output
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
"tftpput $fileaddr $filesize $serverip:%s" % (fnu)
)
@@ -445,8 +447,8 @@
assert "Access violation" not in output
assert expected_text in output
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command("tftpboot %x %s" % (addr, fnu))
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command("tftpboot %x %s" % (addr, fnu))
expected_text = "Bytes transferred = "
if sz:
@@ -454,5 +456,5 @@
assert "TIMEOUT" not in output
assert expected_text in output
- output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+ output = ubman.run_command("crc32 $fileaddr $filesize")
assert expected_tftpb_crc in output
diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py
index d7d7435..abf6dfb 100644
--- a/test/py/tests/test_net_boot.py
+++ b/test/py/tests/test_net_boot.py
@@ -2,7 +2,7 @@
# (C) Copyright 2023, Advanced Micro Devices, Inc.
import pytest
-import u_boot_utils
+import utils
import test_net
import re
@@ -117,26 +117,26 @@
initrd rootfs.cpio.gz.u-boot
"""
-def setup_networking(u_boot_console):
- test_net.test_net_dhcp(u_boot_console)
+def setup_networking(ubman):
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
-def setup_tftpboot_boot(u_boot_console):
- f = u_boot_console.config.env.get('env__net_tftp_bootable_file', None)
+def setup_tftpboot_boot(ubman):
+ f = ubman.config.env.get('env__net_tftp_bootable_file', None)
if not f:
pytest.skip('No TFTP bootable file to read')
- setup_networking(u_boot_console)
+ setup_networking(ubman)
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
fn = f['fn']
timeout = f.get('timeout', 50000)
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command('tftpboot %x %s' % (addr, fn))
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
@@ -145,7 +145,7 @@
assert expected_text in output
expected_crc = f.get('crc32', None)
- output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+ output = ubman.run_command('crc32 %x $filesize' % addr)
if expected_crc:
assert expected_crc in output
@@ -157,7 +157,7 @@
return addr, timeout, pattern, chk_type, chk_pattern, config
@pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_net_tftpboot_boot(u_boot_console):
+def test_net_tftpboot_boot(ubman):
"""Boot the loaded image
A boot file (fit image) is downloaded from the TFTP server and booted using
@@ -167,11 +167,11 @@
The details of the file to download are provided by the boardenv_* file;
see the comment at the beginning of this file.
"""
- if u_boot_console.config.env.get('env__tftp_boot_test_skip', True):
+ if ubman.config.env.get('env__tftp_boot_test_skip', True):
pytest.skip('TFTP boot test is not enabled!')
addr, timeout, pattern, chk_type, chk_pattern, imcfg = setup_tftpboot_boot(
- u_boot_console
+ ubman
)
if imcfg:
@@ -179,38 +179,38 @@
else:
bootcmd = 'bootm %x' % addr
- with u_boot_console.enable_check(
+ with ubman.enable_check(
chk_type, chk_pattern
- ), u_boot_console.temporary_timeout(timeout):
+ ), ubman.temporary_timeout(timeout):
try:
# wait_for_prompt=False makes the core code not wait for the U-Boot
# prompt code to be seen, since it won't be on a successful kernel
# boot
- u_boot_console.run_command(bootcmd, wait_for_prompt=False)
+ ubman.run_command(bootcmd, wait_for_prompt=False)
# Wait for boot log pattern
- u_boot_console.wait_for(pattern)
+ ubman.wait_for(pattern)
finally:
# This forces the console object to be shutdown, so any subsequent
# test will reset the board back into U-Boot. We want to force this
# no matter whether the kernel boot passed or failed.
- u_boot_console.drain_console()
- u_boot_console.cleanup_spawn()
+ ubman.drain_console()
+ ubman.cleanup_spawn()
-def setup_pxe_boot(u_boot_console):
- f = u_boot_console.config.env.get('env__net_pxe_bootable_file', None)
+def setup_pxe_boot(ubman):
+ f = ubman.config.env.get('env__net_pxe_bootable_file', None)
if not f:
pytest.skip('No PXE bootable file to read')
- setup_networking(u_boot_console)
- bootfile = u_boot_console.run_command('echo $bootfile')
+ setup_networking(ubman)
+ bootfile = ubman.run_command('echo $bootfile')
if not bootfile:
bootfile = '<NULL>'
return f, bootfile
@pytest.mark.buildconfigspec('cmd_pxe')
-def test_net_pxe_boot(u_boot_console):
+def test_net_pxe_boot(ubman):
"""Test the pxe boot command.
A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -219,19 +219,19 @@
The details of the file to download are provided by the boardenv_* file;
see the comment at the beginning of this file.
"""
- if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+ if ubman.config.env.get('env__pxe_boot_test_skip', True):
pytest.skip('PXE boot test is not enabled!')
- f, bootfile = setup_pxe_boot(u_boot_console)
+ f, bootfile = setup_pxe_boot(ubman)
addr = f.get('addr', None)
- timeout = f.get('timeout', u_boot_console.p.timeout)
+ timeout = f.get('timeout', ubman.p.timeout)
fn = f['fn']
if addr:
- u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+ ubman.run_command('setenv pxefile_addr_r %x' % addr)
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command('pxe get')
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command('pxe get')
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
@@ -250,18 +250,18 @@
else:
pxe_boot_cmd = 'pxe boot %x' % addr
- with u_boot_console.enable_check(
+ with ubman.enable_check(
chk_type, chk_pattern
- ), u_boot_console.temporary_timeout(timeout):
+ ), ubman.temporary_timeout(timeout):
try:
- u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
- u_boot_console.wait_for(pattern)
+ ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
+ ubman.wait_for(pattern)
finally:
- u_boot_console.drain_console()
- u_boot_console.cleanup_spawn()
+ ubman.drain_console()
+ ubman.cleanup_spawn()
@pytest.mark.buildconfigspec('cmd_pxe')
-def test_net_pxe_boot_config(u_boot_console):
+def test_net_pxe_boot_config(ubman):
"""Test the pxe boot command by selecting different combination of labels
A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -270,12 +270,12 @@
The details of the file to download are provided by the boardenv_* file;
see the comment at the beginning of this file.
"""
- if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+ if ubman.config.env.get('env__pxe_boot_test_skip', True):
pytest.skip('PXE boot test is not enabled!')
- f, bootfile = setup_pxe_boot(u_boot_console)
+ f, bootfile = setup_pxe_boot(ubman)
addr = f.get('addr', None)
- timeout = f.get('timeout', u_boot_console.p.timeout)
+ timeout = f.get('timeout', ubman.p.timeout)
fn = f['fn']
local_label = f['local_label']
empty_label = f['empty_label']
@@ -283,10 +283,10 @@
exp_str_empty = f['exp_str_empty']
if addr:
- u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+ ubman.run_command('setenv pxefile_addr_r %x' % addr)
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command('pxe get')
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command('pxe get')
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
@@ -305,20 +305,20 @@
else:
pxe_boot_cmd = 'pxe boot %x' % addr
- with u_boot_console.enable_check(
+ with ubman.enable_check(
chk_type, chk_pattern
- ), u_boot_console.temporary_timeout(timeout):
+ ), ubman.temporary_timeout(timeout):
try:
- u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+ ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
# pxe config is loaded where multiple labels are there and need to
# select particular label to boot and check for expected string
# In this case, local label is selected and it should look for
# localcmd env variable and if that variable is not defined it
# should not boot it and come out to u-boot prompt
- u_boot_console.wait_for('Enter choice:')
- u_boot_console.run_command(local_label, wait_for_prompt=False)
- expected_str = u_boot_console.p.expect([exp_str_local])
+ ubman.wait_for('Enter choice:')
+ ubman.run_command(local_label, wait_for_prompt=False)
+ expected_str = ubman.p.expect([exp_str_local])
assert (
expected_str == 0
), f'Expected string: {exp_str_local} did not match!'
@@ -326,21 +326,21 @@
# In this case, empty label is selected and it should look for
# kernel image path and if it is not set it should fail it and load
# default label to boot
- u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
- u_boot_console.wait_for('Enter choice:')
- u_boot_console.run_command(empty_label, wait_for_prompt=False)
- expected_str = u_boot_console.p.expect([exp_str_empty])
+ ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
+ ubman.wait_for('Enter choice:')
+ ubman.run_command(empty_label, wait_for_prompt=False)
+ expected_str = ubman.p.expect([exp_str_empty])
assert (
expected_str == 0
), f'Expected string: {exp_str_empty} did not match!'
- u_boot_console.wait_for(pattern)
+ ubman.wait_for(pattern)
finally:
- u_boot_console.drain_console()
- u_boot_console.cleanup_spawn()
+ ubman.drain_console()
+ ubman.cleanup_spawn()
@pytest.mark.buildconfigspec('cmd_pxe')
-def test_net_pxe_boot_config_invalid(u_boot_console):
+def test_net_pxe_boot_config_invalid(ubman):
"""Test the pxe boot command by selecting invalid label
A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -349,21 +349,21 @@
The details of the file to download are provided by the boardenv_* file;
see the comment at the beginning of this file.
"""
- if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+ if ubman.config.env.get('env__pxe_boot_test_skip', True):
pytest.skip('PXE boot test is not enabled!')
- f, bootfile = setup_pxe_boot(u_boot_console)
+ f, bootfile = setup_pxe_boot(ubman)
addr = f.get('addr', None)
- timeout = f.get('timeout', u_boot_console.p.timeout)
+ timeout = f.get('timeout', ubman.p.timeout)
fn = f['fn']
invalid_label = f['invalid_label']
exp_str_invalid = f['exp_str_invalid']
if addr:
- u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+ ubman.run_command('setenv pxefile_addr_r %x' % addr)
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command('pxe get')
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command('pxe get')
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
@@ -379,22 +379,22 @@
else:
pxe_boot_cmd = 'pxe boot %x' % addr
- with u_boot_console.temporary_timeout(timeout):
+ with ubman.temporary_timeout(timeout):
try:
- u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+ ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
# pxe config is loaded where multiple labels are there and need to
# select particular label to boot and check for expected string
# In this case invalid label is selected, it should load invalid
# label and if it fails it should load the default label to boot
- u_boot_console.wait_for('Enter choice:')
- u_boot_console.run_command(invalid_label, wait_for_prompt=False)
- expected_str = u_boot_console.p.expect([exp_str_invalid])
+ ubman.wait_for('Enter choice:')
+ ubman.run_command(invalid_label, wait_for_prompt=False)
+ expected_str = ubman.p.expect([exp_str_invalid])
assert (
expected_str == 0
), f'Expected string: {exp_str_invalid} did not match!'
- u_boot_console.wait_for(pattern)
+ ubman.wait_for(pattern)
finally:
- u_boot_console.drain_console()
- u_boot_console.cleanup_spawn()
+ ubman.drain_console()
+ ubman.cleanup_spawn()
diff --git a/test/py/tests/test_of_migrate.py b/test/py/tests/test_of_migrate.py
index 910f7c0..ab89332 100644
--- a/test/py/tests/test_of_migrate.py
+++ b/test/py/tests/test_of_migrate.py
@@ -7,18 +7,18 @@
import os
import pytest
-import u_boot_utils as util
+import utils
# This is needed for Azure, since the default '..' directory is not writeable
TMPDIR1 = '/tmp/test_no_migrate'
TMPDIR2 = '/tmp/test_no_migrate_spl'
TMPDIR3 = '/tmp/test_migrate'
-def build_for_migrate(cons, replace_pair, board, tmpdir, disable_migrate=True):
+def build_for_migrate(ubman, replace_pair, board, tmpdir, disable_migrate=True):
"""Build an updated U-Boot with a slightly modified device tree
Args:
- cons (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
replace_pair (tuple):
String to find
String to replace it with
@@ -26,15 +26,15 @@
tmpdir (str): Temporary directory to use
disable_migrate (bool): True to disable CONFIG_OF_TAG_MIGRATE in build
"""
- srcdir = cons.config.source_dir
- build_dir = cons.config.build_dir
+ srcdir = ubman.config.source_dir
+ build_dir = ubman.config.build_dir
# Get the source for the existing dts
dt_dir = os.path.join(build_dir, 'arch', 'sandbox', 'dts')
orig_fname = os.path.join(dt_dir, 'sandbox.dtb')
out_dts = os.path.join(dt_dir, 'sandbox_out.dts')
- util.run_and_log(cons, ['dtc', orig_fname, '-I', 'dtb', '-O', 'dts',
- '-o', out_dts])
+ utils.run_and_log(ubman, ['dtc', orig_fname, '-I', 'dtb', '-O', 'dts',
+ '-o', out_dts])
# Update it to use an old tag
with open(out_dts) as inf:
@@ -45,7 +45,7 @@
with open(dts_fname, 'w') as outf:
print(data, file=outf)
dtb_fname = os.path.join(dt_dir, 'sandbox_oldtag.dtb')
- util.run_and_log(cons, ['dtc', dts_fname, '-o', dtb_fname])
+ utils.run_and_log(ubman, ['dtc', dts_fname, '-o', dtb_fname])
migrate = ['-a', '~CONFIG_OF_TAG_MIGRATE'] if disable_migrate else []
@@ -54,24 +54,23 @@
env['EXT_DTB'] = dtb_fname
env['DEVICE_TREE'] = 'sandbox_new'
env['NO_LTO'] = '1' # Speed up build
- out = util.run_and_log(
- cons, ['./tools/buildman/buildman', '-m', '--board', board,
+ out = utils.run_and_log(
+ ubman, ['./tools/buildman/buildman', '-m', '--board', board,
*migrate, '-w', '-o', tmpdir], ignore_errors=True, env=env)
return out
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
-def test_of_no_migrate(u_boot_console):
+def test_of_no_migrate(ubman):
"""Test sandbox with old boot phase tags like u-boot,dm-pre-proper"""
- cons = u_boot_console
- build_for_migrate(cons, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
+ build_for_migrate(ubman, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
'sandbox', TMPDIR1)
# It should fail to run, since the lcd device will not be bound before
# relocation. so won't get its frame-buffer memory
- out = util.run_and_log(
- cons, [os.path.join(TMPDIR1, 'u-boot'), '-D', '-c', 'help'],
+ out = utils.run_and_log(
+ ubman, [os.path.join(TMPDIR1, 'u-boot'), '-D', '-c', 'help'],
ignore_errors=True)
assert "Video device 'lcd' cannot allocate frame buffer memory" in out
@@ -80,11 +79,10 @@
@pytest.mark.boardspec('sandbox_spl')
@pytest.mark.boardspec('spl_of_platdata_inst')
@pytest.mark.boardspec('!sandbox_tpl')
-def test_of_no_migrate_spl(u_boot_console):
+def test_of_no_migrate_spl(ubman):
"""Test sandbox with old boot phase tags like u-boot,dm-spl"""
- cons = u_boot_console
- out = build_for_migrate(cons, ['bootph-pre-ram', 'u-boot,dm-spl'],
+ out = build_for_migrate(ubman, ['bootph-pre-ram', 'u-boot,dm-spl'],
'sandbox_spl', TMPDIR2)
# It should fail to build, since the SPL DT will not include 'spl-test'
@@ -94,15 +92,14 @@
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
-def test_of_migrate(u_boot_console):
+def test_of_migrate(ubman):
"""Test sandbox shows a message when tags were migrated"""
- cons = u_boot_console
- build_for_migrate(cons, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
+ build_for_migrate(ubman, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
'sandbox', TMPDIR3, disable_migrate=False)
# It should show a migration message
- out = util.run_and_log(
- cons, [os.path.join(TMPDIR3, 'u-boot'), '-D', '-c', 'help'],
+ out = utils.run_and_log(
+ ubman, [os.path.join(TMPDIR3, 'u-boot'), '-D', '-c', 'help'],
ignore_errors=True)
assert "Warning: Device tree includes old 'u-boot,dm-' tags" in out
diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py
index 51a1884..d31fa55 100644
--- a/test/py/tests/test_ofplatdata.py
+++ b/test/py/tests/test_ofplatdata.py
@@ -2,16 +2,15 @@
# Copyright (c) 2016 Google, Inc
import pytest
-import u_boot_utils as util
+import utils
@pytest.mark.boardspec('sandbox_spl')
@pytest.mark.buildconfigspec('spl_of_platdata')
-def test_spl_devicetree(u_boot_console):
+def test_spl_devicetree(ubman):
"""Test content of spl device-tree"""
- cons = u_boot_console
- dtb = cons.config.build_dir + '/spl/u-boot-spl.dtb'
- fdtgrep = cons.config.build_dir + '/tools/fdtgrep'
- output = util.run_and_log(cons, [fdtgrep, '-l', dtb])
+ dtb = ubman.config.build_dir + '/spl/u-boot-spl.dtb'
+ fdtgrep = ubman.config.build_dir + '/tools/fdtgrep'
+ output = utils.run_and_log(ubman, [fdtgrep, '-l', dtb])
assert "bootph-all" not in output
assert "bootph-some-ram" not in output
diff --git a/test/py/tests/test_optee_rpmb.py b/test/py/tests/test_optee_rpmb.py
index 8a081b5..04b3b5e 100644
--- a/test/py/tests/test_optee_rpmb.py
+++ b/test/py/tests/test_optee_rpmb.py
@@ -7,14 +7,14 @@
"""
import pytest
-import u_boot_utils as util
+import utils
@pytest.mark.buildconfigspec('cmd_optee_rpmb')
-def test_optee_rpmb_read_write(u_boot_console):
+def test_optee_rpmb_read_write(ubman):
"""Test OP-TEE RPMB cmd read/write
"""
- response = u_boot_console.run_command('optee_rpmb write_pvalue test_variable test_value')
+ response = ubman.run_command('optee_rpmb write_pvalue test_variable test_value')
assert response == 'Wrote 11 bytes'
- response = u_boot_console.run_command('optee_rpmb read_pvalue test_variable 11')
- assert response == 'Read 11 bytes, value = test_value'
\ No newline at end of file
+ response = ubman.run_command('optee_rpmb read_pvalue test_variable 11')
+ assert response == 'Read 11 bytes, value = test_value'
diff --git a/test/py/tests/test_part.py b/test/py/tests/test_part.py
index 2b51846..04c95a6 100644
--- a/test/py/tests/test_part.py
+++ b/test/py/tests/test_part.py
@@ -7,8 +7,8 @@
@pytest.mark.buildconfigspec('cmd_part')
@pytest.mark.buildconfigspec('partitions')
@pytest.mark.buildconfigspec('efi_partition')
-def test_part_types(u_boot_console):
+def test_part_types(ubman):
"""Test that `part types` prints a result which includes `EFI`."""
- output = u_boot_console.run_command('part types')
+ output = ubman.run_command('part types')
assert "Supported partition tables:" in output
assert "EFI" in output
diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py
index 794994e..ee79e84 100644
--- a/test/py/tests/test_pinmux.py
+++ b/test/py/tests/test_pinmux.py
@@ -1,27 +1,27 @@
# SPDX-License-Identifier: GPL-2.0
import pytest
-import u_boot_utils
+import utils
@pytest.mark.buildconfigspec('cmd_pinmux')
-def test_pinmux_usage_1(u_boot_console):
+def test_pinmux_usage_1(ubman):
"""Test that 'pinmux' command without parameters displays
pinmux usage."""
- output = u_boot_console.run_command('pinmux')
+ output = ubman.run_command('pinmux')
assert 'Usage:' in output
@pytest.mark.buildconfigspec('cmd_pinmux')
-def test_pinmux_usage_2(u_boot_console):
+def test_pinmux_usage_2(ubman):
"""Test that 'pinmux status' executed without previous "pinmux dev"
command displays error message."""
- output = u_boot_console.run_command('pinmux status')
+ output = ubman.run_command('pinmux status')
assert 'pin-controller device not selected' in output
@pytest.mark.buildconfigspec('cmd_pinmux')
@pytest.mark.boardspec('sandbox')
-def test_pinmux_status_all(u_boot_console):
+def test_pinmux_status_all(ubman):
"""Test that 'pinmux status -a' displays pin's muxing."""
- output = u_boot_console.run_command('pinmux status -a')
+ output = ubman.run_command('pinmux status -a')
assert ('pinctrl-gpio:' in output)
assert ('a5 : gpio output .' in output)
@@ -40,36 +40,36 @@
@pytest.mark.buildconfigspec('cmd_pinmux')
@pytest.mark.boardspec('sandbox')
-def test_pinmux_list(u_boot_console):
+def test_pinmux_list(ubman):
"""Test that 'pinmux list' returns the pin-controller list."""
- output = u_boot_console.run_command('pinmux list')
+ output = ubman.run_command('pinmux list')
assert 'sandbox_pinctrl' in output
@pytest.mark.buildconfigspec('cmd_pinmux')
-def test_pinmux_dev_bad(u_boot_console):
+def test_pinmux_dev_bad(ubman):
"""Test that 'pinmux dev' returns an error when trying to select a
wrong pin controller."""
pincontroller = 'bad_pin_controller_name'
- output = u_boot_console.run_command('pinmux dev ' + pincontroller)
+ output = ubman.run_command('pinmux dev ' + pincontroller)
expected_output = 'Can\'t get the pin-controller: ' + pincontroller + '!'
assert (expected_output in output)
@pytest.mark.buildconfigspec('cmd_pinmux')
@pytest.mark.boardspec('sandbox')
-def test_pinmux_dev(u_boot_console):
+def test_pinmux_dev(ubman):
"""Test that 'pinmux dev' select the wanted pin controller."""
pincontroller = 'pinctrl'
- output = u_boot_console.run_command('pinmux dev ' + pincontroller)
+ output = ubman.run_command('pinmux dev ' + pincontroller)
expected_output = 'dev: ' + pincontroller
assert (expected_output in output)
@pytest.mark.buildconfigspec('cmd_pinmux')
@pytest.mark.boardspec('sandbox')
-def test_pinmux_status(u_boot_console):
+def test_pinmux_status(ubman):
"""Test that 'pinmux status' displays selected pincontroller's pin
muxing descriptions."""
- u_boot_console.run_command('pinmux dev pinctrl')
- output = u_boot_console.run_command('pinmux status')
+ ubman.run_command('pinmux dev pinctrl')
+ output = ubman.run_command('pinmux status')
assert (not 'pinctrl-gpio:' in output)
assert (not 'pinctrl:' in output)
diff --git a/test/py/tests/test_pstore.py b/test/py/tests/test_pstore.py
index 5a35724..70e0750 100644
--- a/test/py/tests/test_pstore.py
+++ b/test/py/tests/test_pstore.py
@@ -3,7 +3,7 @@
# Author: Frédéric Danis <frederic.danis@collabora.com>
import pytest
-import u_boot_utils
+import utils
import os
import tempfile
import shutil
@@ -15,63 +15,63 @@
PSTORE_CONSOLE='test/py/tests/test_pstore_data_console.hex'
ADDR=0x01000008
-def load_pstore(u_boot_console):
+def load_pstore(ubman):
"""Load PStore records from sample files"""
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'host load hostfs - 0x%x %s' % (PSTORE_ADDR,
- os.path.join(u_boot_console.config.source_dir, PSTORE_PANIC1)),
+ os.path.join(ubman.config.source_dir, PSTORE_PANIC1)),
'host load hostfs - 0x%x %s' % (PSTORE_ADDR + 4096,
- os.path.join(u_boot_console.config.source_dir, PSTORE_PANIC2)),
+ os.path.join(ubman.config.source_dir, PSTORE_PANIC2)),
'host load hostfs - 0x%x %s' % (PSTORE_ADDR + 253 * 4096,
- os.path.join(u_boot_console.config.source_dir, PSTORE_CONSOLE)),
+ os.path.join(ubman.config.source_dir, PSTORE_CONSOLE)),
'pstore set 0x%x 0x%x' % (PSTORE_ADDR, PSTORE_LENGTH)])
-def checkfile(u_boot_console, path, filesize, checksum):
+def checkfile(ubman, path, filesize, checksum):
"""Check file against MD5 checksum"""
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'load hostfs - %x %s' % (ADDR, path),
'printenv filesize'])
assert('filesize=%x' % (filesize) in ''.join(output))
- output = u_boot_console.run_command_list([
+ output = ubman.run_command_list([
'md5sum %x $filesize' % ADDR,
'setenv filesize'])
assert(checksum in ''.join(output))
@pytest.mark.buildconfigspec('cmd_pstore')
-def test_pstore_display_all_records(u_boot_console):
+def test_pstore_display_all_records(ubman):
"""Test that pstore displays all records."""
- u_boot_console.run_command('')
- load_pstore(u_boot_console)
- response = u_boot_console.run_command('pstore display')
+ ubman.run_command('')
+ load_pstore(ubman)
+ response = ubman.run_command('pstore display')
assert('**** Dump' in response)
assert('**** Console' in response)
@pytest.mark.buildconfigspec('cmd_pstore')
-def test_pstore_display_one_record(u_boot_console):
+def test_pstore_display_one_record(ubman):
"""Test that pstore displays only one record."""
- u_boot_console.run_command('')
- load_pstore(u_boot_console)
- response = u_boot_console.run_command('pstore display dump 1')
+ ubman.run_command('')
+ load_pstore(ubman)
+ response = ubman.run_command('pstore display dump 1')
assert('Panic#2 Part1' in response)
assert('**** Console' not in response)
@pytest.mark.buildconfigspec('cmd_pstore')
-def test_pstore_save_records(u_boot_console):
+def test_pstore_save_records(ubman):
"""Test that pstore saves all records."""
outdir = tempfile.mkdtemp()
- u_boot_console.run_command('')
- load_pstore(u_boot_console)
- u_boot_console.run_command('pstore save hostfs - %s' % (outdir))
+ ubman.run_command('')
+ load_pstore(ubman)
+ ubman.run_command('pstore save hostfs - %s' % (outdir))
- checkfile(u_boot_console, '%s/dmesg-ramoops-0' % (outdir), 3798, '8059335ab4cfa62c77324c491659c503')
- checkfile(u_boot_console, '%s/dmesg-ramoops-1' % (outdir), 4035, '3ff30df3429d81939c75d0070b5187b9')
- checkfile(u_boot_console, '%s/console-ramoops-0' % (outdir), 4084, 'bb44de4a9b8ebd9b17ae98003287325b')
+ checkfile(ubman, '%s/dmesg-ramoops-0' % (outdir), 3798, '8059335ab4cfa62c77324c491659c503')
+ checkfile(ubman, '%s/dmesg-ramoops-1' % (outdir), 4035, '3ff30df3429d81939c75d0070b5187b9')
+ checkfile(ubman, '%s/console-ramoops-0' % (outdir), 4084, 'bb44de4a9b8ebd9b17ae98003287325b')
shutil.rmtree(outdir)
diff --git a/test/py/tests/test_qfw.py b/test/py/tests/test_qfw.py
index 8b668c9..844cd3d 100644
--- a/test/py/tests/test_qfw.py
+++ b/test/py/tests/test_qfw.py
@@ -6,20 +6,20 @@
import pytest
@pytest.mark.buildconfigspec('cmd_qfw')
-def test_qfw_cpus(u_boot_console):
+def test_qfw_cpus(ubman):
"Test QEMU firmware config reports the CPU count."
- output = u_boot_console.run_command('qfw cpus')
+ output = ubman.run_command('qfw cpus')
# The actual number varies depending on the board under test, so only
# assert a non-zero output.
assert 'cpu(s) online' in output
assert '0 cpu(s) online' not in output
@pytest.mark.buildconfigspec('cmd_qfw')
-def test_qfw_list(u_boot_console):
+def test_qfw_list(ubman):
"Test QEMU firmware config lists devices."
- output = u_boot_console.run_command('qfw list')
+ output = ubman.run_command('qfw list')
# Assert either:
# 1) 'test-one', from the sandbox driver, or
# 2) 'bootorder', found in every real QEMU implementation.
diff --git a/test/py/tests/test_reset.py b/test/py/tests/test_reset.py
index 00fc31d..af079a70 100644
--- a/test/py/tests/test_reset.py
+++ b/test/py/tests/test_reset.py
@@ -24,15 +24,15 @@
import pytest
import test_000_version
-def setup_reset_env(u_boot_console):
- if u_boot_console.config.env.get('env__reset_test_skip', False):
+def setup_reset_env(ubman):
+ if ubman.config.env.get('env__reset_test_skip', False):
pytest.skip('reset test is not enabled')
- output = u_boot_console.run_command('echo $modeboot')
+ output = ubman.run_command('echo $modeboot')
if output:
bootmode = output
else:
- f = u_boot_console.config.env.get('env__reset_test', None)
+ f = ubman.config.env.get('env__reset_test', None)
if not f:
pytest.skip('bootmode cannot be determined')
bootmode = f.get('bootmode', 'jtagboot')
@@ -41,23 +41,23 @@
pytest.skip('skipping reset test due to jtag bootmode')
@pytest.mark.buildconfigspec('hush_parser')
-def test_reset(u_boot_console):
+def test_reset(ubman):
"""Test the reset command in non-JTAG bootmode.
It does COLD reset, which resets CPU, DDR and peripherals
"""
- setup_reset_env(u_boot_console)
- u_boot_console.run_command('reset', wait_for_reboot=True)
+ setup_reset_env(ubman)
+ ubman.run_command('reset', wait_for_reboot=True)
# Checks the u-boot command prompt's functionality after reset
- test_000_version.test_version(u_boot_console)
+ test_000_version.test_version(ubman)
@pytest.mark.buildconfigspec('hush_parser')
-def test_reset_w(u_boot_console):
+def test_reset_w(ubman):
"""Test the reset -w command in non-JTAG bootmode.
It does WARM reset, which resets CPU but keep DDR/peripherals active.
"""
- setup_reset_env(u_boot_console)
- u_boot_console.run_command('reset -w', wait_for_reboot=True)
+ setup_reset_env(ubman)
+ ubman.run_command('reset -w', wait_for_reboot=True)
# Checks the u-boot command prompt's functionality after reset
- test_000_version.test_version(u_boot_console)
+ test_000_version.test_version(ubman)
diff --git a/test/py/tests/test_sandbox_exit.py b/test/py/tests/test_sandbox_exit.py
index 706f5fa..9610adf 100644
--- a/test/py/tests/test_sandbox_exit.py
+++ b/test/py/tests/test_sandbox_exit.py
@@ -7,39 +7,39 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('sysreset_cmd_poweroff')
-def test_poweroff(u_boot_console):
+def test_poweroff(ubman):
"""Test that the "poweroff" command exits sandbox process."""
- u_boot_console.run_command('poweroff', wait_for_prompt=False)
- assert(u_boot_console.validate_exited())
+ ubman.run_command('poweroff', wait_for_prompt=False)
+ assert(ubman.validate_exited())
@pytest.mark.boardspec('sandbox')
-def test_ctrl_c(u_boot_console):
+def test_ctrl_c(ubman):
"""Test that sending SIGINT to sandbox causes it to exit."""
- u_boot_console.kill(signal.SIGINT)
- assert(u_boot_console.validate_exited())
+ ubman.kill(signal.SIGINT)
+ assert(ubman.validate_exited())
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_exception')
@pytest.mark.buildconfigspec('sandbox_crash_reset')
-def test_exception_reset(u_boot_console):
+def test_exception_reset(ubman):
"""Test that SIGILL causes a reset."""
- u_boot_console.run_command('exception undefined', wait_for_prompt=False)
- m = u_boot_console.p.expect(['resetting ...', 'U-Boot'])
+ ubman.run_command('exception undefined', wait_for_prompt=False)
+ m = ubman.p.expect(['resetting ...', 'U-Boot'])
if m != 0:
raise Exception('SIGILL did not lead to reset')
- m = u_boot_console.p.expect(['U-Boot', '=>'])
+ m = ubman.p.expect(['U-Boot', '=>'])
if m != 0:
raise Exception('SIGILL did not lead to reset')
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_exception')
@pytest.mark.notbuildconfigspec('sandbox_crash_reset')
-def test_exception_exit(u_boot_console):
+def test_exception_exit(ubman):
"""Test that SIGILL causes a reset."""
- u_boot_console.run_command('exception undefined', wait_for_prompt=False)
- assert(u_boot_console.validate_exited())
+ ubman.run_command('exception undefined', wait_for_prompt=False)
+ assert(ubman.validate_exited())
diff --git a/test/py/tests/test_sandbox_opts.py b/test/py/tests/test_sandbox_opts.py
index 422b43c..48f5b31 100644
--- a/test/py/tests/test_sandbox_opts.py
+++ b/test/py/tests/test_sandbox_opts.py
@@ -4,27 +4,25 @@
import pytest
-import u_boot_utils as util
+import utils
# This is needed for Azure, since the default '..' directory is not writeable
TMPDIR = '/tmp/test_cmdline'
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
-def test_sandbox_cmdline(u_boot_console):
+def test_sandbox_cmdline(ubman):
"""Test building sandbox without CONFIG_CMDLINE"""
- cons = u_boot_console
- out = util.run_and_log(
- cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ utils.run_and_log(
+ ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
'-a', '~CMDLINE', '-o', TMPDIR])
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
-def test_sandbox_lto(u_boot_console):
+def test_sandbox_lto(ubman):
"""Test building sandbox without CONFIG_LTO"""
- cons = u_boot_console
- out = util.run_and_log(
- cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ utils.run_and_log(
+ ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
'-a', '~LTO', '-o', TMPDIR])
diff --git a/test/py/tests/test_saveenv.py b/test/py/tests/test_saveenv.py
index 7faa3bd..019b229 100644
--- a/test/py/tests/test_saveenv.py
+++ b/test/py/tests/test_saveenv.py
@@ -28,15 +28,15 @@
import uuid
# Setup the env
-def setup_saveenv_env(u_boot_console):
- if u_boot_console.config.env.get('env__saveenv_test_skip', False):
+def setup_saveenv_env(ubman):
+ if ubman.config.env.get('env__saveenv_test_skip', False):
pytest.skip('saveenv test is not enabled')
- output = u_boot_console.run_command('echo $modeboot')
+ output = ubman.run_command('echo $modeboot')
if output:
bootmode = output
else:
- f = u_boot_console.config.env.get('env__saveenv_test', None)
+ f = ubman.config.env.get('env__saveenv_test', None)
if not f:
pytest.skip('bootmode cannot be determined')
bootmode = f.get('bootmode', 'jtagboot')
@@ -45,39 +45,39 @@
pytest.skip('skipping saveenv test due to jtag bootmode')
# Check return code
-def ret_code(u_boot_console):
- return u_boot_console.run_command('echo $?')
+def ret_code(ubman):
+ return ubman.run_command('echo $?')
# Verify env variable
-def check_env(u_boot_console, var_name, var_value):
+def check_env(ubman, var_name, var_value):
if var_value:
- output = u_boot_console.run_command(f'printenv {var_name}')
+ output = ubman.run_command(f'printenv {var_name}')
var_value = str(var_value)
if (var_value.startswith("'") and var_value.endswith("'")) or (
var_value.startswith('"') and var_value.endswith('"')
):
var_value = var_value.split(var_value[-1])[1]
assert var_value in output
- assert ret_code(u_boot_console).endswith('0')
+ assert ret_code(ubman).endswith('0')
else:
- u_boot_console.p.send(f'printenv {var_name}\n')
- output = u_boot_console.p.expect(['not defined'])
+ ubman.p.send(f'printenv {var_name}\n')
+ output = ubman.p.expect(['not defined'])
assert output == 0
- assert ret_code(u_boot_console).endswith('1')
+ assert ret_code(ubman).endswith('1')
# Set env variable
-def set_env(u_boot_console, var_name, var_value):
- u_boot_console.run_command(f'setenv {var_name} {var_value}')
- assert ret_code(u_boot_console).endswith('0')
- check_env(u_boot_console, var_name, var_value)
+def set_env(ubman, var_name, var_value):
+ ubman.run_command(f'setenv {var_name} {var_value}')
+ assert ret_code(ubman).endswith('0')
+ check_env(ubman, var_name, var_value)
@pytest.mark.buildconfigspec('cmd_saveenv')
@pytest.mark.buildconfigspec('hush_parser')
-def test_saveenv(u_boot_console):
+def test_saveenv(ubman):
"""Test the saveenv command in non-JTAG bootmode.
It saves the U-Boot environment in persistent storage.
"""
- setup_saveenv_env(u_boot_console)
+ setup_saveenv_env(ubman)
# Set env for random mac address
rand_mac = '%02x:%02x:%02x:%02x:%02x:%02x' % (
@@ -88,50 +88,50 @@
random.randint(0, 255),
random.randint(0, 255),
)
- set_env(u_boot_console, 'mac_addr', rand_mac)
+ set_env(ubman, 'mac_addr', rand_mac)
# Set env for random IPv4 address
rand_ipv4 = ipaddress.IPv4Address._string_from_ip_int(
random.randint(0, ipaddress.IPv4Address._ALL_ONES)
)
- set_env(u_boot_console, 'ipv4_addr', rand_ipv4)
+ set_env(ubman, 'ipv4_addr', rand_ipv4)
# Set env for random IPv6 address
rand_ipv6 = ipaddress.IPv6Address._string_from_ip_int(
random.randint(0, ipaddress.IPv6Address._ALL_ONES)
)
- set_env(u_boot_console, 'ipv6_addr', rand_ipv6)
+ set_env(ubman, 'ipv6_addr', rand_ipv6)
# Set env for random number
rand_num = random.randrange(1, 10**9)
- set_env(u_boot_console, 'num_var', rand_num)
+ set_env(ubman, 'num_var', rand_num)
# Set env for uuid
uuid_str = uuid.uuid4().hex.lower()
- set_env(u_boot_console, 'uuid_var', uuid_str)
+ set_env(ubman, 'uuid_var', uuid_str)
# Set env for random string including special characters
sc = "!#%&()*+,-./:;<=>?@[\\]^_`{|}~"
rand_str = ''.join(
random.choices(' ' + string.ascii_letters + sc + string.digits, k=300)
)
- set_env(u_boot_console, 'str_var', f'"{rand_str}"')
+ set_env(ubman, 'str_var', f'"{rand_str}"')
# Set env for empty string
- set_env(u_boot_console, 'empty_var', '')
+ set_env(ubman, 'empty_var', '')
# Save the env variables
- u_boot_console.run_command('saveenv')
- assert ret_code(u_boot_console).endswith('0')
+ ubman.run_command('saveenv')
+ assert ret_code(ubman).endswith('0')
# Reboot
- u_boot_console.run_command('reset', wait_for_reboot=True)
+ ubman.run_command('reset', wait_for_reboot=True)
# Verify the saved env variables
- check_env(u_boot_console, 'mac_addr', rand_mac)
- check_env(u_boot_console, 'ipv4_addr', rand_ipv4)
- check_env(u_boot_console, 'ipv6_addr', rand_ipv6)
- check_env(u_boot_console, 'num_var', rand_num)
- check_env(u_boot_console, 'uuid_var', uuid_str)
- check_env(u_boot_console, 'str_var', rand_str)
- check_env(u_boot_console, 'empty_var', '')
+ check_env(ubman, 'mac_addr', rand_mac)
+ check_env(ubman, 'ipv4_addr', rand_ipv4)
+ check_env(ubman, 'ipv6_addr', rand_ipv6)
+ check_env(ubman, 'num_var', rand_num)
+ check_env(ubman, 'uuid_var', uuid_str)
+ check_env(ubman, 'str_var', rand_str)
+ check_env(ubman, 'empty_var', '')
diff --git a/test/py/tests/test_scp03.py b/test/py/tests/test_scp03.py
index 1a104b3..414b425 100644
--- a/test/py/tests/test_scp03.py
+++ b/test/py/tests/test_scp03.py
@@ -11,17 +11,17 @@
"""
import pytest
-import u_boot_utils as util
+import utils
@pytest.mark.buildconfigspec('cmd_scp03')
-def test_scp03(u_boot_console):
+def test_scp03(ubman):
"""Enable and provision keys with SCP03
"""
success_str1 = "SCP03 is enabled"
success_str2 = "SCP03 is provisioned"
- response = u_boot_console.run_command('scp03 enable')
+ response = ubman.run_command('scp03 enable')
assert success_str1 in response
- response = u_boot_console.run_command('scp03 provision')
+ response = ubman.run_command('scp03 provision')
assert success_str2 in response
diff --git a/test/py/tests/test_scsi.py b/test/py/tests/test_scsi.py
index 445693c..2a35e47 100644
--- a/test/py/tests/test_scsi.py
+++ b/test/py/tests/test_scsi.py
@@ -19,8 +19,8 @@
}
"""
-def scsi_setup(u_boot_console):
- f = u_boot_console.config.env.get('env__scsi_device_test', None)
+def scsi_setup(ubman):
+ f = ubman.config.env.get('env__scsi_device_test', None)
if not f:
pytest.skip('No SCSI device to test')
@@ -39,54 +39,54 @@
return dev_num, dev_type, dev_size
@pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_reset(u_boot_console):
- dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
- output = u_boot_console.run_command('scsi reset')
+def test_scsi_reset(ubman):
+ dev_num, dev_type, dev_size = scsi_setup(ubman)
+ output = ubman.run_command('scsi reset')
assert f'Device {dev_num}:' in output
assert f'Type: {dev_type}' in output
assert f'Capacity: {dev_size}' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_info(u_boot_console):
- dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
- output = u_boot_console.run_command('scsi info')
+def test_scsi_info(ubman):
+ dev_num, dev_type, dev_size = scsi_setup(ubman)
+ output = ubman.run_command('scsi info')
assert f'Device {dev_num}:' in output
assert f'Type: {dev_type}' in output
assert f'Capacity: {dev_size}' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_scan(u_boot_console):
- dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
- output = u_boot_console.run_command('scsi scan')
+def test_scsi_scan(ubman):
+ dev_num, dev_type, dev_size = scsi_setup(ubman)
+ output = ubman.run_command('scsi scan')
assert f'Device {dev_num}:' in output
assert f'Type: {dev_type}' in output
assert f'Capacity: {dev_size}' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_dev(u_boot_console):
- dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
- output = u_boot_console.run_command('scsi device')
+def test_scsi_dev(ubman):
+ dev_num, dev_type, dev_size = scsi_setup(ubman)
+ output = ubman.run_command('scsi device')
assert 'no scsi devices available' not in output
assert f'device {dev_num}:' in output
assert f'Type: {dev_type}' in output
assert f'Capacity: {dev_size}' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- output = u_boot_console.run_command('scsi device %d' % dev_num)
+ output = ubman.run_command('scsi device %d' % dev_num)
assert 'is now current device' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_part(u_boot_console):
- test_scsi_dev(u_boot_console)
- output = u_boot_console.run_command('scsi part')
+def test_scsi_part(ubman):
+ test_scsi_dev(ubman)
+ output = ubman.run_command('scsi part')
assert 'Partition Map for scsi device' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
diff --git a/test/py/tests/test_semihosting/test_hostfs.py b/test/py/tests/test_semihosting/test_hostfs.py
index 51f6fa7..1bead69 100644
--- a/test/py/tests/test_semihosting/test_hostfs.py
+++ b/test/py/tests/test_semihosting/test_hostfs.py
@@ -6,28 +6,28 @@
import pytest
@pytest.mark.buildconfigspec('semihosting')
-def test_semihosting_hostfs(u_boot_console, semihosting_data):
+def test_semihosting_hostfs(ubman, semihosting_data):
""" Unit test for semihosting
Args:
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
semihosting_data -- Path to the disk image used for testing.
"""
- response = u_boot_console.run_command(
+ response = ubman.run_command(
f'load hostfs - $loadaddr {semihosting_data}')
assert '11 bytes read' in response
- response = u_boot_console.run_command(
+ response = ubman.run_command(
'crc32 $loadaddr $filesize')
assert '==> 60cfccfc' in response
- u_boot_console.run_command(
+ ubman.run_command(
f'save hostfs - $loadaddr {semihosting_data} 11 11')
- response = u_boot_console.run_command(
+ response = ubman.run_command(
f'load hostfs - $loadaddr {semihosting_data} 4 13')
assert '4 bytes read' in response
- response = u_boot_console.run_command(
+ response = ubman.run_command(
'crc32 $loadaddr $filesize')
assert '==> e29063ea' in response
diff --git a/test/py/tests/test_sf.py b/test/py/tests/test_sf.py
index adf8b7d..5b4ba80 100644
--- a/test/py/tests/test_sf.py
+++ b/test/py/tests/test_sf.py
@@ -5,7 +5,7 @@
import re
import pytest
import random
-import u_boot_utils
+import utils
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -44,11 +44,11 @@
)
"""
-def sf_prepare(u_boot_console, env__sf_config):
+def sf_prepare(ubman, env__sf_config):
"""Check global state of the SPI Flash before running any test.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__sf_config: The single SPI Flash device configuration on which to
run the tests.
@@ -57,7 +57,7 @@
"""
sf_params = {}
- sf_params['ram_base'] = u_boot_utils.find_ram_base(u_boot_console)
+ sf_params['ram_base'] = utils.find_ram_base(ubman)
probe_id = env__sf_config.get('id', 0)
speed = env__sf_config.get('speed', 0)
@@ -69,7 +69,7 @@
cmd = 'sf probe %d %d' % (probe_id, sf_params['speed'])
- output = u_boot_console.run_command(cmd)
+ output = ubman.run_command(cmd)
assert 'SF: Detected' in output, 'No Flash device available'
m = re.search('page size (.+?) Bytes', output)
@@ -101,12 +101,12 @@
return sf_params
-def sf_read(u_boot_console, env__sf_config, sf_params):
+def sf_read(ubman, env__sf_config, sf_params):
"""Helper function used to read and compute the CRC32 value of a section of
SPI Flash memory.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__sf_config: The single SPI Flash device configuration on which to
run the tests.
sf_params: SPI Flash parameters.
@@ -122,26 +122,26 @@
crc_expected = env__sf_config.get('crc32', None)
cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
- u_boot_console.run_command(cmd)
- crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+ ubman.run_command(cmd)
+ crc_pattern = utils.crc32(ubman, addr, count)
if crc_expected:
assert crc_pattern != crc_expected
cmd = 'sf read %08x %08x %x' % (addr, offset, count)
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert 'Read: OK' in response, 'Read operation failed'
- crc_readback = u_boot_utils.crc32(u_boot_console, addr, count)
+ crc_readback = utils.crc32(ubman, addr, count)
assert crc_pattern != crc_readback, 'sf read did not update RAM content.'
if crc_expected:
assert crc_readback == crc_expected
return crc_readback
-def sf_update(u_boot_console, env__sf_config, sf_params):
+def sf_update(ubman, env__sf_config, sf_params):
"""Helper function used to update a section of SPI Flash memory.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__sf_config: The single SPI Flash device configuration on which to
run the tests.
@@ -155,63 +155,63 @@
pattern = int(random.random() * 0xFF)
cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
- u_boot_console.run_command(cmd)
- crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+ ubman.run_command(cmd)
+ crc_pattern = utils.crc32(ubman, addr, count)
cmd = 'sf update %08x %08x %x' % (addr, offset, count)
- u_boot_console.run_command(cmd)
- crc_readback = sf_read(u_boot_console, env__sf_config, sf_params)
+ ubman.run_command(cmd)
+ crc_readback = sf_read(ubman, env__sf_config, sf_params)
assert crc_readback == crc_pattern
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_crc32')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_read(u_boot_console, env__sf_config):
- sf_params = sf_prepare(u_boot_console, env__sf_config)
- sf_read(u_boot_console, env__sf_config, sf_params)
+def test_sf_read(ubman, env__sf_config):
+ sf_params = sf_prepare(ubman, env__sf_config)
+ sf_read(ubman, env__sf_config, sf_params)
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_crc32')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_read_twice(u_boot_console, env__sf_config):
- sf_params = sf_prepare(u_boot_console, env__sf_config)
+def test_sf_read_twice(ubman, env__sf_config):
+ sf_params = sf_prepare(ubman, env__sf_config)
- crc1 = sf_read(u_boot_console, env__sf_config, sf_params)
+ crc1 = sf_read(ubman, env__sf_config, sf_params)
sf_params['ram_base'] += 0x100
- crc2 = sf_read(u_boot_console, env__sf_config, sf_params)
+ crc2 = sf_read(ubman, env__sf_config, sf_params)
assert crc1 == crc2, 'CRC32 of two successive read operation do not match'
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_crc32')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_erase(u_boot_console, env__sf_config):
+def test_sf_erase(ubman, env__sf_config):
if not env__sf_config.get('writeable', False):
pytest.skip('Flash config is tagged as not writeable')
- sf_params = sf_prepare(u_boot_console, env__sf_config)
+ sf_params = sf_prepare(ubman, env__sf_config)
addr = sf_params['ram_base']
offset = env__sf_config['offset']
count = sf_params['len']
cmd = 'sf erase %08x %x' % (offset, count)
- output = u_boot_console.run_command(cmd)
+ output = ubman.run_command(cmd)
assert 'Erased: OK' in output, 'Erase operation failed'
cmd = 'mw.b %08x ff %x' % (addr, count)
- u_boot_console.run_command(cmd)
- crc_ffs = u_boot_utils.crc32(u_boot_console, addr, count)
+ ubman.run_command(cmd)
+ crc_ffs = utils.crc32(ubman, addr, count)
- crc_read = sf_read(u_boot_console, env__sf_config, sf_params)
+ crc_read = sf_read(ubman, env__sf_config, sf_params)
assert crc_ffs == crc_read, 'Unexpected CRC32 after erase operation.'
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_crc32')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_update(u_boot_console, env__sf_config):
+def test_sf_update(ubman, env__sf_config):
if not env__sf_config.get('writeable', False):
pytest.skip('Flash config is tagged as not writeable')
- sf_params = sf_prepare(u_boot_console, env__sf_config)
- sf_update(u_boot_console, env__sf_config, sf_params)
+ sf_params = sf_prepare(ubman, env__sf_config)
+ sf_update(ubman, env__sf_config, sf_params)
diff --git a/test/py/tests/test_shell_basics.py b/test/py/tests/test_shell_basics.py
index 68a3f89..97e22af 100644
--- a/test/py/tests/test_shell_basics.py
+++ b/test/py/tests/test_shell_basics.py
@@ -7,39 +7,39 @@
pytestmark = pytest.mark.buildconfigspec('cmd_echo')
-def test_shell_execute(u_boot_console):
+def test_shell_execute(ubman):
"""Test any shell command."""
- response = u_boot_console.run_command('echo hello')
+ response = ubman.run_command('echo hello')
assert response.strip() == 'hello'
-def test_shell_semicolon_two(u_boot_console):
+def test_shell_semicolon_two(ubman):
"""Test two shell commands separate by a semi-colon."""
cmd = 'echo hello; echo world'
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
# This validation method ignores the exact whitespace between the strings
assert response.index('hello') < response.index('world')
-def test_shell_semicolon_three(u_boot_console):
+def test_shell_semicolon_three(ubman):
"""Test three shell commands separate by a semi-colon, with variable
expansion dependencies between them."""
cmd = 'setenv list 1; setenv list ${list}2; setenv list ${list}3; ' + \
'echo ${list}'
- response = u_boot_console.run_command(cmd)
+ response = ubman.run_command(cmd)
assert response.strip() == '123'
- u_boot_console.run_command('setenv list')
+ ubman.run_command('setenv list')
-def test_shell_run(u_boot_console):
+def test_shell_run(ubman):
"""Test the "run" shell command."""
- u_boot_console.run_command('setenv foo \'setenv monty 1; setenv python 2\'')
- u_boot_console.run_command('run foo')
- response = u_boot_console.run_command('echo ${monty}')
+ ubman.run_command('setenv foo \'setenv monty 1; setenv python 2\'')
+ ubman.run_command('run foo')
+ response = ubman.run_command('echo ${monty}')
assert response.strip() == '1'
- response = u_boot_console.run_command('echo ${python}')
+ response = ubman.run_command('echo ${python}')
assert response.strip() == '2'
- u_boot_console.run_command('setenv foo')
- u_boot_console.run_command('setenv monty')
- u_boot_console.run_command('setenv python')
+ ubman.run_command('setenv foo')
+ ubman.run_command('setenv monty')
+ ubman.run_command('setenv python')
diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py
index 8965fc3..f1bf34e 100644
--- a/test/py/tests/test_sleep.py
+++ b/test/py/tests/test_sleep.py
@@ -19,43 +19,43 @@
"""
-def test_sleep(u_boot_console):
+def test_sleep(ubman):
"""Test the sleep command, and validate that it sleeps for approximately
the correct amount of time."""
- sleep_skip = u_boot_console.config.env.get('env__sleep_accurate', True)
+ sleep_skip = ubman.config.env.get('env__sleep_accurate', True)
if not sleep_skip:
pytest.skip('sleep is not accurate')
- if u_boot_console.config.buildconfig.get('config_cmd_sleep', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_sleep', 'n') != 'y':
pytest.skip('sleep command not supported')
# 3s isn't too long, but is enough to cross a few second boundaries.
- sleep_time = u_boot_console.config.env.get('env__sleep_time', 3)
- sleep_margin = u_boot_console.config.env.get('env__sleep_margin', 0.25)
+ sleep_time = ubman.config.env.get('env__sleep_time', 3)
+ sleep_margin = ubman.config.env.get('env__sleep_margin', 0.25)
tstart = time.time()
- u_boot_console.run_command('sleep %d' % sleep_time)
+ ubman.run_command('sleep %d' % sleep_time)
tend = time.time()
elapsed = tend - tstart
assert elapsed >= (sleep_time - 0.01)
- if not u_boot_console.config.gdbserver:
+ if not ubman.config.gdbserver:
# margin is hopefully enough to account for any system overhead.
assert elapsed < (sleep_time + sleep_margin)
@pytest.mark.buildconfigspec("cmd_time")
-def test_time(u_boot_console):
+def test_time(ubman):
"""Test the time command, and validate that it gives approximately the
correct amount of command execution time."""
- sleep_skip = u_boot_console.config.env.get("env__sleep_accurate", True)
+ sleep_skip = ubman.config.env.get("env__sleep_accurate", True)
if not sleep_skip:
pytest.skip("sleep is not accurate")
- sleep_time = u_boot_console.config.env.get("env__sleep_time", 10)
- sleep_margin = u_boot_console.config.env.get("env__sleep_margin", 0.25)
- output = u_boot_console.run_command("time sleep %d" % sleep_time)
+ sleep_time = ubman.config.env.get("env__sleep_time", 10)
+ sleep_margin = ubman.config.env.get("env__sleep_margin", 0.25)
+ output = ubman.run_command("time sleep %d" % sleep_time)
execute_time = float(output.split()[1])
assert sleep_time >= (execute_time - 0.01)
- if not u_boot_console.config.gdbserver:
+ if not ubman.config.gdbserver:
# margin is hopefully enough to account for any system overhead.
assert sleep_time < (execute_time + sleep_margin)
diff --git a/test/py/tests/test_smbios.py b/test/py/tests/test_smbios.py
index 0405a9b..3b85a7c 100644
--- a/test/py/tests/test_smbios.py
+++ b/test/py/tests/test_smbios.py
@@ -7,9 +7,9 @@
@pytest.mark.buildconfigspec('cmd_smbios')
@pytest.mark.notbuildconfigspec('qfw_smbios')
@pytest.mark.notbuildconfigspec('sandbox')
-def test_cmd_smbios(u_boot_console):
+def test_cmd_smbios(ubman):
"""Run the smbios command"""
- output = u_boot_console.run_command('smbios')
+ output = ubman.run_command('smbios')
assert 'DMI type 127,' in output
@pytest.mark.buildconfigspec('cmd_smbios')
@@ -19,18 +19,18 @@
# QEMU v8.2.0 lacks SMBIOS support for RISC-V
# Once support is available in our Docker image we can remove the constraint.
@pytest.mark.notbuildconfigspec('riscv')
-def test_cmd_smbios_qemu(u_boot_console):
+def test_cmd_smbios_qemu(ubman):
"""Run the smbios command on QEMU"""
- output = u_boot_console.run_command('smbios')
+ output = ubman.run_command('smbios')
assert 'DMI type 1,' in output
assert 'Manufacturer: QEMU' in output
assert 'DMI type 127,' in output
@pytest.mark.buildconfigspec('cmd_smbios')
@pytest.mark.buildconfigspec('sandbox')
-def test_cmd_smbios_sandbox(u_boot_console):
+def test_cmd_smbios_sandbox(ubman):
"""Run the smbios command on the sandbox"""
- output = u_boot_console.run_command('smbios')
+ output = ubman.run_command('smbios')
assert 'DMI type 0,' in output
assert 'Vendor: U-Boot' in output
assert 'DMI type 1,' in output
@@ -43,9 +43,9 @@
@pytest.mark.buildconfigspec('cmd_smbios')
@pytest.mark.buildconfigspec('sysinfo_smbios')
@pytest.mark.buildconfigspec('generate_smbios_table_verbose')
-def test_cmd_smbios_sysinfo_verbose(u_boot_console):
+def test_cmd_smbios_sysinfo_verbose(ubman):
"""Run the smbios command"""
- output = u_boot_console.run_command('smbios')
+ output = ubman.run_command('smbios')
assert 'DMI type 0,' in output
assert 'Vendor: U-Boot' in output
assert 'DMI type 1,' in output
diff --git a/test/py/tests/test_source.py b/test/py/tests/test_source.py
index bbc311d..970d8c7 100644
--- a/test/py/tests/test_source.py
+++ b/test/py/tests/test_source.py
@@ -3,35 +3,34 @@
import os
import pytest
-import u_boot_utils as util
+import utils
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_echo')
@pytest.mark.buildconfigspec('cmd_source')
@pytest.mark.buildconfigspec('fit')
-def test_source(u_boot_console):
+def test_source(ubman):
# Compile our test script image
- cons = u_boot_console
- mkimage = os.path.join(cons.config.build_dir, 'tools/mkimage')
- its = os.path.join(cons.config.source_dir, 'test/py/tests/source.its')
- fit = os.path.join(cons.config.build_dir, 'source.itb')
- util.run_and_log(cons, (mkimage, '-f', its, fit))
- cons.run_command(f'host load hostfs - $loadaddr {fit}')
+ mkimage = os.path.join(ubman.config.build_dir, 'tools/mkimage')
+ its = os.path.join(ubman.config.source_dir, 'test/py/tests/source.its')
+ fit = os.path.join(ubman.config.build_dir, 'source.itb')
+ utils.run_and_log(ubman, (mkimage, '-f', its, fit))
+ ubman.run_command(f'host load hostfs - $loadaddr {fit}')
- assert '2' in cons.run_command('source')
- assert '1' in cons.run_command('source :')
- assert '1' in cons.run_command('source :script-1')
- assert '2' in cons.run_command('source :script-2')
- assert 'Fail' in cons.run_command('source :not-a-script || echo Fail')
- assert '2' in cons.run_command('source \\#')
- assert '1' in cons.run_command('source \\#conf-1')
- assert '2' in cons.run_command('source \\#conf-2')
+ assert '2' in ubman.run_command('source')
+ assert '1' in ubman.run_command('source :')
+ assert '1' in ubman.run_command('source :script-1')
+ assert '2' in ubman.run_command('source :script-2')
+ assert 'Fail' in ubman.run_command('source :not-a-script || echo Fail')
+ assert '2' in ubman.run_command('source \\#')
+ assert '1' in ubman.run_command('source \\#conf-1')
+ assert '2' in ubman.run_command('source \\#conf-2')
- cons.run_command('fdt addr $loadaddr')
- cons.run_command('fdt rm /configurations default')
- assert '1' in cons.run_command('source')
- assert 'Fail' in cons.run_command('source \\# || echo Fail')
+ ubman.run_command('fdt addr $loadaddr')
+ ubman.run_command('fdt rm /configurations default')
+ assert '1' in ubman.run_command('source')
+ assert 'Fail' in ubman.run_command('source \\# || echo Fail')
- cons.run_command('fdt rm /images default')
- assert 'Fail' in cons.run_command('source || echo Fail')
- assert 'Fail' in cons.run_command('source \\# || echo Fail')
+ ubman.run_command('fdt rm /images default')
+ assert 'Fail' in ubman.run_command('source || echo Fail')
+ assert 'Fail' in ubman.run_command('source \\# || echo Fail')
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index d57db91..dd76752 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -51,7 +51,7 @@
import random
import re
import pytest
-import u_boot_utils
+import utils
SPI_DATA = {}
EXPECTED_ERASE = 'Erased: OK'
@@ -71,9 +71,9 @@
'Written: ERROR',
]
-def get_params_spi(u_boot_console):
+def get_params_spi(ubman):
''' Get SPI device test parameters from boardenv file '''
- f = u_boot_console.config.env.get('env__spi_device_test', None)
+ f = ubman.config.env.get('env__spi_device_test', None)
if not f:
pytest.skip('No SPI test device configured')
@@ -88,9 +88,9 @@
return bus, cs, mode, part_name, timeout
-def spi_find_freq_range(u_boot_console):
+def spi_find_freq_range(ubman):
'''Find out minimum and maximum frequnecies that SPI device can operate'''
- f = u_boot_console.config.env.get('env__spi_device_test', None)
+ f = ubman.config.env.get('env__spi_device_test', None)
if not f:
pytest.skip('No SPI test device configured')
@@ -107,11 +107,11 @@
return min_f, max_f, iterations
-def spi_pre_commands(u_boot_console, freq):
+def spi_pre_commands(ubman, freq):
''' Find out SPI family flash memory parameters '''
- bus, cs, mode, part_name, timeout = get_params_spi(u_boot_console)
+ bus, cs, mode, part_name, timeout = get_params_spi(ubman)
- output = u_boot_console.run_command(f'sf probe {bus}:{cs} {freq} {mode}')
+ output = ubman.run_command(f'sf probe {bus}:{cs} {freq} {mode}')
if not 'SF: Detected' in output:
pytest.fail('No SPI device available')
@@ -178,27 +178,27 @@
''' Get the SPI timeout from spi data '''
return SPI_DATA['timeout']
-def spi_erase_block(u_boot_console, erase_size, total_size):
+def spi_erase_block(ubman, erase_size, total_size):
''' Erase SPI flash memory block wise '''
for start in range(0, total_size, erase_size):
- output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(erase_size)}')
+ output = ubman.run_command(f'sf erase {hex(start)} {hex(erase_size)}')
assert EXPECTED_ERASE in output
@pytest.mark.buildconfigspec('cmd_sf')
-def test_spi_erase_block(u_boot_console):
+def test_spi_erase_block(ubman):
''' Test case to check SPI erase functionality by erasing memory regions
block-wise '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ min_f, max_f, loop = spi_find_freq_range(ubman)
i = 0
while i < loop:
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
- spi_erase_block(u_boot_console, get_erase_size(), get_total_size())
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
+ spi_erase_block(ubman, get_erase_size(), get_total_size())
i = i + 1
-def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout):
+def spi_write_twice(ubman, page_size, erase_size, total_size, timeout):
''' Random write till page size, random till size and full size '''
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
old_size = 0
for size in (
@@ -210,7 +210,7 @@
offset = offset & ~3
size = size & ~3
size = size - old_size
- output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
+ output = ubman.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
m = re.search('==> (.+?)$', output)
if not m:
pytest.fail('CRC32 failed')
@@ -228,23 +228,23 @@
eraseoffset *= erase_size
timeout = 100000000
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf erase {hex(eraseoffset)} {hex(erasesize)}'
)
assert EXPECTED_ERASE in output
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf write {hex(addr + total_size)} {hex(old_size)} {hex(size)}'
)
assert EXPECTED_WRITE in output
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf read {hex(addr + total_size + offset)} {hex(old_size)} {hex(size)}'
)
assert EXPECTED_READ in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
f'crc32 {hex(addr + total_size + offset)} {hex(size)}'
)
assert expected_crc32 in output
@@ -253,14 +253,14 @@
@pytest.mark.buildconfigspec('cmd_bdi')
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_write_twice(u_boot_console):
+def test_spi_write_twice(ubman):
''' Test to write data with random size twice for SPI '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ min_f, max_f, loop = spi_find_freq_range(ubman)
i = 0
while i < loop:
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
spi_write_twice(
- u_boot_console,
+ ubman,
get_page_size(),
get_erase_size(),
get_total_size(),
@@ -268,12 +268,12 @@
)
i = i + 1
-def spi_write_continues(u_boot_console, page_size, erase_size, total_size, timeout):
+def spi_write_continues(ubman, page_size, erase_size, total_size, timeout):
''' Write with random size of data to continue SPI write case '''
- spi_erase_block(u_boot_console, erase_size, total_size)
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ spi_erase_block(ubman, erase_size, total_size)
+ addr = utils.find_ram_base(ubman)
- output = u_boot_console.run_command(f'crc32 {hex(addr + 0x10000)} {hex(total_size)}')
+ output = ubman.run_command(f'crc32 {hex(addr + 0x10000)} {hex(total_size)}')
m = re.search('==> (.+?)$', output)
if not m:
pytest.fail('CRC32 failed')
@@ -287,20 +287,20 @@
):
size = size & ~3
size = size - old_size
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf write {hex(addr + 0x10000 + old_size)} {hex(old_size)} {hex(size)}'
)
assert EXPECTED_WRITE in output
old_size += size
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf read {hex(addr + 0x10000 + total_size)} 0 {hex(total_size)}'
)
assert EXPECTED_READ in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
f'crc32 {hex(addr + 0x10000 + total_size)} {hex(total_size)}'
)
assert expected_crc32 in output
@@ -308,14 +308,14 @@
@pytest.mark.buildconfigspec('cmd_bdi')
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_write_continues(u_boot_console):
+def test_spi_write_continues(ubman):
''' Test to write more random size data for SPI '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ min_f, max_f, loop = spi_find_freq_range(ubman)
i = 0
while i < loop:
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
spi_write_twice(
- u_boot_console,
+ ubman,
get_page_size(),
get_erase_size(),
get_total_size(),
@@ -323,28 +323,28 @@
)
i = i + 1
-def spi_read_twice(u_boot_console, page_size, total_size, timeout):
+def spi_read_twice(ubman, page_size, total_size, timeout):
''' Read the whole SPI flash twice, random_size till full flash size,
random till page size '''
for size in random.randint(4, page_size), random.randint(4, total_size), total_size:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
size = size & ~3
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf read {hex(addr + total_size)} 0 {hex(size)}'
)
assert EXPECTED_READ in output
- output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
+ output = ubman.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
m = re.search('==> (.+?)$', output)
if not m:
pytest.fail('CRC32 failed')
expected_crc32 = m.group(1)
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf read {hex(addr + total_size + 10)} 0 {hex(size)}'
)
assert EXPECTED_READ in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
f'crc32 {hex(addr + total_size + 10)} {hex(size)}'
)
assert expected_crc32 in output
@@ -352,49 +352,49 @@
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_bdi')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_read_twice(u_boot_console):
+def test_spi_read_twice(ubman):
''' Test to read random data twice from SPI '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ min_f, max_f, loop = spi_find_freq_range(ubman)
i = 0
while i < loop:
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
- spi_read_twice(u_boot_console, get_page_size(), get_total_size(), get_timeout())
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
+ spi_read_twice(ubman, get_page_size(), get_total_size(), get_timeout())
i = i + 1
-def spi_erase_all(u_boot_console, total_size, timeout):
+def spi_erase_all(ubman, total_size, timeout):
''' Erase the full chip SPI '''
start = 0
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(f'sf erase {start} {hex(total_size)}')
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(f'sf erase {start} {hex(total_size)}')
assert EXPECTED_ERASE in output
@pytest.mark.buildconfigspec('cmd_sf')
-def test_spi_erase_all(u_boot_console):
+def test_spi_erase_all(ubman):
''' Test to check full chip erase for SPI '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ min_f, max_f, loop = spi_find_freq_range(ubman)
i = 0
while i < loop:
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
- spi_erase_all(u_boot_console, get_total_size(), get_timeout())
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
+ spi_erase_all(ubman, get_total_size(), get_timeout())
i = i + 1
def flash_ops(
- u_boot_console, ops, start, size, offset=0, exp_ret=0, exp_str='', not_exp_str=''
+ ubman, ops, start, size, offset=0, exp_ret=0, exp_str='', not_exp_str=''
):
''' Flash operations: erase, write and read '''
- f = u_boot_console.config.env.get('env__spi_device_test', None)
+ f = ubman.config.env.get('env__spi_device_test', None)
if not f:
timeout = 1000000
timeout = f.get('timeout', 1000000)
if ops == 'erase':
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(size)}')
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(f'sf erase {hex(start)} {hex(size)}')
else:
- with u_boot_console.temporary_timeout(timeout):
- output = u_boot_console.run_command(
+ with ubman.temporary_timeout(timeout):
+ output = ubman.run_command(
f'sf {ops} {hex(offset)} {hex(start)} {hex(size)}'
)
@@ -403,15 +403,15 @@
if not_exp_str:
assert not_exp_str not in output
- ret_code = u_boot_console.run_command('echo $?')
+ ret_code = ubman.run_command('echo $?')
if exp_ret >= 0:
assert ret_code.endswith(str(exp_ret))
return output, ret_code
-def spi_unlock_exit(u_boot_console, addr, size):
+def spi_unlock_exit(ubman, addr, size):
''' Unlock the flash before making it fail '''
- u_boot_console.run_command(f'sf protect unlock {hex(addr)} {hex(size)}')
+ ubman.run_command(f'sf protect unlock {hex(addr)} {hex(size)}')
assert False, 'FAIL: Flash lock is unable to protect the data!'
def find_prot_region(lock_addr, lock_size):
@@ -440,49 +440,49 @@
return prot_start, prot_size, unprot_start, unprot_size
-def protect_ops(u_boot_console, lock_addr, lock_size, ops="unlock"):
+def protect_ops(ubman, lock_addr, lock_size, ops="unlock"):
''' Run the command to lock or Unlock the flash '''
- u_boot_console.run_command(f'sf protect {ops} {hex(lock_addr)} {hex(lock_size)}')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command(f'sf protect {ops} {hex(lock_addr)} {hex(lock_size)}')
+ output = ubman.run_command('echo $?')
if ops == "lock" and not output.endswith('0'):
- u_boot_console.run_command(f'sf protect unlock {hex(lock_addr)} {hex(lock_size)}')
+ ubman.run_command(f'sf protect unlock {hex(lock_addr)} {hex(lock_size)}')
assert False, "sf protect lock command exits with non-zero return code"
assert output.endswith('0')
-def erase_write_ops(u_boot_console, start, size):
+def erase_write_ops(ubman, start, size):
''' Basic erase and write operation for flash '''
- addr = u_boot_utils.find_ram_base(u_boot_console)
- flash_ops(u_boot_console, 'erase', start, size, 0, 0, EXPECTED_ERASE)
- flash_ops(u_boot_console, 'write', start, size, addr, 0, EXPECTED_WRITE)
+ addr = utils.find_ram_base(ubman)
+ flash_ops(ubman, 'erase', start, size, 0, 0, EXPECTED_ERASE)
+ flash_ops(ubman, 'write', start, size, addr, 0, EXPECTED_WRITE)
-def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
+def spi_lock_unlock(ubman, lock_addr, lock_size):
''' Lock unlock operations for SPI family flash '''
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
erase_size = get_erase_size()
# Find the protected/un-protected region
prot_start, prot_size, unprot_start, unprot_size = find_prot_region(lock_addr, lock_size)
# Check erase/write operation before locking
- erase_write_ops(u_boot_console, prot_start, prot_size)
+ erase_write_ops(ubman, prot_start, prot_size)
# Locking the flash
- protect_ops(u_boot_console, lock_addr, lock_size, 'lock')
+ protect_ops(ubman, lock_addr, lock_size, 'lock')
# Check erase/write operation after locking
- output, ret_code = flash_ops(u_boot_console, 'erase', prot_start, prot_size, 0, -1)
+ output, ret_code = flash_ops(ubman, 'erase', prot_start, prot_size, 0, -1)
if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith(
'0'
):
- spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+ spi_unlock_exit(ubman, lock_addr, lock_size)
output, ret_code = flash_ops(
- u_boot_console, 'write', prot_start, prot_size, addr, -1
+ ubman, 'write', prot_start, prot_size, addr, -1
)
if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith(
'0'
):
- spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+ spi_unlock_exit(ubman, lock_addr, lock_size)
# Check locked sectors
sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size)
@@ -495,20 +495,20 @@
sect_write_size = random.randint(1, sect_lock_size)
output, ret_code = flash_ops(
- u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, -1
+ ubman, 'erase', sect_lock_start, sect_lock_size, 0, -1
)
if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith(
'0'
):
- spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+ spi_unlock_exit(ubman, lock_addr, lock_size)
output, ret_code = flash_ops(
- u_boot_console, 'write', sect_lock_start, sect_write_size, addr, -1
+ ubman, 'write', sect_lock_start, sect_write_size, addr, -1
)
if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith(
'0'
):
- spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+ spi_unlock_exit(ubman, lock_addr, lock_size)
# Check unlocked sectors
if unprot_size != 0:
@@ -524,22 +524,22 @@
sect_write_size = random.randint(1, sect_unlock_size)
output, ret_code = flash_ops(
- u_boot_console, 'erase', sect_unlock_start, sect_unlock_size, 0, -1
+ ubman, 'erase', sect_unlock_start, sect_unlock_size, 0, -1
)
if EXPECTED_ERASE not in output or ret_code.endswith('1'):
- spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+ spi_unlock_exit(ubman, lock_addr, lock_size)
output, ret_code = flash_ops(
- u_boot_console, 'write', sect_unlock_start, sect_write_size, addr, -1
+ ubman, 'write', sect_unlock_start, sect_write_size, addr, -1
)
if EXPECTED_WRITE not in output or ret_code.endswith('1'):
- spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+ spi_unlock_exit(ubman, lock_addr, lock_size)
# Unlocking the flash
- protect_ops(u_boot_console, lock_addr, lock_size, 'unlock')
+ protect_ops(ubman, lock_addr, lock_size, 'unlock')
# Check erase/write operation after un-locking
- erase_write_ops(u_boot_console, prot_start, prot_size)
+ erase_write_ops(ubman, prot_start, prot_size)
# Check previous locked sectors
sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size)
@@ -552,10 +552,10 @@
sect_write_size = random.randint(1, sect_lock_size)
flash_ops(
- u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, 0, EXPECTED_ERASE
+ ubman, 'erase', sect_lock_start, sect_lock_size, 0, 0, EXPECTED_ERASE
)
flash_ops(
- u_boot_console,
+ ubman,
'write',
sect_lock_start,
sect_write_size,
@@ -567,16 +567,16 @@
@pytest.mark.buildconfigspec('cmd_bdi')
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_lock_unlock(u_boot_console):
+def test_spi_lock_unlock(ubman):
''' Test to check the lock-unlock functionality for SPI family flash '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
- flashes = u_boot_console.config.env.get('env__spi_lock_unlock', False)
+ min_f, max_f, loop = spi_find_freq_range(ubman)
+ flashes = ubman.config.env.get('env__spi_lock_unlock', False)
if not flashes:
pytest.skip('No SPI test device configured for lock/unlock')
i = 0
while i < loop:
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
total_size = get_total_size()
flash_part = get_flash_part()
@@ -588,31 +588,31 @@
# For lower half of memory
lock_addr = random.randint(0, (total_size // 2) - 1)
lock_size = random.randint(1, ((total_size // 2) - lock_addr))
- spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+ spi_lock_unlock(ubman, lock_addr, lock_size)
# For upper half of memory
lock_addr = random.randint((total_size // 2), total_size - 1)
lock_size = random.randint(1, (total_size - lock_addr))
- spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+ spi_lock_unlock(ubman, lock_addr, lock_size)
# For entire flash
lock_addr = random.randint(0, total_size - 1)
lock_size = random.randint(1, (total_size - lock_addr))
- spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+ spi_lock_unlock(ubman, lock_addr, lock_size)
i = i + 1
@pytest.mark.buildconfigspec('cmd_bdi')
@pytest.mark.buildconfigspec('cmd_sf')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_negative(u_boot_console):
+def test_spi_negative(ubman):
''' Negative tests for SPI '''
- min_f, max_f, loop = spi_find_freq_range(u_boot_console)
- spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ min_f, max_f, loop = spi_find_freq_range(ubman)
+ spi_pre_commands(ubman, random.randint(min_f, max_f))
total_size = get_total_size()
erase_size = get_erase_size()
page_size = get_page_size()
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
i = 0
while i < loop:
# Erase negative test
@@ -625,28 +625,28 @@
error_msg = 'Erased: ERROR'
flash_ops(
- u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
)
# If eraseoffset exceeds beyond flash size
eoffset = random.randint(total_size, (total_size + int(0x1000000)))
error_msg = 'Offset exceeds device limit'
flash_ops(
- u_boot_console, 'erase', eoffset, esize, 0, 1, error_msg, EXPECTED_ERASE
+ ubman, 'erase', eoffset, esize, 0, 1, error_msg, EXPECTED_ERASE
)
# If erasesize exceeds beyond flash size
esize = random.randint((total_size - start), (total_size + int(0x1000000)))
error_msg = 'ERROR: attempting erase past flash size'
flash_ops(
- u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
)
# If erase size is 0
esize = 0
error_msg = None
flash_ops(
- u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
)
# If erasesize is less than flash's page size
@@ -654,7 +654,7 @@
start = random.randint(0, (total_size - page_size))
error_msg = 'Erased: ERROR'
flash_ops(
- u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
)
# Write/Read negative test
@@ -663,10 +663,10 @@
size = random.randint((total_size - offset), (total_size + int(0x1000000)))
error_msg = 'Size exceeds partition or device limit'
flash_ops(
- u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+ ubman, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
)
flash_ops(
- u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+ ubman, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
)
# if Write/Read offset exceeds beyond flash size
@@ -674,10 +674,10 @@
size = random.randint(0, total_size)
error_msg = 'Offset exceeds device limit'
flash_ops(
- u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+ ubman, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
)
flash_ops(
- u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+ ubman, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
)
# if Write/Read size is 0
@@ -685,14 +685,14 @@
size = 0
error_msg = None
flash_ops(
- u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+ ubman, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
)
flash_ops(
- u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+ ubman, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
)
# Read to relocation address
- output = u_boot_console.run_command('bdinfo')
+ output = ubman.run_command('bdinfo')
m = re.search(r'relocaddr\s*= (.+)', output)
res_area = int(m.group(1), 16)
@@ -700,7 +700,7 @@
size = 0x2000
error_msg = 'ERROR: trying to overwrite reserved memory'
flash_ops(
- u_boot_console, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
+ ubman, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
)
i = i + 1
diff --git a/test/py/tests/test_spl.py b/test/py/tests/test_spl.py
index 474f430..4840739 100644
--- a/test/py/tests/test_spl.py
+++ b/test/py/tests/test_spl.py
@@ -6,16 +6,16 @@
import pytest
@pytest.mark.buildconfigspec('spl_unit_test')
-def test_ut_spl_init(u_boot_console):
+def test_ut_spl_init(ubman):
"""Initialize data for ut spl tests."""
- fn = u_boot_console.config.source_dir + '/spi.bin'
+ fn = ubman.config.source_dir + '/spi.bin'
if not os.path.exists(fn):
data = b'\x00' * (2 * 1024 * 1024)
with open(fn, 'wb') as fh:
fh.write(data)
-def test_spl(u_boot_console, ut_spl_subtest):
+def test_spl(ubman, ut_spl_subtest):
"""Execute a "ut" subtest.
The subtests are collected in function generate_ut_subtest() from linker
@@ -29,16 +29,15 @@
implemented in C function foo_test_bar().
Args:
- u_boot_console (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
ut_subtest (str): SPL test to be executed (e.g. 'dm platdata_phandle')
"""
try:
- cons = u_boot_console
- cons.restart_uboot_with_flags(['-u', '-k', ut_spl_subtest.split()[1]])
- output = cons.get_spawn_output().replace('\r', '')
+ ubman.restart_uboot_with_flags(['-u', '-k', ut_spl_subtest.split()[1]])
+ output = ubman.get_spawn_output().replace('\r', '')
assert 'failures: 0' in output
finally:
# Restart afterward in case a non-SPL test is run next. This should not
# happen since SPL tests are run in their own invocation of test.py, but
# the cost of doing this is not too great at present.
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_stackprotector.py b/test/py/tests/test_stackprotector.py
index b87392c..a7e20d6 100644
--- a/test/py/tests/test_stackprotector.py
+++ b/test/py/tests/test_stackprotector.py
@@ -6,10 +6,10 @@
@pytest.mark.buildconfigspec('cmd_stackprotector_test')
@pytest.mark.notbuildconfigspec('asan')
-def test_stackprotector(u_boot_console):
+def test_stackprotector(ubman):
"""Test that the stackprotector function works."""
- u_boot_console.run_command('stackprot_test',wait_for_prompt=False)
+ ubman.run_command('stackprot_test',wait_for_prompt=False)
expected_response = 'Stack smashing detected'
- u_boot_console.wait_for(expected_response)
- u_boot_console.restart_uboot()
+ ubman.wait_for(expected_response)
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_suite.py b/test/py/tests/test_suite.py
index 9ddc883..7fe9a90 100644
--- a/test/py/tests/test_suite.py
+++ b/test/py/tests/test_suite.py
@@ -18,11 +18,11 @@
DEBUG_ME = False
-def collect_info(cons, output):
+def collect_info(ubman, output):
"""Process the output from 'ut all'
Args:
- cons: U-Boot console object
+ ubman: U-Boot console object
output: Output from running 'ut all'
Returns:
@@ -45,15 +45,15 @@
for line in output.splitlines():
line = line.rstrip()
if DEBUG_ME:
- cons.log.info(f'line: {line}')
+ ubman.log.info(f'line: {line}')
m = re.search('----Running ([^ ]*) tests----', line)
if m:
if DEBUG_ME and cur_suite and cur_suite != 'info':
- cons.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
+ ubman.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
cur_suite = m.group(1)
if DEBUG_ME:
- cons.log.info(f'cur_suite: {cur_suite}')
+ ubman.log.info(f'cur_suite: {cur_suite}')
suites.add(cur_suite)
test_count = 0
@@ -65,7 +65,7 @@
test_name = m.group(1)
msg = m.group(3)
if DEBUG_ME:
- cons.log.info(f"test_name {test_name} msg '{msg}'")
+ ubman.log.info(f"test_name {test_name} msg '{msg}'")
full_name = f'{cur_suite}.{test_name}'
if msg == ' (flat tree)' and full_name not in tests:
tests.add(full_name)
@@ -74,10 +74,10 @@
tests.add(full_name)
test_count += 1
if DEBUG_ME:
- cons.log.info(f'test_count {test_count}')
+ ubman.log.info(f'test_count {test_count}')
if DEBUG_ME:
- cons.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
- cons.log.info(f"Tests: {' '.join(sorted(list(tests)))}")
+ ubman.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
+ ubman.log.info(f"Tests: {' '.join(sorted(list(tests)))}")
# Figure out what is missing, or extra
missing = set()
@@ -91,11 +91,11 @@
return suites, tests, exp_test_count, missing, extra
-def process_ut_info(cons, output):
+def process_ut_info(ubman, output):
"""Process the output of the 'ut info' command
Args:
- cons: U-Boot console object
+ ubman: U-Boot console object
output: Output from running 'ut all'
Returns:
@@ -113,7 +113,7 @@
for line in output.splitlines():
line = line.rstrip()
if DEBUG_ME:
- cons.log.info(f'line: {line}')
+ ubman.log.info(f'line: {line}')
m = re.match(r'Test suites: (.*)', line)
if m:
suite_count = int(m.group(1))
@@ -130,7 +130,7 @@
@pytest.mark.notbuildconfigspec('sandbox_spl')
@pytest.mark.notbuildconfigspec('sandbox64')
# This test is disabled since it fails; remove the leading 'x' to try it
-def xtest_suite(u_boot_console, u_boot_config):
+def xtest_suite(ubman, u_boot_config):
"""Perform various checks on the unit tests, including:
- The number of suites matches that reported by the 'ut info'
@@ -142,45 +142,44 @@
- The expected set of suites is run (the list is hard-coded in this test)
"""
- cons = u_boot_console
buildconfig = u_boot_config.buildconfig
- with cons.log.section('Run all unit tests'):
+ with ubman.log.section('Run all unit tests'):
# ut hush hush_test_simple_dollar prints "Unknown command" on purpose.
- with u_boot_console.disable_check('unknown_command'):
- output = cons.run_command('ut all')
+ with ubman.disable_check('unknown_command'):
+ output = ubman.run_command('ut all')
# Process the output from the run
- with cons.log.section('Check output'):
- suites, all_tests, exp_test_count, missing, extra = collect_info(cons,
+ with ubman.log.section('Check output'):
+ suites, all_tests, exp_test_count, missing, extra = collect_info(ubman,
output)
- cons.log.info(f'missing {missing}')
- cons.log.info(f'extra {extra}')
+ ubman.log.info(f'missing {missing}')
+ ubman.log.info(f'extra {extra}')
# Make sure we got a test count for each suite
assert not (suites - exp_test_count.keys())
# Deal with missing suites
- with cons.log.section('Check missing suites'):
+ with ubman.log.section('Check missing suites'):
if 'config_cmd_seama' not in buildconfig:
- cons.log.info("CMD_SEAMA not enabled: Ignoring suite 'seama'")
+ ubman.log.info("CMD_SEAMA not enabled: Ignoring suite 'seama'")
missing.discard('seama')
# Run 'ut info' and compare with the log results
- with cons.log.section('Check suite test-counts'):
- output = cons.run_command('ut -s info')
+ with ubman.log.section('Check suite test-counts'):
+ output = ubman.run_command('ut -s info')
- suite_count, total_test_count, test_count = process_ut_info(cons,
+ suite_count, total_test_count, test_count = process_ut_info(ubman,
output)
if missing or extra:
- cons.log.info(f"suites: {' '.join(sorted(list(suites)))}")
- cons.log.error(f'missing: {sorted(list(missing))}')
- cons.log.error(f'extra: {sorted(list(extra))}')
+ ubman.log.info(f"suites: {' '.join(sorted(list(suites)))}")
+ ubman.log.error(f'missing: {sorted(list(missing))}')
+ ubman.log.error(f'extra: {sorted(list(extra))}')
assert not missing, f'Missing suites {missing}'
assert not extra, f'Extra suites {extra}'
- cons.log.info(str(exp_test_count))
+ ubman.log.info(str(exp_test_count))
for suite in EXPECTED_SUITES:
assert test_count[suite] in ['?', str(exp_test_count[suite])], \
f'suite {suite} expected {exp_test_count[suite]}'
@@ -189,18 +188,18 @@
assert total_test_count == len(all_tests)
# Run three suites
- with cons.log.section('Check multiple suites'):
- output = cons.run_command('ut bloblist,setexpr,mem')
+ with ubman.log.section('Check multiple suites'):
+ output = ubman.run_command('ut bloblist,setexpr,mem')
assert 'Suites run: 3' in output
# Run a particular test
- with cons.log.section('Check single test'):
- output = cons.run_command('ut bloblist reloc')
+ with ubman.log.section('Check single test'):
+ output = ubman.run_command('ut bloblist reloc')
assert 'Test: reloc: bloblist.c' in output
# Run tests multiple times
- with cons.log.section('Check multiple runs'):
- output = cons.run_command('ut -r2 bloblist')
+ with ubman.log.section('Check multiple runs'):
+ output = ubman.run_command('ut -r2 bloblist')
lines = output.splitlines()
run = len([line for line in lines if 'Test:' in line])
count = re.search(r'Tests run: (\d*)', lines[-1]).group(1)
diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py
index 75f5d31..064651c 100644
--- a/test/py/tests/test_tpm2.py
+++ b/test/py/tests/test_tpm2.py
@@ -4,7 +4,7 @@
import os.path
import pytest
-import u_boot_utils
+import utils
import re
import time
@@ -31,109 +31,109 @@
updates = 0
-def force_init(u_boot_console, force=False):
+def force_init(ubman, force=False):
"""When a test fails, U-Boot is reset. Because TPM stack must be initialized
after each reboot, we must ensure these lines are always executed before
trying any command or they will fail with no reason. Executing 'tpm init'
twice will spawn an error used to detect that the TPM was not reset and no
initialization code should be run.
"""
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- output = u_boot_console.run_command('tpm2 autostart')
+ output = ubman.run_command('tpm2 autostart')
if force or not 'Error' in output:
- u_boot_console.run_command('echo --- start of init ---')
- u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('echo --- start of init ---')
+ ubman.run_command('tpm2 clear TPM2_RH_LOCKOUT')
+ output = ubman.run_command('echo $?')
if not output.endswith('0'):
- u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
- u_boot_console.run_command('echo --- end of init ---')
+ ubman.run_command('tpm2 clear TPM2_RH_PLATFORM')
+ ubman.run_command('echo --- end of init ---')
-def is_sandbox(cons):
+def is_sandbox(ubman):
# Array slice removes leading/trailing quotes.
- sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
+ sys_arch = ubman.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
return sys_arch == 'sandbox'
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_init(u_boot_console):
+def test_tpm2_init(ubman):
"""Init the software stack to use TPMv2 commands."""
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- u_boot_console.run_command('tpm2 autostart')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 autostart')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_startup(u_boot_console):
+def test_tpm2_startup(ubman):
"""Execute a TPM2_Startup command.
Initiate the TPM internal state machine.
"""
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 startup TPM2_SU_CLEAR')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
-def tpm2_sandbox_init(u_boot_console):
+def tpm2_sandbox_init(ubman):
"""Put sandbox back into a known state so we can run a test
This allows all tests to run in parallel, since no test depends on another.
"""
- u_boot_console.restart_uboot()
- u_boot_console.run_command('tpm2 autostart')
- output = u_boot_console.run_command('echo $?')
+ ubman.restart_uboot()
+ ubman.run_command('tpm2 autostart')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_sandbox_self_test_full(u_boot_console):
+def test_tpm2_sandbox_self_test_full(ubman):
"""Execute a TPM2_SelfTest (full) command.
Ask the TPM to perform all self tests to also enable full capabilities.
"""
- if is_sandbox(u_boot_console):
- u_boot_console.restart_uboot()
- u_boot_console.run_command('tpm2 autostart')
- output = u_boot_console.run_command('echo $?')
+ if is_sandbox(ubman):
+ ubman.restart_uboot()
+ ubman.run_command('tpm2 autostart')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 startup TPM2_SU_CLEAR')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- u_boot_console.run_command('tpm2 self_test full')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 self_test full')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_continue_self_test(u_boot_console):
+def test_tpm2_continue_self_test(ubman):
"""Execute a TPM2_SelfTest (continued) command.
Ask the TPM to finish its self tests (alternative to the full test) in order
to enter a fully operational state.
"""
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
- u_boot_console.run_command('tpm2 self_test continue')
- output = u_boot_console.run_command('echo $?')
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
+ ubman.run_command('tpm2 self_test continue')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_clear(u_boot_console):
+def test_tpm2_clear(ubman):
"""Execute a TPM2_Clear command.
Ask the TPM to reset entirely its internal state (including internal
@@ -144,22 +144,22 @@
not have a password set, otherwise this test will fail. ENDORSEMENT and
PLATFORM hierarchies are also available.
"""
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
- skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+ skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
if skip_test:
pytest.skip('skip TPM device test')
- u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 clear TPM2_RH_LOCKOUT')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 clear TPM2_RH_PLATFORM')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_change_auth(u_boot_console):
+def test_tpm2_change_auth(ubman):
"""Execute a TPM2_HierarchyChangeAuth command.
Ask the TPM to change the owner, ie. set a new password: 'unicorn'
@@ -167,22 +167,22 @@
Use the LOCKOUT hierarchy for this. ENDORSEMENT and PLATFORM hierarchies are
also available.
"""
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
- force_init(u_boot_console)
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
+ force_init(ubman)
- u_boot_console.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT unicorn')
- output = u_boot_console.run_command('echo $?')
- u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
+ ubman.run_command('tpm2 clear TPM2_RH_LOCKOUT unicorn')
+ output = ubman.run_command('echo $?')
+ ubman.run_command('tpm2 clear TPM2_RH_PLATFORM')
assert output.endswith('0')
@pytest.mark.buildconfigspec('sandbox')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_get_capability(u_boot_console):
+def test_tpm2_get_capability(ubman):
"""Execute a TPM_GetCapability command.
Display one capability. In our test case, let's display the default DAM
@@ -193,19 +193,19 @@
There is no expected default values because it would depend on the chip
used. We can still save them in order to check they have changed later.
"""
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
- force_init(u_boot_console)
- ram = u_boot_utils.find_ram_base(u_boot_console)
+ force_init(ubman)
+ ram = utils.find_ram_base(ubman)
- read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
- output = u_boot_console.run_command('echo $?')
+ read_cap = ubman.run_command('tpm2 get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
assert 'Property 0x0000020e: 0x00000000' in read_cap
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_dam_parameters(u_boot_console):
+def test_tpm2_dam_parameters(ubman):
"""Execute a TPM2_DictionaryAttackParameters command.
Change Dictionary Attack Mitigation (DAM) parameters. Ask the TPM to change:
@@ -217,38 +217,38 @@
the authentication, otherwise the lockout will be engaged after the first
failed authentication attempt.
"""
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
- force_init(u_boot_console)
- ram = u_boot_utils.find_ram_base(u_boot_console)
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
+ force_init(ubman)
+ ram = utils.find_ram_base(ubman)
# Set the DAM parameters to known values
- u_boot_console.run_command('tpm2 dam_parameters 3 10 0')
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 dam_parameters 3 10 0')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
# Check the values have been saved
- read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20f 0x%x 3' % ram)
- output = u_boot_console.run_command('echo $?')
+ read_cap = ubman.run_command('tpm2 get_capability 0x6 0x20f 0x%x 3' % ram)
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
assert 'Property 0x0000020f: 0x00000003' in read_cap
assert 'Property 0x00000210: 0x0000000a' in read_cap
assert 'Property 0x00000211: 0x00000000' in read_cap
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_pcr_read(u_boot_console):
+def test_tpm2_pcr_read(ubman):
"""Execute a TPM2_PCR_Read command.
Perform a PCR read of the 10th PCR. Must be zero.
"""
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
- force_init(u_boot_console)
- ram = u_boot_utils.find_ram_base(u_boot_console)
+ force_init(ubman)
+ ram = utils.find_ram_base(ubman)
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % ram)
- output = u_boot_console.run_command('echo $?')
+ read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % ram)
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
# Save the number of PCR updates
@@ -261,7 +261,7 @@
assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_pcr_extend(u_boot_console):
+def test_tpm2_pcr_extend(ubman):
"""Execute a TPM2_PCR_Extend command.
Perform a PCR extension with a known hash in memory (zeroed since the board
@@ -270,25 +270,25 @@
No authentication mechanism is used here, not protecting against packet
replay, yet.
"""
- if is_sandbox(u_boot_console):
- tpm2_sandbox_init(u_boot_console)
- force_init(u_boot_console)
- ram = u_boot_utils.find_ram_base(u_boot_console)
+ if is_sandbox(ubman):
+ tpm2_sandbox_init(ubman)
+ force_init(ubman)
+ ram = utils.find_ram_base(ubman)
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
- output = u_boot_console.run_command('echo $?')
+ read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
str = re.findall(r'\d+ known updates', read_pcr)[0]
updates = int(re.findall(r'\d+', str)[0])
- u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram)
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 pcr_extend 10 0x%x' % ram)
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
# Read the value back into a different place so we can still use 'ram' as
# our zero bytes
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
- output = u_boot_console.run_command('echo $?')
+ read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr
assert '43 00 3d 23 20 d9 f0 e8 ea 98 31 a9 27 59 fb 4b' in read_pcr
@@ -297,12 +297,12 @@
new_updates = int(re.findall(r'\d+', str)[0])
assert (updates + 1) == new_updates
- u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram)
- output = u_boot_console.run_command('echo $?')
+ ubman.run_command('tpm2 pcr_extend 10 0x%x' % ram)
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
- output = u_boot_console.run_command('echo $?')
+ read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
assert '7a 05 01 f5 95 7b df 9c b3 a8 ff 49 66 f0 22 65' in read_pcr
assert 'f9 68 65 8b 7a 9c 62 64 2c ba 11 65 e8 66 42 f5' in read_pcr
@@ -312,7 +312,7 @@
assert (updates + 2) == new_updates
@pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_cleanup(u_boot_console):
+def test_tpm2_cleanup(ubman):
"""Ensure the TPM is cleared from password or test related configuration."""
- force_init(u_boot_console, True)
+ force_init(ubman, True)
diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py
index 44239da..6ac1b22 100644
--- a/test/py/tests/test_trace.py
+++ b/test/py/tests/test_trace.py
@@ -6,7 +6,7 @@
import pytest
import re
-import u_boot_utils as util
+import utils
# This is needed for Azure, since the default '..' directory is not writeable
TMPDIR = '/tmp/test_trace'
@@ -15,19 +15,19 @@
RE_LINE = re.compile(r'.*0\.\.\.\.\.? \s*([0-9.]*): func.*[|](\s*)(\S.*)?([{};])$')
-def collect_trace(cons):
+def collect_trace(ubman):
"""Build U-Boot and run it to collect a trace
Args:
- cons (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
Returns:
tuple:
str: Filename of the output trace file
int: Microseconds taken for initf_dm according to bootstage
"""
- cons.run_command('trace pause')
- out = cons.run_command('trace stats')
+ ubman.run_command('trace pause')
+ out = ubman.run_command('trace stats')
# The output is something like this:
# 251,003 function sites
@@ -48,10 +48,10 @@
assert int(vals['untracked function calls']) == 0
assert int(vals['maximum observed call depth']) > 30
assert (vals['call depth limit'] ==
- cons.config.buildconfig.get('config_trace_call_depth_limit'))
+ ubman.config.buildconfig.get('config_trace_call_depth_limit'))
assert int(vals['calls not traced due to depth']) > 100000
- out = cons.run_command('bootstage report')
+ out = ubman.run_command('bootstage report')
# Accumulated time:
# 19,104 dm_r
# 23,078 of_live
@@ -62,26 +62,26 @@
# Read out the trace data
addr = 0x02000000
size = 0x02000000
- out = cons.run_command(f'trace calls {addr:x} {size:x}')
+ out = ubman.run_command(f'trace calls {addr:x} {size:x}')
print(out)
fname = os.path.join(TMPDIR, 'trace')
- out = cons.run_command(
+ out = ubman.run_command(
'host save hostfs - %x %s ${profoffset}' % (addr, fname))
return fname, int(dm_f_time[0])
-def wipe_and_collect_trace(cons):
+def wipe_and_collect_trace(ubman):
"""Pause and wipe traces, return the number of calls (should be zero)
Args:
- cons (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
Returns:
int: the number of traced function calls reported by 'trace stats'
"""
- cons.run_command('trace pause')
- cons.run_command('trace wipe')
- out = cons.run_command('trace stats')
+ ubman.run_command('trace pause')
+ ubman.run_command('trace wipe')
+ out = ubman.run_command('trace stats')
# The output is something like this:
# 117,221 function sites
@@ -96,22 +96,22 @@
return int(vals['traced function calls'])
-def check_function(cons, fname, proftool, map_fname, trace_dat):
+def check_function(ubman, fname, proftool, map_fname, trace_dat):
"""Check that the 'function' output works
Args:
- cons (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
fname (str): Filename of trace file
proftool (str): Filename of proftool
map_fname (str): Filename of System.map
trace_dat (str): Filename of output file
"""
- out = util.run_and_log(
- cons, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
+ out = utils.run_and_log(
+ ubman, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
'dump-ftrace'])
# Check that trace-cmd can read it
- out = util.run_and_log(cons, ['trace-cmd', 'dump', trace_dat])
+ out = utils.run_and_log(ubman, ['trace-cmd', 'dump', trace_dat])
# Tracing meta data in file /tmp/test_trace/trace.dat:
# [Initial format]
@@ -140,7 +140,7 @@
# Check that the trace has something useful
cmd = f"trace-cmd report -l {trace_dat} |grep -E '(initf_|initr_)'"
- out = util.run_and_log(cons, ['sh', '-c', cmd])
+ out = utils.run_and_log(ubman, ['sh', '-c', cmd])
# Format:
# u-boot-1 0..... 60.805596: function: initf_malloc
@@ -167,11 +167,11 @@
assert max_delta < 5
-def check_funcgraph(cons, fname, proftool, map_fname, trace_dat):
+def check_funcgraph(ubman, fname, proftool, map_fname, trace_dat):
"""Check that the 'funcgraph' output works
Args:
- cons (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
fname (str): Filename of trace file
proftool (str): Filename of proftool
map_fname (str): Filename of System.map
@@ -182,13 +182,13 @@
"""
# Generate the funcgraph format
- out = util.run_and_log(
- cons, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
+ out = utils.run_and_log(
+ ubman, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
'dump-ftrace', '-f', 'funcgraph'])
# Check that the trace has what we expect
cmd = f'trace-cmd report -l {trace_dat} |head -n 70'
- out = util.run_and_log(cons, ['sh', '-c', cmd])
+ out = utils.run_and_log(ubman, ['sh', '-c', cmd])
# First look for this:
# u-boot-1 0..... 282.101360: funcgraph_entry: 0.004 us | initf_malloc();
@@ -230,7 +230,7 @@
# Now look for initf_dm() and dm_timer_init() so we can check the bootstage
# time
cmd = f"trace-cmd report -l {trace_dat} |grep -E '(initf_dm|dm_timer_init)'"
- out = util.run_and_log(cons, ['sh', '-c', cmd])
+ out = utils.run_and_log(ubman, ['sh', '-c', cmd])
start_timestamp = None
end_timestamp = None
@@ -249,14 +249,14 @@
return int((float(end_timestamp) - float(start_timestamp)) * 1000000)
-def check_flamegraph(cons, fname, proftool, map_fname, trace_fg):
+def check_flamegraph(ubman, fname, proftool, map_fname, trace_fg):
"""Check that the 'flamegraph' output works
This spot checks a few call counts and estimates the time taken by the
initf_dm() function
Args:
- cons (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
fname (str): Filename of trace file
proftool (str): Filename of proftool
map_fname (str): Filename of System.map
@@ -267,8 +267,8 @@
"""
# Generate the flamegraph format
- out = util.run_and_log(
- cons, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
+ out = utils.run_and_log(
+ ubman, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
'dump-flamegraph'])
# We expect dm_timer_init() to be called twice: once before relocation and
@@ -284,8 +284,8 @@
assert found == 2
# Generate the timing graph
- out = util.run_and_log(
- cons, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
+ utils.run_and_log(
+ ubman, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
'dump-flamegraph', '-f', 'timing'])
# Add up all the time spend in initf_dm() and its children
@@ -303,28 +303,27 @@
@pytest.mark.slow
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('trace')
-def test_trace(u_boot_console):
+def test_trace(ubman):
"""Test we can build sandbox with trace, collect and process a trace"""
- cons = u_boot_console
if not os.path.exists(TMPDIR):
os.mkdir(TMPDIR)
- proftool = os.path.join(cons.config.build_dir, 'tools', 'proftool')
- map_fname = os.path.join(cons.config.build_dir, 'System.map')
+ proftool = os.path.join(ubman.config.build_dir, 'tools', 'proftool')
+ map_fname = os.path.join(ubman.config.build_dir, 'System.map')
trace_dat = os.path.join(TMPDIR, 'trace.dat')
trace_fg = os.path.join(TMPDIR, 'trace.fg')
- fname, dm_f_time = collect_trace(cons)
+ fname, dm_f_time = collect_trace(ubman)
- check_function(cons, fname, proftool, map_fname, trace_dat)
- trace_time = check_funcgraph(cons, fname, proftool, map_fname, trace_dat)
+ check_function(ubman, fname, proftool, map_fname, trace_dat)
+ trace_time = check_funcgraph(ubman, fname, proftool, map_fname, trace_dat)
# Check that bootstage and funcgraph agree to within 10 microseconds
diff = abs(trace_time - dm_f_time)
print(f'trace_time {trace_time}, dm_f_time {dm_f_time}')
assert diff / dm_f_time < 0.01
- fg_time = check_flamegraph(cons, fname, proftool, map_fname, trace_fg)
+ fg_time = check_flamegraph(ubman, fname, proftool, map_fname, trace_fg)
# Check that bootstage and flamegraph agree to within 30%
# This allows for CI being slow to run
@@ -332,5 +331,5 @@
assert diff / dm_f_time < 0.3
# Check that the trace buffer can be wiped
- numcalls = wipe_and_collect_trace(cons)
+ numcalls = wipe_and_collect_trace(ubman)
assert numcalls == 0
diff --git a/test/py/tests/test_ums.py b/test/py/tests/test_ums.py
index 387571c..caf6c0a 100644
--- a/test/py/tests/test_ums.py
+++ b/test/py/tests/test_ums.py
@@ -11,7 +11,7 @@
import pytest
import re
import time
-import u_boot_utils
+import utils
"""
Note: This test relies on:
@@ -74,13 +74,13 @@
"""
@pytest.mark.buildconfigspec('cmd_usb_mass_storage')
-def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
+def test_ums(ubman, env__usb_dev_port, env__block_devs):
"""Test the "ums" command; the host system must be able to enumerate a UMS
device when "ums" is running, block and optionally file I/O are tested,
and this device must disappear when "ums" is aborted.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
env__usb_dev_port: The single USB device-mode port specification on
which to run the test. See the file-level comment above for
details of the format.
@@ -96,7 +96,7 @@
if not have_writable_fs_partition:
# If 'writable_fs_subdir' is missing, we'll skip all parts of the
# testing which mount filesystems.
- u_boot_console.log.warning(
+ ubman.log.warning(
'boardenv missing "writable_fs_partition"; ' +
'UMS testing will be limited.')
@@ -109,12 +109,11 @@
tgt_dev_type = env__block_devs[0]['type']
tgt_dev_id = env__block_devs[0]['id']
if have_writable_fs_partition:
- mount_point = u_boot_console.config.env['env__mount_points'][0]
+ mount_point = ubman.config.env['env__mount_points'][0]
mount_subdir = env__block_devs[0]['writable_fs_subdir']
part_num = env__block_devs[0]['writable_fs_partition']
host_ums_part_node = '%s-part%d' % (host_ums_dev_node, part_num)
- test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin',
- 1024 * 1024);
+ test_f = utils.PersistentRandomFile(ubman, 'ums.bin', 1024 * 1024);
mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn
else:
host_ums_part_node = host_ums_dev_node
@@ -131,13 +130,13 @@
Nothing.
"""
- u_boot_console.log.action(
+ ubman.log.action(
'Starting long-running U-Boot ums shell command')
cmd = 'ums %s %s %s' % (tgt_usb_ctlr, tgt_dev_type, tgt_dev_id)
- u_boot_console.run_command(cmd, wait_for_prompt=False)
- u_boot_console.wait_for(re.compile('UMS: LUN.*[\r\n]'))
- fh = u_boot_utils.wait_until_open_succeeds(host_ums_part_node)
- u_boot_console.log.action('Reading raw data from UMS device')
+ ubman.run_command(cmd, wait_for_prompt=False)
+ ubman.wait_for(re.compile('UMS: LUN.*[\r\n]'))
+ fh = utils.wait_until_open_succeeds(host_ums_part_node)
+ ubman.log.action('Reading raw data from UMS device')
fh.read(4096)
fh.close()
@@ -151,9 +150,9 @@
Nothing.
"""
- u_boot_console.log.action('Mounting exported UMS device')
+ ubman.log.action('Mounting exported UMS device')
cmd = ('/bin/mount', host_ums_part_node)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
def umount(ignore_errors):
"""Unmount the block device that U-Boot exports.
@@ -168,9 +167,9 @@
Nothing.
"""
- u_boot_console.log.action('Unmounting UMS device')
+ ubman.log.action('Unmounting UMS device')
cmd = ('/bin/umount', host_ums_part_node)
- u_boot_utils.run_and_log(u_boot_console, cmd, ignore_errors)
+ utils.run_and_log(ubman, cmd, ignore_errors)
def stop_ums(ignore_errors):
"""Stop U-Boot's ums shell command from executing.
@@ -188,10 +187,10 @@
Nothing.
"""
- u_boot_console.log.action(
+ ubman.log.action(
'Stopping long-running U-Boot ums shell command')
- u_boot_console.ctrlc()
- u_boot_utils.wait_until_file_open_fails(host_ums_part_node,
+ ubman.ctrlc()
+ utils.wait_until_file_open_fails(host_ums_part_node,
ignore_errors)
ignore_cleanup_errors = True
@@ -200,13 +199,13 @@
start_ums()
try:
mount()
- u_boot_console.log.action('Writing test file via UMS')
+ ubman.log.action('Writing test file via UMS')
cmd = ('rm', '-f', mounted_test_fn)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
if os.path.exists(mounted_test_fn):
raise Exception('Could not rm target UMS test file')
cmd = ('cp', test_f.abs_fn, mounted_test_fn)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
ignore_cleanup_errors = False
finally:
umount(ignore_errors=ignore_cleanup_errors)
@@ -218,10 +217,10 @@
start_ums()
try:
mount()
- u_boot_console.log.action('Reading test file back via UMS')
- read_back_hash = u_boot_utils.md5sum_file(mounted_test_fn)
+ ubman.log.action('Reading test file back via UMS')
+ read_back_hash = utils.md5sum_file(mounted_test_fn)
cmd = ('rm', '-f', mounted_test_fn)
- u_boot_utils.run_and_log(u_boot_console, cmd)
+ utils.run_and_log(ubman, cmd)
ignore_cleanup_errors = False
finally:
umount(ignore_errors=ignore_cleanup_errors)
diff --git a/test/py/tests/test_unknown_cmd.py b/test/py/tests/test_unknown_cmd.py
index 8fc284a..b40c57f 100644
--- a/test/py/tests/test_unknown_cmd.py
+++ b/test/py/tests/test_unknown_cmd.py
@@ -2,12 +2,12 @@
# Copyright (c) 2015 Stephen Warren
# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
-def test_unknown_command(u_boot_console):
+def test_unknown_command(ubman):
"""Test that executing an unknown command causes U-Boot to print an
error."""
# The "unknown command" error is actively expected here,
# so error detection for it is disabled.
- with u_boot_console.disable_check('unknown_command'):
- response = u_boot_console.run_command('non_existent_cmd')
+ with ubman.disable_check('unknown_command'):
+ response = ubman.run_command('non_existent_cmd')
assert('Unknown command \'non_existent_cmd\' - try \'help\'' in response)
diff --git a/test/py/tests/test_upl.py b/test/py/tests/test_upl.py
index a1ccc8d..c79c32a 100644
--- a/test/py/tests/test_upl.py
+++ b/test/py/tests/test_upl.py
@@ -6,10 +6,10 @@
import os
import pytest
-import u_boot_utils
+import utils
@pytest.mark.boardspec('sandbox_vpl')
-def test_upl_handoff(u_boot_console):
+def test_upl_handoff(ubman):
"""Test of UPL handoff
This works by starting up U-Boot VPL, which gets to SPL and then sets up a
@@ -19,20 +19,19 @@
The entire FIT is loaded into memory in SPL (in upl_load_from_image()) so
that it can be inspected in upl_test_info_norun
"""
- cons = u_boot_console
- ram = os.path.join(cons.config.build_dir, 'ram.bin')
- fdt = os.path.join(cons.config.build_dir, 'u-boot.dtb')
+ ram = os.path.join(ubman.config.build_dir, 'ram.bin')
+ fdt = os.path.join(ubman.config.build_dir, 'u-boot.dtb')
# Remove any existing RAM file, so we don't have old data present
if os.path.exists(ram):
os.remove(ram)
flags = ['-m', ram, '-d', fdt, '--upl']
- cons.restart_uboot_with_flags(flags, use_dtb=False)
+ ubman.restart_uboot_with_flags(flags, use_dtb=False)
# Make sure that Universal Payload is detected in U-Boot proper
- output = cons.run_command('upl info')
+ output = ubman.run_command('upl info')
assert 'UPL state: active' == output
# Check the FIT offsets look correct
- output = cons.run_command('ut upl -f upl_test_info_norun')
+ output = ubman.run_command('ut upl -f upl_test_info_norun')
assert 'failures: 0' in output
diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py
index 9bef883..1dcd083 100644
--- a/test/py/tests/test_usb.py
+++ b/test/py/tests/test_usb.py
@@ -4,7 +4,7 @@
import pytest
import random
import re
-import u_boot_utils
+import utils
"""
Note: This test doesn't rely on boardenv_* configuration values but it can
@@ -20,20 +20,20 @@
env__usb_device_test_skip = False
"""
-def setup_usb(u_boot_console):
- if u_boot_console.config.env.get('env__usb_device_test_skip', True):
+def setup_usb(ubman):
+ if ubman.config.env.get('env__usb_device_test_skip', True):
pytest.skip('USB device test is not enabled')
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_start(u_boot_console):
- setup_usb(u_boot_console)
- output = u_boot_console.run_command('usb start')
+def test_usb_start(ubman):
+ setup_usb(ubman)
+ output = ubman.run_command('usb start')
# if output is empty, usb start may already run as part of preboot command
# re-start the usb, in that case
if not output:
- u_boot_console.run_command('usb stop')
- output = u_boot_console.run_command('usb start')
+ ubman.run_command('usb stop')
+ output = ubman.run_command('usb start')
if 'No USB device found' in output:
pytest.skip('No USB controller available')
@@ -61,26 +61,26 @@
if 'Starting the controller' in output:
assert 'USB XHCI' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
return controllers, storage_device
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_stop(u_boot_console):
- setup_usb(u_boot_console)
- output = u_boot_console.run_command('usb stop')
+def test_usb_stop(ubman):
+ setup_usb(ubman)
+ output = ubman.run_command('usb stop')
assert 'stopping USB..' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- output = u_boot_console.run_command('usb dev')
+ output = ubman.run_command('usb dev')
assert "USB is stopped. Please issue 'usb start' first." in output
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_reset(u_boot_console):
- setup_usb(u_boot_console)
- output = u_boot_console.run_command('usb reset')
+def test_usb_reset(ubman):
+ setup_usb(ubman)
+ output = ubman.run_command('usb reset')
if 'No USB device found' in output:
pytest.skip('No USB controller available')
@@ -107,13 +107,13 @@
if 'Starting the controller' in output:
assert 'USB XHCI' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_info(u_boot_console):
- controllers, storage_device = test_usb_start(u_boot_console)
- output = u_boot_console.run_command('usb info')
+def test_usb_info(ubman):
+ controllers, storage_device = test_usb_start(ubman)
+ output = ubman.run_command('usb info')
num_controller = len(re.findall(': Hub,', output))
num_mass_storage = len(re.findall(': Mass Storage,', output))
@@ -121,22 +121,22 @@
assert num_controller == controllers - 1
assert num_mass_storage == storage_device
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
for i in range(0, storage_device + controllers - 1):
- output = u_boot_console.run_command('usb info %d' % i)
+ output = ubman.run_command('usb info %d' % i)
num_controller = len(re.findall(': Hub,', output))
num_mass_storage = len(re.findall(': Mass Storage,', output))
assert num_controller + num_mass_storage == 1
assert 'No device available' not in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_tree(u_boot_console):
- controllers, storage_device = test_usb_start(u_boot_console)
- output = u_boot_console.run_command('usb tree')
+def test_usb_tree(ubman):
+ controllers, storage_device = test_usb_start(ubman)
+ output = ubman.run_command('usb tree')
num_controller = len(re.findall('Hub', output))
num_mass_storage = len(re.findall('Mass Storage', output))
@@ -144,14 +144,14 @@
assert num_controller == controllers - 1
assert num_mass_storage == storage_device
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('usb_storage')
-def test_usb_storage(u_boot_console):
- controllers, storage_device = test_usb_start(u_boot_console)
- output = u_boot_console.run_command('usb storage')
+def test_usb_storage(ubman):
+ controllers, storage_device = test_usb_start(ubman)
+ output = ubman.run_command('usb storage')
obj = re.findall(r'Capacity: (\d+|\d+[\.]?\d)', output)
devices = {}
@@ -167,17 +167,17 @@
except ValueError:
pytest.fail('USB storage device capacity not recognized')
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_dev(u_boot_console):
- controllers, storage_device = test_usb_start(u_boot_console)
- output = u_boot_console.run_command('usb dev')
+def test_usb_dev(ubman):
+ controllers, storage_device = test_usb_start(ubman)
+ output = ubman.run_command('usb dev')
assert 'no usb devices available' not in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
devices = {}
@@ -188,7 +188,7 @@
fail = 0
for x in range(0, storage_device):
devices[x]['detected'] = 'yes'
- output = u_boot_console.run_command('usb dev %d' % x)
+ output = ubman.run_command('usb dev %d' % x)
if 'Card did not respond to voltage select' in output:
fail = 1
@@ -201,7 +201,7 @@
devices[x]['detected'] = 'no'
assert 'is now current device' in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
if fail:
@@ -210,20 +210,20 @@
return devices, controllers, storage_device
@pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_part(u_boot_console):
- devices, controllers, storage_device = test_usb_dev(u_boot_console)
+def test_usb_part(ubman):
+ devices, controllers, storage_device = test_usb_dev(ubman)
if not devices:
pytest.skip('No devices detected')
- u_boot_console.run_command('usb part')
+ ubman.run_command('usb part')
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
for i in range(0, storage_device):
if devices[i]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % i)
- output = u_boot_console.run_command('usb part')
+ ubman.run_command('usb dev %d' % i)
+ output = ubman.run_command('usb part')
lines = output.split('\n')
part_fat = []
@@ -241,7 +241,7 @@
part_fat.append(part_id)
elif part_type == '83':
print('ext(2/4) detected')
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'fstype usb %d:%d' % (i, part_id)
)
if 'ext2' in output:
@@ -261,8 +261,8 @@
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_fat')
-def test_usb_fatls_fatinfo(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_fatls_fatinfo(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
@@ -270,7 +270,7 @@
fs = 'fat'
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -278,7 +278,7 @@
continue
for part in partitions:
- output = u_boot_console.run_command('fatls usb %d:%s' % (x, part))
+ output = ubman.run_command('fatls usb %d:%s' % (x, part))
if 'Unrecognized filesystem type' in output:
partitions.remove(part)
pytest.fail('Unrecognized filesystem')
@@ -286,7 +286,7 @@
if not re.search(r'\d file\(s\), \d dir\(s\)', output):
pytest.fail('%s read failed on device %d' % (fs.upper, x))
- output = u_boot_console.run_command('fatinfo usb %d:%s' % (x, part))
+ output = ubman.run_command('fatinfo usb %d:%s' % (x, part))
string = 'Filesystem: %s' % fs.upper
if re.search(string, output):
pytest.fail('%s FS failed on device %d' % (fs.upper(), x))
@@ -295,17 +295,17 @@
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
-def usb_fatload_fatwrite(u_boot_console, fs, x, part):
- addr = u_boot_utils.find_ram_base(u_boot_console)
+def usb_fatload_fatwrite(ubman, fs, x, part):
+ addr = utils.find_ram_base(ubman)
size = random.randint(4, 1 * 1024 * 1024)
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ output = ubman.run_command('crc32 %x %x' % (addr, size))
m = re.search('==> (.+?)', output)
if not m:
pytest.fail('CRC32 failed')
expected_crc32 = m.group(1)
file = '%s_%d' % ('uboot_test', size)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite usb %d:%s %x %s %x' % (fs, x, part, addr, file, size)
)
assert 'Unable to write' not in output
@@ -315,12 +315,12 @@
assert expected_text in output
alignment = int(
- u_boot_console.config.buildconfig.get(
+ ubman.config.buildconfig.get(
'config_sys_cacheline_size', 128
)
)
offset = random.randrange(alignment, 1024, alignment)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload usb %d:%s %x %s' % (fs, x, part, addr + offset, file)
)
assert 'Invalid FAT entry' not in output
@@ -329,7 +329,7 @@
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -339,8 +339,8 @@
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_fat')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_usb_fatload_fatwrite(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_fatload_fatwrite(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
@@ -348,7 +348,7 @@
fs = 'fat'
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -357,15 +357,15 @@
for part in partitions:
part_detect = 1
- usb_fatload_fatwrite(u_boot_console, fs, x, part)
+ usb_fatload_fatwrite(ubman, fs, x, part)
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext4')
-def test_usb_ext4ls(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext4ls(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
@@ -379,9 +379,9 @@
print('No %s table on this device' % fs.upper())
continue
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
for part in partitions:
- output = u_boot_console.run_command('%sls usb %d:%s' % (fs, x, part))
+ output = ubman.run_command('%sls usb %d:%s' % (fs, x, part))
if 'Unrecognized filesystem type' in output:
partitions.remove(part)
pytest.fail('Unrecognized filesystem')
@@ -390,17 +390,17 @@
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
-def usb_ext4load_ext4write(u_boot_console, fs, x, part):
- addr = u_boot_utils.find_ram_base(u_boot_console)
+def usb_ext4load_ext4write(ubman, fs, x, part):
+ addr = utils.find_ram_base(ubman)
size = random.randint(4, 1 * 1024 * 1024)
- output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+ output = ubman.run_command('crc32 %x %x' % (addr, size))
m = re.search('==> (.+?)', output)
if not m:
pytest.fail('CRC32 failed')
expected_crc32 = m.group(1)
file = '%s_%d' % ('uboot_test', size)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%swrite usb %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
)
assert 'Unable to write' not in output
@@ -410,13 +410,13 @@
assert expected_text in output
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload usb %d:%s %x /%s' % (fs, x, part, addr + offset, file)
)
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -427,8 +427,8 @@
@pytest.mark.buildconfigspec('cmd_ext4')
@pytest.mark.buildconfigspec('cmd_ext4_write')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_usb_ext4load_ext4write(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext4load_ext4write(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
@@ -436,7 +436,7 @@
fs = 'ext4'
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -445,15 +445,15 @@
for part in partitions:
part_detect = 1
- usb_ext4load_ext4write(u_boot_console, fs, x, part)
+ usb_ext4load_ext4write(ubman, fs, x, part)
if not part_detect:
pytest.skip('No %s partition detected' % fs.upper())
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext2')
-def test_usb_ext2ls(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext2ls(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
@@ -461,7 +461,7 @@
fs = 'ext2'
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -470,7 +470,7 @@
for part in partitions:
part_detect = 1
- output = u_boot_console.run_command('%sls usb %d:%s' % (fs, x, part))
+ output = ubman.run_command('%sls usb %d:%s' % (fs, x, part))
if 'Unrecognized filesystem type' in output:
partitions.remove(part)
pytest.fail('Unrecognized filesystem')
@@ -484,8 +484,8 @@
@pytest.mark.buildconfigspec('cmd_ext4')
@pytest.mark.buildconfigspec('cmd_ext4_write')
@pytest.mark.buildconfigspec('cmd_memory')
-def test_usb_ext2load(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext2load(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
@@ -494,7 +494,7 @@
fs = 'ext2'
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
try:
partitions = devices[x][fs]
except:
@@ -504,17 +504,17 @@
for part in partitions:
part_detect = 1
file, size, expected_crc32 = \
- usb_ext4load_ext4write(u_boot_console, fs, x, part)
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ usb_ext4load_ext4write(ubman, fs, x, part)
+ addr = utils.find_ram_base(ubman)
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'%sload usb %d:%s %x /%s' % (fs, x, part, addr + offset, file)
)
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -524,15 +524,15 @@
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_usb_ls(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ls(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
part_detect = 0
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
@@ -542,7 +542,7 @@
for part in partitions:
part_detect = 1
- output = u_boot_console.run_command('ls usb %d:%s' % (x, part))
+ output = ubman.run_command('ls usb %d:%s' % (x, part))
if re.search(r'No \w+ table on this device', output):
pytest.fail(
'%s: Partition table not found %d' % (fs.upper(), x)
@@ -554,15 +554,15 @@
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_ext4_write')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_usb_load(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_load(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
part_detect = 0
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
@@ -572,25 +572,25 @@
for part in partitions:
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
if fs == 'fat':
file, size, expected_crc32 = \
- usb_fatload_fatwrite(u_boot_console, fs, x, part)
+ usb_fatload_fatwrite(ubman, fs, x, part)
elif fs in ['ext4', 'ext2']:
file, size, expected_crc32 = \
- usb_ext4load_ext4write(u_boot_console, fs, x, part)
+ usb_ext4load_ext4write(ubman, fs, x, part)
else:
raise Exception('Unsupported filesystem type %s' % fs)
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'load usb %d:%s %x /%s' % (x, part, addr + offset, file)
)
expected_text = '%d bytes read' % size
assert expected_text in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'crc32 %x $filesize' % (addr + offset)
)
assert expected_crc32 in output
@@ -600,15 +600,15 @@
@pytest.mark.buildconfigspec('cmd_usb')
@pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_usb_save(u_boot_console):
- devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_save(ubman):
+ devices, controllers, storage_device = test_usb_part(ubman)
if not devices:
pytest.skip('No devices detected')
part_detect = 0
for x in range(0, int(storage_device)):
if devices[x]['detected'] == 'yes':
- u_boot_console.run_command('usb dev %d' % x)
+ ubman.run_command('usb dev %d' % x)
for fs in ['fat', 'ext2', 'ext4']:
try:
partitions = devices[x][fs]
@@ -618,12 +618,12 @@
for part in partitions:
part_detect = 1
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
size = random.randint(4, 1 * 1024 * 1024)
file = '%s_%d' % ('uboot_test', size)
offset = random.randrange(128, 1024, 128)
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'save usb %d:%s %x /%s %x'
% (x, part, addr + offset, file, size)
)
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index d2d8ce1..ea0c43c 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -13,7 +13,7 @@
import os.path
import pytest
-import u_boot_utils
+import utils
# pylint: disable=E0611
from tests import fs_helper
from test_android import test_abootimg
@@ -27,12 +27,12 @@
if not os.path.exists(dirname):
os.mkdir(dirname)
-def setup_image(cons, devnum, part_type, img_size=20, second_part=False,
+def setup_image(ubman, devnum, part_type, img_size=20, second_part=False,
basename='mmc'):
"""Create a disk image with a single partition
Args:
- cons (ConsoleBase): Console to use
+ ubman (ConsoleBase): Console to use
devnum (int): Device number to use, e.g. 1
part_type (int): Partition type, e.g. 0xc for FAT32
img_size (int): Image size in MiB
@@ -44,26 +44,26 @@
str: Filename of MMC image
str: Directory name of scratch directory
"""
- fname = os.path.join(cons.config.source_dir, f'{basename}{devnum}.img')
- mnt = os.path.join(cons.config.persistent_data_dir, 'scratch')
+ fname = os.path.join(ubman.config.source_dir, f'{basename}{devnum}.img')
+ mnt = os.path.join(ubman.config.persistent_data_dir, 'scratch')
mkdir_cond(mnt)
spec = f'type={part_type:x}, size={img_size - 2}M, start=1M, bootable'
if second_part:
spec += '\ntype=c'
- u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
- u_boot_utils.run_and_log(cons, f'sfdisk {fname}',
+ utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+ utils.run_and_log(ubman, f'sfdisk {fname}',
stdin=spec.encode('utf-8'))
return fname, mnt
-def setup_bootmenu_image(cons):
+def setup_bootmenu_image(ubman):
"""Create a 20MB disk image with a single ext4 partition
This is modelled on Armbian 22.08 Jammy
"""
mmc_dev = 4
- fname, mnt = setup_image(cons, mmc_dev, 0x83)
+ fname, mnt = setup_image(ubman, mmc_dev, 0x83)
script = '''# DO NOT EDIT THIS FILE
#
@@ -146,16 +146,16 @@
with open(cmd_fname, 'w', encoding='ascii') as outf:
print(script, file=outf)
- infname = os.path.join(cons.config.source_dir,
+ infname = os.path.join(ubman.config.source_dir,
'test/py/tests/bootstd/armbian.bmp.xz')
bmp_file = os.path.join(bootdir, 'boot.bmp')
- u_boot_utils.run_and_log(
- cons,
+ utils.run_and_log(
+ ubman,
['sh', '-c', f'xz -dc {infname} >{bmp_file}'])
- mkimage = cons.config.build_dir + '/tools/mkimage'
- u_boot_utils.run_and_log(
- cons, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}')
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ utils.run_and_log(
+ ubman, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}')
kernel = 'vmlinuz-5.15.63-rockchip64'
target = os.path.join(bootdir, kernel)
@@ -165,21 +165,21 @@
symlink = os.path.join(bootdir, 'Image')
if os.path.exists(symlink):
os.remove(symlink)
- u_boot_utils.run_and_log(
- cons, f'echo here {kernel} {symlink}')
+ utils.run_and_log(
+ ubman, f'echo here {kernel} {symlink}')
os.symlink(kernel, symlink)
fsfile = 'ext18M.img'
- u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
- u_boot_utils.run_and_log(cons, f'mkfs.ext4 {fsfile} -d {mnt}')
- u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
- u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
- u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
+ utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
+ utils.run_and_log(ubman, f'mkfs.ext4 {fsfile} -d {mnt}')
+ utils.run_and_log(ubman, f'dd if={fsfile} of={fname} bs=1M seek=1')
+ utils.run_and_log(ubman, f'rm -rf {mnt}')
+ utils.run_and_log(ubman, f'rm -f {fsfile}')
-def setup_bootflow_image(cons):
+def setup_bootflow_image(ubman):
"""Create a 20MB disk image with a single FAT partition"""
mmc_dev = 1
- fname, mnt = setup_image(cons, mmc_dev, 0xc, second_part=True)
+ fname, mnt = setup_image(ubman, mmc_dev, 0xc, second_part=True)
vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
@@ -204,12 +204,12 @@
with open(conf, 'w', encoding='ascii') as fd:
print(script, file=fd)
- inf = os.path.join(cons.config.persistent_data_dir, 'inf')
+ inf = os.path.join(ubman.config.persistent_data_dir, 'inf')
with open(inf, 'wb') as fd:
fd.write(gzip.compress(b'vmlinux'))
- mkimage = cons.config.build_dir + '/tools/mkimage'
- u_boot_utils.run_and_log(
- cons, f'{mkimage} -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ utils.run_and_log(
+ ubman, f'{mkimage} -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd:
print('initrd', file=fd)
@@ -217,28 +217,28 @@
mkdir_cond(os.path.join(mnt, dtbdir))
dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb')
- u_boot_utils.run_and_log(
- cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
+ utils.run_and_log(
+ ubman, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
fsfile = 'vfat18M.img'
- u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
- u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}')
- u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/'])
- u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
- u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
- u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
+ utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
+ utils.run_and_log(ubman, f'mkfs.vfat {fsfile}')
+ utils.run_and_log(ubman, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/'])
+ utils.run_and_log(ubman, f'dd if={fsfile} of={fname} bs=1M seek=1')
+ utils.run_and_log(ubman, f'rm -rf {mnt}')
+ utils.run_and_log(ubman, f'rm -f {fsfile}')
-def setup_cros_image(cons):
+def setup_cros_image(ubman):
"""Create a 20MB disk image with ChromiumOS partitions"""
Partition = collections.namedtuple('part', 'start,size,name')
parts = {}
disk_data = None
- def pack_kernel(cons, arch, kern, dummy):
+ def pack_kernel(ubman, arch, kern, dummy):
"""Pack a kernel containing some fake data
Args:
- cons (ConsoleBase): Console to use
+ ubman (ConsoleBase): Console to use
arch (str): Architecture to use ('x86' or 'arm')
kern (str): Filename containing kernel
dummy (str): Dummy filename to use for config and bootloader
@@ -246,10 +246,10 @@
Return:
bytes: Packed-kernel data
"""
- kern_part = os.path.join(cons.config.result_dir,
+ kern_part = os.path.join(ubman.config.result_dir,
f'kern-part-{arch}.bin')
- u_boot_utils.run_and_log(
- cons,
+ utils.run_and_log(
+ ubman,
f'futility vbutil_kernel --pack {kern_part} '
'--keyblock doc/chromium/files/devkeys/kernel.keyblock '
'--signprivate doc/chromium/files/devkeys/kernel_data_key.vbprivk '
@@ -275,9 +275,9 @@
disk_data = disk_data[:start] + data + disk_data[start + len(data):]
mmc_dev = 5
- fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
- u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
- u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+ fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
+ utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+ utils.run_and_log(ubman, f'cgpt create {fname}')
uuid_state = 'ebd0a0a2-b9e5-4433-87c0-68b6b72699c7'
uuid_kern = 'fe3a2a5d-4f32-41a7-b725-accc3285a309'
@@ -316,13 +316,13 @@
size = int(size_str[:-1]) * sect_1mb
else:
size = int(size_str)
- u_boot_utils.run_and_log(
- cons,
+ utils.run_and_log(
+ ubman,
f"cgpt add -i {part['num']} -b {ptr} -s {size} -t {part['type']} {fname}")
ptr += size
- u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
- out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+ utils.run_and_log(ubman, f'cgpt boot -p {fname}')
+ out = utils.run_and_log(ubman, f'cgpt show -q {fname}')
# We expect something like this:
# 8239 2048 1 Basic data
@@ -344,14 +344,14 @@
parts[int(num)] = Partition(int(start), int(size), name)
# Set up the kernel command-line
- dummy = os.path.join(cons.config.result_dir, 'dummy.txt')
+ dummy = os.path.join(ubman.config.result_dir, 'dummy.txt')
with open(dummy, 'wb') as outf:
outf.write(b'BOOT_IMAGE=/vmlinuz-5.15.0-121-generic root=/dev/nvme0n1p1 ro quiet splash vt.handoff=7')
# For now we just use dummy kernels. This limits testing to just detecting
# a signed kernel. We could add support for the x86 data structures so that
# testing could cover getting the cmdline, setup.bin and other pieces.
- kern = os.path.join(cons.config.result_dir, 'kern.bin')
+ kern = os.path.join(ubman.config.result_dir, 'kern.bin')
with open(kern, 'wb') as outf:
outf.write(b'kernel\n')
@@ -359,15 +359,15 @@
disk_data = inf.read()
# put x86 kernel in partition 2 and arm one in partition 4
- set_part_data(2, pack_kernel(cons, 'x86', kern, dummy))
- set_part_data(4, pack_kernel(cons, 'arm', kern, dummy))
+ set_part_data(2, pack_kernel(ubman, 'x86', kern, dummy))
+ set_part_data(4, pack_kernel(ubman, 'arm', kern, dummy))
with open(fname, 'wb') as outf:
outf.write(disk_data)
return fname
-def setup_android_image(cons):
+def setup_android_image(ubman):
"""Create a 20MB disk image with Android partitions"""
Partition = collections.namedtuple('part', 'start,size,name')
parts = {}
@@ -388,9 +388,9 @@
disk_data = disk_data[:start] + data + disk_data[start + len(data):]
mmc_dev = 7
- fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
- u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
- u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+ fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
+ utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+ utils.run_and_log(ubman, f'cgpt create {fname}')
ptr = 40
@@ -412,13 +412,13 @@
size = int(size_str[:-1]) * sect_1mb
else:
size = int(size_str)
- u_boot_utils.run_and_log(
- cons,
+ utils.run_and_log(
+ ubman,
f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}")
ptr += size
- u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
- out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+ utils.run_and_log(ubman, f'cgpt boot -p {fname}')
+ out = utils.run_and_log(ubman, f'cgpt show -q {fname}')
# Create a dict (indexed by partition number) containing the above info
for line in out.splitlines():
@@ -428,13 +428,13 @@
with open(fname, 'rb') as inf:
disk_data = inf.read()
- test_abootimg.AbootimgTestDiskImage(cons, 'bootv4.img', test_abootimg.boot_img_hex)
- boot_img = os.path.join(cons.config.result_dir, 'bootv4.img')
+ test_abootimg.AbootimgTestDiskImage(ubman, 'bootv4.img', test_abootimg.boot_img_hex)
+ boot_img = os.path.join(ubman.config.result_dir, 'bootv4.img')
with open(boot_img, 'rb') as inf:
set_part_data(2, inf.read())
- test_abootimg.AbootimgTestDiskImage(cons, 'vendor_boot.img', test_abootimg.vboot_img_hex)
- vendor_boot_img = os.path.join(cons.config.result_dir, 'vendor_boot.img')
+ test_abootimg.AbootimgTestDiskImage(ubman, 'vendor_boot.img', test_abootimg.vboot_img_hex)
+ vendor_boot_img = os.path.join(ubman.config.result_dir, 'vendor_boot.img')
with open(vendor_boot_img, 'rb') as inf:
set_part_data(4, inf.read())
@@ -444,9 +444,9 @@
print(f'wrote to {fname}')
mmc_dev = 8
- fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
- u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
- u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+ fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
+ utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+ utils.run_and_log(ubman, f'cgpt create {fname}')
ptr = 40
@@ -466,13 +466,13 @@
size = int(size_str[:-1]) * sect_1mb
else:
size = int(size_str)
- u_boot_utils.run_and_log(
- cons,
+ utils.run_and_log(
+ ubman,
f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}")
ptr += size
- u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
- out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+ utils.run_and_log(ubman, f'cgpt boot -p {fname}')
+ out = utils.run_and_log(ubman, f'cgpt show -q {fname}')
# Create a dict (indexed by partition number) containing the above info
for line in out.splitlines():
@@ -482,8 +482,8 @@
with open(fname, 'rb') as inf:
disk_data = inf.read()
- test_abootimg.AbootimgTestDiskImage(cons, 'boot.img', test_abootimg.img_hex)
- boot_img = os.path.join(cons.config.result_dir, 'boot.img')
+ test_abootimg.AbootimgTestDiskImage(ubman, 'boot.img', test_abootimg.img_hex)
+ boot_img = os.path.join(ubman.config.result_dir, 'boot.img')
with open(boot_img, 'rb') as inf:
set_part_data(2, inf.read())
@@ -494,95 +494,95 @@
return fname
-def setup_cedit_file(cons):
+def setup_cedit_file(ubman):
"""Set up a .dtb file for use with testing expo and configuration editor"""
- infname = os.path.join(cons.config.source_dir,
+ infname = os.path.join(ubman.config.source_dir,
'test/boot/files/expo_layout.dts')
- inhname = os.path.join(cons.config.source_dir,
+ inhname = os.path.join(ubman.config.source_dir,
'test/boot/files/expo_ids.h')
- expo_tool = os.path.join(cons.config.source_dir, 'tools/expo.py')
+ expo_tool = os.path.join(ubman.config.source_dir, 'tools/expo.py')
outfname = 'cedit.dtb'
- u_boot_utils.run_and_log(
- cons, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}')
+ utils.run_and_log(
+ ubman, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}')
@pytest.mark.buildconfigspec('ut_dm')
-def test_ut_dm_init(u_boot_console):
+def test_ut_dm_init(ubman):
"""Initialize data for ut dm tests."""
- fn = u_boot_console.config.source_dir + '/testflash.bin'
+ fn = ubman.config.source_dir + '/testflash.bin'
if not os.path.exists(fn):
data = b'this is a test'
data += b'\x00' * ((4 * 1024 * 1024) - len(data))
with open(fn, 'wb') as fh:
fh.write(data)
- fn = u_boot_console.config.source_dir + '/spi.bin'
+ fn = ubman.config.source_dir + '/spi.bin'
if not os.path.exists(fn):
data = b'\x00' * (2 * 1024 * 1024)
with open(fn, 'wb') as fh:
fh.write(data)
# Create a file with a single partition
- fn = u_boot_console.config.source_dir + '/scsi.img'
+ fn = ubman.config.source_dir + '/scsi.img'
if not os.path.exists(fn):
data = b'\x00' * (2 * 1024 * 1024)
with open(fn, 'wb') as fh:
fh.write(data)
- u_boot_utils.run_and_log(
- u_boot_console, f'sfdisk {fn}', stdin=b'type=83')
+ utils.run_and_log(
+ ubman, f'sfdisk {fn}', stdin=b'type=83')
- fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB', None)
- fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB', None)
+ fs_helper.mk_fs(ubman.config, 'ext2', 0x200000, '2MB', None)
+ fs_helper.mk_fs(ubman.config, 'fat32', 0x100000, '1MB', None)
mmc_dev = 6
- fn = os.path.join(u_boot_console.config.source_dir, f'mmc{mmc_dev}.img')
+ fn = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
data = b'\x00' * (12 * 1024 * 1024)
with open(fn, 'wb') as fh:
fh.write(data)
-def setup_efi_image(cons):
+def setup_efi_image(ubman):
"""Create a 20MB disk image with an EFI app on it"""
devnum = 1
basename = 'flash'
- fname, mnt = setup_image(cons, devnum, 0xc, second_part=True,
+ fname, mnt = setup_image(ubman, devnum, 0xc, second_part=True,
basename=basename)
efi_dir = os.path.join(mnt, 'EFI')
mkdir_cond(efi_dir)
bootdir = os.path.join(efi_dir, 'BOOT')
mkdir_cond(bootdir)
- efi_src = os.path.join(cons.config.build_dir,
+ efi_src = os.path.join(ubman.config.build_dir,
'lib/efi_loader/testapp.efi')
efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI')
with open(efi_src, 'rb') as inf:
with open(efi_dst, 'wb') as outf:
outf.write(inf.read())
fsfile = 'vfat18M.img'
- u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
- u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}')
- u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/'])
- u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
- u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
- u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
+ utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
+ utils.run_and_log(ubman, f'mkfs.vfat {fsfile}')
+ utils.run_and_log(ubman, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/'])
+ utils.run_and_log(ubman, f'dd if={fsfile} of={fname} bs=1M seek=1')
+ utils.run_and_log(ubman, f'rm -rf {mnt}')
+ utils.run_and_log(ubman, f'rm -f {fsfile}')
@pytest.mark.buildconfigspec('cmd_bootflow')
@pytest.mark.buildconfigspec('sandbox')
-def test_ut_dm_init_bootstd(u_boot_console):
+def test_ut_dm_init_bootstd(ubman):
"""Initialise data for bootflow tests"""
- setup_bootflow_image(u_boot_console)
- setup_bootmenu_image(u_boot_console)
- setup_cedit_file(u_boot_console)
- setup_cros_image(u_boot_console)
- setup_android_image(u_boot_console)
- setup_efi_image(u_boot_console)
+ setup_bootflow_image(ubman)
+ setup_bootmenu_image(ubman)
+ setup_cedit_file(ubman)
+ setup_cros_image(ubman)
+ setup_android_image(ubman)
+ setup_efi_image(ubman)
# Restart so that the new mmc1.img is picked up
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
-def test_ut(u_boot_console, ut_subtest):
+def test_ut(ubman, ut_subtest):
"""Execute a "ut" subtest.
The subtests are collected in function generate_ut_subtest() from linker
@@ -595,16 +595,16 @@
implemented in C function foo_test_bar().
Args:
- u_boot_console (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
ut_subtest (str): test to be executed via command ut, e.g 'foo bar' to
execute command 'ut foo bar'
"""
if ut_subtest == 'hush hush_test_simple_dollar':
# ut hush hush_test_simple_dollar prints "Unknown command" on purpose.
- with u_boot_console.disable_check('unknown_command'):
- output = u_boot_console.run_command('ut ' + ut_subtest)
+ with ubman.disable_check('unknown_command'):
+ output = ubman.run_command('ut ' + ut_subtest)
assert 'Unknown command \'quux\' - try \'help\'' in output
else:
- output = u_boot_console.run_command('ut ' + ut_subtest)
+ output = ubman.run_command('ut ' + ut_subtest)
assert output.endswith('failures: 0')
diff --git a/test/py/tests/test_vbe.py b/test/py/tests/test_vbe.py
index 861df3f..a1f32f3 100644
--- a/test/py/tests/test_vbe.py
+++ b/test/py/tests/test_vbe.py
@@ -90,11 +90,10 @@
@pytest.mark.boardspec('sandbox_flattree')
@pytest.mark.requiredtool('dtc')
-def test_vbe(u_boot_console):
- cons = u_boot_console
- kernel = fit_util.make_kernel(cons, 'vbe-kernel.bin', 'kernel')
- fdt = fit_util.make_dtb(cons, base_fdt, 'vbe-fdt')
- fdt_out = fit_util.make_fname(cons, 'fdt-out.dtb')
+def test_vbe(ubman):
+ kernel = fit_util.make_kernel(ubman, 'vbe-kernel.bin', 'kernel')
+ fdt = fit_util.make_dtb(ubman, base_fdt, 'vbe-fdt')
+ fdt_out = fit_util.make_fname(ubman, 'fdt-out.dtb')
params = {
'fit_addr' : 0x1000,
@@ -108,13 +107,13 @@
'compression' : 'none',
}
- mkimage = cons.config.build_dir + '/tools/mkimage'
- fit = fit_util.make_fit(cons, mkimage, base_its, params, 'test-vbe.fit',
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ fit = fit_util.make_fit(ubman, mkimage, base_its, params, 'test-vbe.fit',
base_fdt)
params['fit'] = fit
cmd = base_script % params
- with cons.log.section('Kernel load'):
- output = cons.run_command_list(cmd.splitlines())
+ with ubman.log.section('Kernel load'):
+ output = ubman.run_command_list(cmd.splitlines())
assert 'failures: 0' in output[-1]
diff --git a/test/py/tests/test_vbe_vpl.py b/test/py/tests/test_vbe_vpl.py
index ed12d3a..f011b03 100644
--- a/test/py/tests/test_vbe_vpl.py
+++ b/test/py/tests/test_vbe_vpl.py
@@ -6,35 +6,34 @@
import os
import pytest
-import u_boot_utils
+import utils
@pytest.mark.boardspec('sandbox_vpl')
@pytest.mark.requiredtool('dtc')
-def test_vbe_vpl(u_boot_console):
- cons = u_boot_console
- #cmd = [cons.config.build_dir + fname, '-v']
- ram = os.path.join(cons.config.build_dir, 'ram.bin')
- fdt = os.path.join(cons.config.build_dir, 'arch/sandbox/dts/test.dtb')
- image_fname = os.path.join(cons.config.build_dir, 'image.bin')
+def test_vbe_vpl(ubman):
+ #cmd = [ubman.config.build_dir + fname, '-v']
+ ram = os.path.join(ubman.config.build_dir, 'ram.bin')
+ fdt = os.path.join(ubman.config.build_dir, 'arch/sandbox/dts/test.dtb')
+ image_fname = os.path.join(ubman.config.build_dir, 'image.bin')
# Enable firmware1 and the mmc that it uses. These are needed for the full
# VBE flow.
- u_boot_utils.run_and_log(
- cons, f'fdtput -t s {fdt} /bootstd/firmware0 status disabled')
- u_boot_utils.run_and_log(
- cons, f'fdtput -t s {fdt} /bootstd/firmware1 status okay')
- u_boot_utils.run_and_log(
- cons, f'fdtput -t s {fdt} /mmc3 status okay')
- u_boot_utils.run_and_log(
- cons, f'fdtput -t s {fdt} /mmc3 filename {image_fname}')
+ utils.run_and_log(
+ ubman, f'fdtput -t s {fdt} /bootstd/firmware0 status disabled')
+ utils.run_and_log(
+ ubman, f'fdtput -t s {fdt} /bootstd/firmware1 status okay')
+ utils.run_and_log(
+ ubman, f'fdtput -t s {fdt} /mmc3 status okay')
+ utils.run_and_log(
+ ubman, f'fdtput -t s {fdt} /mmc3 filename {image_fname}')
# Remove any existing RAM file, so we don't have old data present
if os.path.exists(ram):
os.remove(ram)
flags = ['-p', image_fname, '-w', '-s', 'state.dtb']
- cons.restart_uboot_with_flags(flags)
+ ubman.restart_uboot_with_flags(flags)
# Make sure that VBE was used in both VPL (to load SPL) and SPL (to load
# U-Boot
- output = cons.run_command('vbe state')
+ output = ubman.run_command('vbe state')
assert output == 'Phases: VPL SPL'
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index 7e0e8e4..7a7f9c3 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -42,12 +42,12 @@
import shutil
import struct
import pytest
-import u_boot_utils as util
+import utils
import vboot_forge
import vboot_evil
# Common helper functions
-def dtc(dts, cons, dtc_args, datadir, tmpdir, dtb):
+def dtc(dts, ubman, dtc_args, datadir, tmpdir, dtb):
"""Run the device tree compiler to compile a .dts file
The output file will be the same as the input file but with a .dtb
@@ -55,31 +55,31 @@
Args:
dts: Device tree file to compile.
- cons: U-Boot console.
+ ubman: U-Boot console.
dtc_args: DTC arguments.
datadir: Path to data directory.
tmpdir: Path to temp directory.
dtb: Resulting DTB file.
"""
dtb = dts.replace('.dts', '.dtb')
- util.run_and_log(cons, 'dtc %s %s%s -O dtb '
- '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
+ utils.run_and_log(ubman, 'dtc %s %s%s -O dtb '
+ '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
-def make_fit(its, cons, mkimage, dtc_args, datadir, fit):
+def make_fit(its, ubman, mkimage, dtc_args, datadir, fit):
"""Make a new FIT from the .its source file.
This runs 'mkimage -f' to create a new FIT.
Args:
its: Filename containing .its source.
- cons: U-Boot console.
+ ubman: U-Boot console.
mkimage: Path to mkimage utility.
dtc_args: DTC arguments.
datadir: Path to data directory.
fit: Resulting FIT file.
"""
- util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
- '%s%s' % (datadir, its), fit])
+ utils.run_and_log(ubman, [mkimage, '-D', dtc_args, '-f',
+ '%s%s' % (datadir, its), fit])
# Only run the full suite on a few combinations, since it doesn't add any more
# test coverage.
@@ -113,7 +113,7 @@
@pytest.mark.requiredtool('openssl')
@pytest.mark.parametrize("name,sha_algo,padding,sign_options,required,full_test,algo_arg,global_sign",
TESTDATA)
-def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
+def test_vboot(ubman, name, sha_algo, padding, sign_options, required,
full_test, algo_arg, global_sign):
"""Test verified boot signing with mkimage and verification with 'bootm'.
@@ -134,8 +134,8 @@
options: Options provided to the compiler.
"""
dtb = dts.replace('.dts', '.dtb')
- util.run_and_log(cons, 'dtc %s %s%s -O dtb '
- '-o %s%s %s' % (dtc_args, datadir, dts, tmpdir, dtb, options))
+ utils.run_and_log(ubman, 'dtc %s %s%s -O dtb -o %s%s %s' %
+ (dtc_args, datadir, dts, tmpdir, dtb, options))
def run_binman(dtb):
"""Run binman to build an image
@@ -145,9 +145,9 @@
"""
pythonpath = os.environ.get('PYTHONPATH', '')
os.environ['PYTHONPATH'] = pythonpath + ':' + '%s/../scripts/dtc/pylibfdt' % tmpdir
- util.run_and_log(cons, [binman, 'build', '-d', "%s/%s" % (tmpdir,dtb),
- '-a', "pre-load-key-path=%s" % tmpdir, '-O',
- tmpdir, '-I', tmpdir])
+ utils.run_and_log(ubman, [binman, 'build', '-d', "%s/%s" % (tmpdir,dtb),
+ '-a', "pre-load-key-path=%s" % tmpdir, '-O',
+ tmpdir, '-I', tmpdir])
os.environ['PYTHONPATH'] = pythonpath
def run_bootm(sha_algo, test_type, expect_string, boots, fit=None):
@@ -167,9 +167,9 @@
"""
if not fit:
fit = '%stest.fit' % tmpdir
- cons.restart_uboot()
- with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)):
- output = cons.run_command_list(
+ ubman.restart_uboot()
+ with ubman.log.section('Verified boot %s %s' % (sha_algo, test_type)):
+ output = ubman.run_command_list(
['host load hostfs - 100 %s' % fit,
'fdt addr 100',
'bootm 100'])
@@ -194,8 +194,8 @@
args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit]
if options:
args += options.split(' ')
- cons.log.action('%s: Sign images' % sha_algo)
- util.run_and_log(cons, args)
+ ubman.log.action('%s: Sign images' % sha_algo)
+ utils.run_and_log(ubman, args)
def sign_fit_dtb(sha_algo, options, dtb):
"""Sign the FIT
@@ -211,8 +211,8 @@
args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit]
if options:
args += options.split(' ')
- cons.log.action('%s: Sign images' % sha_algo)
- util.run_and_log(cons, args)
+ ubman.log.action('%s: Sign images' % sha_algo)
+ utils.run_and_log(ubman, args)
def sign_fit_norequire(sha_algo, options):
"""Sign the FIT
@@ -228,8 +228,8 @@
args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, fit]
if options:
args += options.split(' ')
- cons.log.action('%s: Sign images' % sha_algo)
- util.run_and_log(cons, args)
+ ubman.log.action('%s: Sign images' % sha_algo)
+ utils.run_and_log(ubman, args)
def replace_fit_totalsize(size):
"""Replace FIT header's totalsize with something greater.
@@ -278,14 +278,14 @@
else:
rsa_keygen_bits = 2048
- util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out %s%s.key '
+ utils.run_and_log(ubman, 'openssl genpkey -algorithm RSA -out %s%s.key '
'-pkeyopt rsa_keygen_bits:%d '
'-pkeyopt rsa_keygen_pubexp:%d' %
(tmpdir, name, rsa_keygen_bits, public_exponent))
# Create a certificate containing the public key
- util.run_and_log(cons, 'openssl req -batch -new -x509 -key %s%s.key '
- '-out %s%s.crt' % (tmpdir, name, tmpdir, name))
+ utils.run_and_log(ubman, 'openssl req -batch -new -x509 -key %s%s.key '
+ '-out %s%s.crt' % (tmpdir, name, tmpdir, name))
def test_with_algo(sha_algo, padding, sign_options):
"""Test verified boot with the given hash algorithm.
@@ -303,12 +303,12 @@
# Compile our device tree files for kernel and U-Boot. These are
# regenerated here since mkimage will modify them (by adding a
# public key) below.
- dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
- dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-kernel.dts', ubman, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
# Build the FIT, but don't sign anything yet
- cons.log.action('%s: Test FIT with signed images' % sha_algo)
- make_fit('sign-images-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ ubman.log.action('%s: Test FIT with signed images' % sha_algo)
+ make_fit('sign-images-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
run_bootm(sha_algo, 'unsigned images', ' - OK' if algo_arg else 'dev-', True)
# Sign images with our dev keys
@@ -316,19 +316,19 @@
run_bootm(sha_algo, 'signed images', 'dev+', True)
# Create a fresh .dtb without the public keys
- dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
- cons.log.action('%s: Test FIT with signed configuration' % sha_algo)
- make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ ubman.log.action('%s: Test FIT with signed configuration' % sha_algo)
+ make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
run_bootm(sha_algo, 'unsigned config', '%s+ OK' % ('sha256' if algo_arg else sha_algo), True)
# Sign images with our dev keys
sign_fit(sha_algo, sign_options)
run_bootm(sha_algo, 'signed config', 'dev+', True)
- cons.log.action('%s: Check signed config on the host' % sha_algo)
+ ubman.log.action('%s: Check signed config on the host' % sha_algo)
- util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
+ utils.run_and_log(ubman, [fit_check_sign, '-f', fit, '-k', dtb])
if full_test:
# Make sure that U-Boot checks that the config is in the list of
@@ -340,8 +340,8 @@
root, strblock = vboot_forge.manipulate(root, strblock)
with open(ffit, 'w+b') as fd:
vboot_forge.write_fdt(root, strblock, fd)
- util.run_and_log_expect_exception(
- cons, [fit_check_sign, '-f', ffit, '-k', dtb],
+ utils.run_and_log_expect_exception(
+ ubman, [fit_check_sign, '-f', ffit, '-k', dtb],
1, 'Failed to verify required signature')
run_bootm(sha_algo, 'forged config', 'Bad Data Hash', False, ffit)
@@ -351,8 +351,8 @@
shutil.copyfile(fit, efit)
vboot_evil.add_evil_node(fit, efit, evil_kernel, 'fakeroot')
- util.run_and_log_expect_exception(
- cons, [fit_check_sign, '-f', efit, '-k', dtb],
+ utils.run_and_log_expect_exception(
+ ubman, [fit_check_sign, '-f', efit, '-k', dtb],
1, 'Failed to verify required signature')
run_bootm(sha_algo, 'evil fakeroot', 'Bad FIT kernel image format',
False, efit)
@@ -363,42 +363,42 @@
vboot_evil.add_evil_node(fit, efit, evil_kernel, 'kernel@')
msg = 'Signature checking prevents use of unit addresses (@) in nodes'
- util.run_and_log_expect_exception(
- cons, [fit_check_sign, '-f', efit, '-k', dtb],
+ utils.run_and_log_expect_exception(
+ ubman, [fit_check_sign, '-f', efit, '-k', dtb],
1, msg)
run_bootm(sha_algo, 'evil kernel@', msg, False, efit)
# Create a new properly signed fit and replace header bytes
- make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
sign_fit(sha_algo, sign_options)
- bcfg = u_boot_console.config.buildconfig
+ bcfg = ubman.config.buildconfig
max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0)
existing_size = replace_fit_totalsize(max_size + 1)
run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash',
False)
- cons.log.action('%s: Check overflowed FIT header totalsize' % sha_algo)
+ ubman.log.action('%s: Check overflowed FIT header totalsize' % sha_algo)
# Replace with existing header bytes
replace_fit_totalsize(existing_size)
run_bootm(sha_algo, 'signed config', 'dev+', True)
- cons.log.action('%s: Check default FIT header totalsize' % sha_algo)
+ ubman.log.action('%s: Check default FIT header totalsize' % sha_algo)
# Increment the first byte of the signature, which should cause failure
- sig = util.run_and_log(cons, 'fdtget -t bx %s %s value' %
- (fit, sig_node))
+ sig = utils.run_and_log(ubman, 'fdtget -t bx %s %s value' %
+ (fit, sig_node))
byte_list = sig.split()
byte = int(byte_list[0], 16)
byte_list[0] = '%x' % (byte + 1)
sig = ' '.join(byte_list)
- util.run_and_log(cons, 'fdtput -t bx %s %s value %s' %
- (fit, sig_node, sig))
+ utils.run_and_log(ubman, 'fdtput -t bx %s %s value %s' %
+ (fit, sig_node, sig))
run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash',
False)
- cons.log.action('%s: Check bad config on the host' % sha_algo)
- util.run_and_log_expect_exception(
- cons, [fit_check_sign, '-f', fit, '-k', dtb],
+ ubman.log.action('%s: Check bad config on the host' % sha_algo)
+ utils.run_and_log_expect_exception(
+ ubman, [fit_check_sign, '-f', fit, '-k', dtb],
1, 'Failed to verify required signature')
def test_required_key(sha_algo, padding, sign_options):
@@ -416,19 +416,19 @@
# Compile our device tree files for kernel and U-Boot. These are
# regenerated here since mkimage will modify them (by adding a
# public key) below.
- dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
- dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-kernel.dts', ubman, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
- cons.log.action('%s: Test FIT with configs images' % sha_algo)
+ ubman.log.action('%s: Test FIT with configs images' % sha_algo)
# Build the FIT with prod key (keys required) and sign it. This puts the
# signature into sandbox-u-boot.dtb, marked 'required'
- make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
sign_fit(sha_algo, sign_options)
# Build the FIT with dev key (keys NOT required). This adds the
# signature into sandbox-u-boot.dtb, NOT marked 'required'.
- make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
sign_fit_norequire(sha_algo, sign_options)
# So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
@@ -440,7 +440,7 @@
# Build the FIT with dev key (keys required) and sign it. This puts the
# signature into sandbox-u-boot.dtb, marked 'required'.
- make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
sign_fit(sha_algo, sign_options)
# Set the required-mode policy to "any".
@@ -449,8 +449,8 @@
# a dev signature only (sign_fit() overwrites the FIT).
# Try to boot the FIT with dev key. This FIT should be accepted by
# U-Boot because the dev key is required and policy is "any" required key.
- util.run_and_log(cons, 'fdtput -t s %s /signature required-mode any' %
- (dtb))
+ utils.run_and_log(ubman, 'fdtput -t s %s /signature required-mode any' %
+ dtb)
run_bootm(sha_algo, 'multi required key', 'dev+', True)
# Set the required-mode policy to "all".
@@ -459,8 +459,8 @@
# a dev signature only (sign_fit() overwrites the FIT).
# Try to boot the FIT with dev key. This FIT should not be accepted by
# U-Boot because the prod key is required and policy is "all" required key
- util.run_and_log(cons, 'fdtput -t s %s /signature required-mode all' %
- (dtb))
+ utils.run_and_log(ubman, 'fdtput -t s %s /signature required-mode all' %
+ dtb)
run_bootm(sha_algo, 'multi required key', '', False)
def test_global_sign(sha_algo, padding, sign_options):
@@ -473,22 +473,22 @@
"""
dtb = '%ssandbox-u-boot-global%s.dtb' % (tmpdir, padding)
- cons.config.dtb = dtb
+ ubman.config.dtb = dtb
# Compile our device tree files for kernel and U-Boot. These are
# regenerated here since mkimage will modify them (by adding a
# public key) below.
- dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-kernel.dts', ubman, dtc_args, datadir, tmpdir, dtb)
dtc_options('sandbox-u-boot-global%s.dts' % padding, '-p 1024')
# Build the FIT with dev key (keys NOT required). This adds the
# signature into sandbox-u-boot.dtb, NOT marked 'required'.
- make_fit('simple-images.its', cons, mkimage, dtc_args, datadir, fit)
+ make_fit('simple-images.its', ubman, mkimage, dtc_args, datadir, fit)
sign_fit_dtb(sha_algo, '', dtb)
# Build the dtb for binman that define the pre-load header
# with the global sigature.
- dtc('sandbox-binman%s.dts' % padding, cons, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-binman%s.dts' % padding, ubman, dtc_args, datadir, tmpdir, dtb)
# Run binman to create the final image with the not signed fit
# and the pre-load header that contains the global signature.
@@ -508,15 +508,14 @@
# Check that the boot fails if the global signature is not provided
run_bootm(sha_algo, 'global image signature', 'signature is mandatory', False)
- cons = u_boot_console
- tmpdir = os.path.join(cons.config.result_dir, name) + '/'
+ tmpdir = os.path.join(ubman.config.result_dir, name) + '/'
if not os.path.exists(tmpdir):
os.mkdir(tmpdir)
- datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+ datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
fit = '%stest.fit' % tmpdir
- mkimage = cons.config.build_dir + '/tools/mkimage'
- binman = cons.config.source_dir + '/tools/binman/binman'
- fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ binman = ubman.config.source_dir + '/tools/binman/binman'
+ fit_check_sign = ubman.config.build_dir + '/tools/fit_check_sign'
dtc_args = '-I dts -O dtb -i %s' % tmpdir
dtb = '%ssandbox-u-boot.dtb' % tmpdir
sig_node = '/configurations/conf-1/signature'
@@ -535,9 +534,9 @@
# We need to use our own device tree file. Remember to restore it
# afterwards.
- old_dtb = cons.config.dtb
+ old_dtb = ubman.config.dtb
try:
- cons.config.dtb = dtb
+ ubman.config.dtb = dtb
if global_sign:
test_global_sign(sha_algo, padding, sign_options)
elif required:
@@ -546,8 +545,8 @@
test_with_algo(sha_algo, padding, sign_options)
finally:
# Go back to the original U-Boot with the correct dtb.
- cons.config.dtb = old_dtb
- cons.restart_uboot()
+ ubman.config.dtb = old_dtb
+ ubman.restart_uboot()
TESTDATA_IN = [
@@ -577,7 +576,7 @@
@pytest.mark.requiredtool('dtc')
@pytest.mark.requiredtool('openssl')
@pytest.mark.parametrize("name,sha_algo,padding,sign_options,algo_arg", TESTDATA)
-def test_fdt_add_pubkey(u_boot_console, name, sha_algo, padding, sign_options, algo_arg):
+def test_fdt_add_pubkey(ubman, name, sha_algo, padding, sign_options, algo_arg):
"""Test fdt_add_pubkey utility with bunch of different algo options."""
def sign_fit(sha_algo, options):
@@ -593,8 +592,8 @@
args = [mkimage, '-F', '-k', tmpdir, fit]
if options:
args += options.split(' ')
- cons.log.action('%s: Sign images' % sha_algo)
- util.run_and_log(cons, args)
+ ubman.log.action('%s: Sign images' % sha_algo)
+ utils.run_and_log(ubman, args)
def test_add_pubkey(sha_algo, padding, sign_options):
"""Test fdt_add_pubkey utility with given hash algorithm and padding.
@@ -609,32 +608,33 @@
"""
# Create a fresh .dtb without the public keys
- dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+ dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
- cons.log.action('%s: Test fdt_add_pubkey with signed configuration' % sha_algo)
+ ubman.log.action('%s: Test fdt_add_pubkey with signed configuration' % sha_algo)
# Then add the dev key via the fdt_add_pubkey tool
- util.run_and_log(cons, [fdt_add_pubkey, '-a', '%s,%s' % ('sha256' if algo_arg else sha_algo, \
- 'rsa3072' if sha_algo == 'sha384' else 'rsa2048'),
- '-k', tmpdir, '-n', 'dev', '-r', 'conf', dtb])
+ utils.run_and_log(ubman,
+ [fdt_add_pubkey, '-a', '%s,%s' %
+ ('sha256' if algo_arg else sha_algo,
+ 'rsa3072' if sha_algo == 'sha384' else 'rsa2048'),
+ '-k', tmpdir, '-n', 'dev', '-r', 'conf', dtb])
- make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+ make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
# Sign images with our dev keys
sign_fit(sha_algo, sign_options)
# Check with fit_check_sign that FIT is signed with key
- util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
+ utils.run_and_log(ubman, [fit_check_sign, '-f', fit, '-k', dtb])
- cons = u_boot_console
- tmpdir = os.path.join(cons.config.result_dir, name) + '/'
+ tmpdir = os.path.join(ubman.config.result_dir, name) + '/'
if not os.path.exists(tmpdir):
os.mkdir(tmpdir)
- datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+ datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
fit = '%stest.fit' % tmpdir
- mkimage = cons.config.build_dir + '/tools/mkimage'
- binman = cons.config.source_dir + '/tools/binman/binman'
- fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
- fdt_add_pubkey = cons.config.build_dir + '/tools/fdt_add_pubkey'
+ mkimage = ubman.config.build_dir + '/tools/mkimage'
+ binman = ubman.config.source_dir + '/tools/binman/binman'
+ fit_check_sign = ubman.config.build_dir + '/tools/fit_check_sign'
+ fdt_add_pubkey = ubman.config.build_dir + '/tools/fdt_add_pubkey'
dtc_args = '-I dts -O dtb -i %s' % tmpdir
dtb = '%ssandbox-u-boot.dtb' % tmpdir
diff --git a/test/py/tests/test_vpl.py b/test/py/tests/test_vpl.py
index 8c472ca..a269c7c 100644
--- a/test/py/tests/test_vpl.py
+++ b/test/py/tests/test_vpl.py
@@ -5,7 +5,7 @@
import os.path
import pytest
-def test_vpl(u_boot_console, ut_vpl_subtest):
+def test_vpl(ubman, ut_vpl_subtest):
"""Execute a "ut" subtest.
The subtests are collected in function generate_ut_subtest() from linker
@@ -19,16 +19,15 @@
implemented in C function foo_test_bar().
Args:
- u_boot_console (ConsoleBase): U-Boot console
+ ubman (ConsoleBase): U-Boot console
ut_subtest (str): VPL test to be executed (e.g. 'dm platdata_phandle')
"""
try:
- cons = u_boot_console
- cons.restart_uboot_with_flags(['-u', '-k', ut_vpl_subtest.split()[1]])
- output = cons.get_spawn_output().replace('\r', '')
+ ubman.restart_uboot_with_flags(['-u', '-k', ut_vpl_subtest.split()[1]])
+ output = ubman.get_spawn_output().replace('\r', '')
assert 'failures: 0' in output
finally:
# Restart afterward in case a non-VPL test is run next. This should not
# happen since VPL tests are run in their own invocation of test.py, but
# the cost of doing this is not too great at present.
- u_boot_console.restart_uboot()
+ ubman.restart_uboot()
diff --git a/test/py/tests/test_xxd/test_xxd.py b/test/py/tests/test_xxd/test_xxd.py
index 06b9cfc..c04bf8b 100644
--- a/test/py/tests/test_xxd/test_xxd.py
+++ b/test/py/tests/test_xxd/test_xxd.py
@@ -7,14 +7,14 @@
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('cmd_xxd')
-def test_xxd(u_boot_console, xxd_data):
+def test_xxd(ubman, xxd_data):
""" Unit test for xxd
Args:
- u_boot_console -- U-Boot console
+ ubman -- U-Boot console
xxd_data -- Path to the disk image used for testing.
"""
- response = u_boot_console.run_command_list([
+ response = ubman.run_command_list([
f'host bind 0 {xxd_data}',
'xxd host 0 hello'])
diff --git a/test/py/tests/test_zynq_secure.py b/test/py/tests/test_zynq_secure.py
index 0ee5aeb..f066a03 100644
--- a/test/py/tests/test_zynq_secure.py
+++ b/test/py/tests/test_zynq_secure.py
@@ -3,7 +3,7 @@
import pytest
import re
-import u_boot_utils
+import utils
import test_net
"""
@@ -36,8 +36,8 @@
}
"""
-def zynq_secure_pre_commands(u_boot_console):
- output = u_boot_console.run_command('print modeboot')
+def zynq_secure_pre_commands(ubman):
+ output = ubman.run_command('print modeboot')
if not 'modeboot=' in output:
pytest.skip('bootmode cannnot be determined')
m = re.search('modeboot=(.+?)boot', output)
@@ -48,8 +48,8 @@
pytest.skip('skipping due to jtag bootmode')
@pytest.mark.buildconfigspec('cmd_zynq_aes')
-def test_zynq_aes_image(u_boot_console):
- f = u_boot_console.config.env.get('env__zynq_aes_readable_file', None)
+def test_zynq_aes_image(ubman):
+ f = ubman.config.env.get('env__zynq_aes_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynq secure aes case to read')
@@ -61,130 +61,130 @@
if not dstsize:
pytest.skip('No dstlen specified in env file to read')
- zynq_secure_pre_commands(u_boot_console)
- test_net.test_net_dhcp(u_boot_console)
+ zynq_secure_pre_commands(ubman)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
srcaddr = f.get('srcaddr', None)
if not srcaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['fn']
- output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
assert expected_tftp in output
expected_op = 'zynq aes [operation type] <srcaddr>'
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'zynq aes %x $filesize %x %x' % (srcaddr, dstaddr, dstsize)
)
assert expected_op not in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_zynq_aes')
-def test_zynq_aes_bitstream(u_boot_console):
- f = u_boot_console.config.env.get('env__zynq_aes_readable_file', None)
+def test_zynq_aes_bitstream(ubman):
+ f = ubman.config.env.get('env__zynq_aes_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynq secure aes case to read')
- zynq_secure_pre_commands(u_boot_console)
- test_net.test_net_dhcp(u_boot_console)
+ zynq_secure_pre_commands(ubman)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
srcaddr = f.get('srcaddr', None)
if not srcaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['fnbit']
- output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
assert expected_tftp in output
expected_op = 'zynq aes [operation type] <srcaddr>'
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'zynq aes load %x $filesize' % (srcaddr)
)
assert expected_op not in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_zynq_aes')
-def test_zynq_aes_partial_bitstream(u_boot_console):
- f = u_boot_console.config.env.get('env__zynq_aes_readable_file', None)
+def test_zynq_aes_partial_bitstream(ubman):
+ f = ubman.config.env.get('env__zynq_aes_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynq secure aes case to read')
- zynq_secure_pre_commands(u_boot_console)
- test_net.test_net_dhcp(u_boot_console)
+ zynq_secure_pre_commands(ubman)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
srcaddr = f.get('srcaddr', None)
if not srcaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['fnpbit']
- output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
assert expected_tftp in output
expected_op = 'zynq aes [operation type] <srcaddr>'
- output = u_boot_console.run_command('zynq aes loadp %x $filesize' % (srcaddr))
+ output = ubman.run_command('zynq aes loadp %x $filesize' % (srcaddr))
assert expected_op not in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_zynq_rsa')
-def test_zynq_rsa_image(u_boot_console):
- f = u_boot_console.config.env.get('env__zynq_rsa_readable_file', None)
+def test_zynq_rsa_image(ubman):
+ f = ubman.config.env.get('env__zynq_rsa_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynq secure rsa case to read')
- zynq_secure_pre_commands(u_boot_console)
- test_net.test_net_dhcp(u_boot_console)
+ zynq_secure_pre_commands(ubman)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
srcaddr = f.get('srcaddr', None)
if not srcaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['fn']
- output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
assert expected_tftp in output
expected_op = 'zynq rsa <baseaddr>'
- output = u_boot_console.run_command('zynq rsa %x ' % (srcaddr))
+ output = ubman.run_command('zynq rsa %x ' % (srcaddr))
assert expected_op not in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_zynq_rsa')
-def test_zynq_rsa_image_invalid(u_boot_console):
- f = u_boot_console.config.env.get('env__zynq_rsa_readable_file', None)
+def test_zynq_rsa_image_invalid(ubman):
+ f = ubman.config.env.get('env__zynq_rsa_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynq secure rsa case to read')
- zynq_secure_pre_commands(u_boot_console)
- test_net.test_net_dhcp(u_boot_console)
+ zynq_secure_pre_commands(ubman)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
srcaddr = f.get('srcaddr', None)
if not srcaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fninvalid = f['fninvalid']
- output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fninvalid))
+ output = ubman.run_command('tftpboot %x %s' % (srcaddr, fninvalid))
assert expected_tftp in output
expected_op = 'zynq rsa <baseaddr>'
- output = u_boot_console.run_command('zynq rsa %x ' % (srcaddr))
+ output = ubman.run_command('zynq rsa %x ' % (srcaddr))
assert expected_op in output
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert not output.endswith('0')
diff --git a/test/py/tests/test_zynqmp_rpu.py b/test/py/tests/test_zynqmp_rpu.py
index 22f687d..cda8c92 100644
--- a/test/py/tests/test_zynqmp_rpu.py
+++ b/test/py/tests/test_zynqmp_rpu.py
@@ -33,8 +33,8 @@
"""
# Get rpu apps params from env
-def get_rpu_apps_env(u_boot_console):
- rpu_apps = u_boot_console.config.env.get('env__zynqmp_rpu_apps', False)
+def get_rpu_apps_env(ubman):
+ rpu_apps = ubman.config.env.get('env__zynqmp_rpu_apps', False)
if not rpu_apps:
pytest.skip('ZynqMP RPU application info not defined!')
@@ -65,29 +65,29 @@
return apps, procs, cpu_nums, addrs, outputs, tftp_addrs
# Check return code
-def ret_code(u_boot_console):
- return u_boot_console.run_command('echo $?')
+def ret_code(ubman):
+ return ubman.run_command('echo $?')
# Initialize tcm
-def tcminit(u_boot_console, rpu_mode):
- output = u_boot_console.run_command(f'zynqmp tcminit {rpu_mode}')
+def tcminit(ubman, rpu_mode):
+ output = ubman.run_command(f'zynqmp tcminit {rpu_mode}')
assert 'Initializing TCM overwrites TCM content' in output
- return ret_code(u_boot_console)
+ return ret_code(ubman)
# Load application in DDR
-def load_app_ddr(u_boot_console, tftp_addr, app):
- output = u_boot_console.run_command('tftpboot %x %s' % (tftp_addr, app))
+def load_app_ddr(ubman, tftp_addr, app):
+ output = ubman.run_command('tftpboot %x %s' % (tftp_addr, app))
assert 'TIMEOUT' not in output
assert 'Bytes transferred = ' in output
# Load elf
- u_boot_console.run_command('bootelf -p %x' % tftp_addr)
- assert ret_code(u_boot_console).endswith('0')
+ ubman.run_command('bootelf -p %x' % tftp_addr)
+ assert ret_code(ubman).endswith('0')
# Disable cpus
-def disable_cpus(u_boot_console, cpu_nums):
+def disable_cpus(ubman, cpu_nums):
for num in cpu_nums:
- u_boot_console.run_command(f'cpu {num} disable')
+ ubman.run_command(f'cpu {num} disable')
# Get random RPU mode between string and integer
def get_rpu_mode(rpu_mode):
@@ -97,47 +97,47 @@
return random.choice(['split', 1])
# Load apps on RPU cores
-def rpu_apps_load(u_boot_console, rpu_mode):
+def rpu_apps_load(ubman, rpu_mode):
apps, procs, cpu_nums, addrs, outputs, tftp_addrs = get_rpu_apps_env(
- u_boot_console)
- test_net.test_net_dhcp(u_boot_console)
+ ubman)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
try:
- assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0')
+ assert tcminit(ubman, get_rpu_mode(rpu_mode)).endswith('0')
for i in range(len(apps)):
if rpu_mode == 'lockstep' and procs[i] != 'rpu0':
continue
- load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
+ load_app_ddr(ubman, tftp_addrs[i], apps[i])
rel_addr = hex(int(addrs[i] + 0x3C))
# Release cpu at app load address
cpu_num = cpu_nums[i]
cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
- output = u_boot_console.run_command(cmd)
+ output = ubman.run_command(cmd)
exp_op = f'Using TCM jump trampoline for address {rel_addr}'
assert exp_op in output
assert f'R5 {rpu_mode} mode' in output
- u_boot_console.wait_for(outputs[i])
- assert ret_code(u_boot_console).endswith('0')
+ ubman.wait_for(outputs[i])
+ assert ret_code(ubman).endswith('0')
finally:
- disable_cpus(u_boot_console, cpu_nums)
+ disable_cpus(ubman, cpu_nums)
@pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_rpu_app_load_split(u_boot_console):
- rpu_apps_load(u_boot_console, 'split')
+def test_zynqmp_rpu_app_load_split(ubman):
+ rpu_apps_load(ubman, 'split')
@pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_rpu_app_load_lockstep(u_boot_console):
- rpu_apps_load(u_boot_console, 'lockstep')
+def test_zynqmp_rpu_app_load_lockstep(ubman):
+ rpu_apps_load(ubman, 'lockstep')
@pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_rpu_app_load_negative(u_boot_console):
+def test_zynqmp_rpu_app_load_negative(ubman):
apps, procs, cpu_nums, addrs, outputs, tftp_addrs = get_rpu_apps_env(
- u_boot_console)
+ ubman)
# Invalid commands
rand_str = ''.join(random.choices(string.ascii_lowercase, k=4))
@@ -145,26 +145,26 @@
inv_modes = ['mode', rand_str, rand_num, 'splittt', 'locksteppp', '00', 11]
for mode in inv_modes:
- u_boot_console.run_command(f'zynqmp tcminit {mode}')
- assert ret_code(u_boot_console).endswith('1')
+ ubman.run_command(f'zynqmp tcminit {mode}')
+ assert ret_code(ubman).endswith('1')
- test_net.test_net_dhcp(u_boot_console)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
try:
rpu_mode = 'split'
- assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0')
+ assert tcminit(ubman, get_rpu_mode(rpu_mode)).endswith('0')
inv_modes += [0, 1]
for i in range(len(apps)):
- load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
+ load_app_ddr(ubman, tftp_addrs[i], apps[i])
# Run in split mode at different load address
rel_addr = hex(int(addrs[i]) + random.randint(200, 1000))
cpu_num = cpu_nums[i]
cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
- output = u_boot_console.run_command(cmd)
+ output = ubman.run_command(cmd)
exp_op = f'Using TCM jump trampoline for address {rel_addr}'
assert exp_op in output
assert f'R5 {rpu_mode} mode' in output
@@ -173,50 +173,50 @@
# Invalid rpu mode
for mode in inv_modes:
cmd = f'cpu {cpu_num} release {rel_addr} {mode}'
- output = u_boot_console.run_command(cmd)
+ output = ubman.run_command(cmd)
assert exp_op in output
assert f'Unsupported mode' in output
- assert not ret_code(u_boot_console).endswith('0')
+ assert not ret_code(ubman).endswith('0')
# Switch to lockstep mode, without disabling CPUs
rpu_mode = 'lockstep'
- output = u_boot_console.run_command(
+ output = ubman.run_command(
f'zynqmp tcminit {get_rpu_mode(rpu_mode)}'
)
assert 'ERROR: ' in output
# Disable cpus
- disable_cpus(u_boot_console, cpu_nums)
+ disable_cpus(ubman, cpu_nums)
# Switch to lockstep mode, after disabling CPUs
- output = u_boot_console.run_command(
+ output = ubman.run_command(
f'zynqmp tcminit {get_rpu_mode(rpu_mode)}'
)
assert 'Initializing TCM overwrites TCM content' in output
- assert ret_code(u_boot_console).endswith('0')
+ assert ret_code(ubman).endswith('0')
# Run lockstep mode for RPU1/RPU0
for i in range(len(apps)):
- load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
+ load_app_ddr(ubman, tftp_addrs[i], apps[i])
rel_addr = hex(int(addrs[i] + 0x3C))
cpu_num = cpu_nums[i]
cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
- output = u_boot_console.run_command(cmd)
+ output = ubman.run_command(cmd)
exp_op = f'Using TCM jump trampoline for address {rel_addr}'
assert exp_op in output
if procs[i] == 'rpu1':
assert 'Lockstep mode should run on ZYNQMP_CORE_RPU0' in output
- assert not ret_code(u_boot_console).endswith('0')
+ assert not ret_code(ubman).endswith('0')
elif procs[i] == 'rpu0':
assert f'R5 {rpu_mode} mode' in output
- u_boot_console.wait_for(outputs[i])
- assert ret_code(u_boot_console).endswith('0')
+ ubman.wait_for(outputs[i])
+ assert ret_code(ubman).endswith('0')
else:
assert False, 'ERROR: Invalid processor!'
finally:
- disable_cpus(u_boot_console, cpu_nums)
+ disable_cpus(ubman, cpu_nums)
# This forces the console object to be shutdown, so any subsequent test
# will reset the board back into U-Boot.
- u_boot_console.drain_console()
- u_boot_console.cleanup_spawn()
+ ubman.drain_console()
+ ubman.cleanup_spawn()
diff --git a/test/py/tests/test_zynqmp_secure.py b/test/py/tests/test_zynqmp_secure.py
index 570bd24..c057e36 100644
--- a/test/py/tests/test_zynqmp_secure.py
+++ b/test/py/tests/test_zynqmp_secure.py
@@ -3,7 +3,7 @@
import pytest
import re
-import u_boot_utils
+import utils
import test_net
"""
@@ -30,75 +30,75 @@
"""
@pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_secure_boot_image(u_boot_console):
+def test_zynqmp_secure_boot_image(ubman):
"""This test verifies secure boot image at the DDR address for
authentication only case.
"""
- f = u_boot_console.config.env.get('env__zynqmp_secure_readable_file', None)
+ f = ubman.config.env.get('env__zynqmp_secure_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynqmp secure cases to read')
- test_net.test_net_dhcp(u_boot_console)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['fn']
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (addr, fn))
assert expected_tftp in output
- output = u_boot_console.run_command('zynqmp secure %x $filesize' % (addr))
+ output = ubman.run_command('zynqmp secure %x $filesize' % (addr))
assert 'Verified image at' in output
ver_addr = re.search(r'Verified image at 0x(.+)', output).group(1)
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- output = u_boot_console.run_command('print zynqmp_verified_img_addr')
+ output = ubman.run_command('print zynqmp_verified_img_addr')
assert f'zynqmp_verified_img_addr={ver_addr}' in output
assert 'Error' not in output
@pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_secure_boot_img_kup(u_boot_console):
+def test_zynqmp_secure_boot_img_kup(ubman):
"""This test verifies secure boot image at the DDR address for encryption
with kup key case.
"""
- f = u_boot_console.config.env.get('env__zynqmp_secure_readable_file', None)
+ f = ubman.config.env.get('env__zynqmp_secure_readable_file', None)
if not f:
pytest.skip('No TFTP readable file for zynqmp secure cases to read')
- test_net.test_net_dhcp(u_boot_console)
+ test_net.test_net_dhcp(ubman)
if not test_net.net_set_up:
- test_net.test_net_setup_static(u_boot_console)
+ test_net.test_net_setup_static(ubman)
keyaddr = f.get('keyaddr', None)
if not keyaddr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
keyfn = f['keyfn']
- output = u_boot_console.run_command('tftpboot %x %s' % (keyaddr, keyfn))
+ output = ubman.run_command('tftpboot %x %s' % (keyaddr, keyfn))
assert expected_tftp in output
addr = f.get('addr', None)
if not addr:
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = utils.find_ram_base(ubman)
expected_tftp = 'Bytes transferred = '
fn = f['enckupfn']
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ output = ubman.run_command('tftpboot %x %s' % (addr, fn))
assert expected_tftp in output
- output = u_boot_console.run_command(
+ output = ubman.run_command(
'zynqmp secure %x $filesize %x' % (addr, keyaddr)
)
assert 'Verified image at' in output
ver_addr = re.search(r'Verified image at 0x(.+)', output).group(1)
- output = u_boot_console.run_command('echo $?')
+ output = ubman.run_command('echo $?')
assert output.endswith('0')
- output = u_boot_console.run_command('print zynqmp_verified_img_addr')
+ output = ubman.run_command('print zynqmp_verified_img_addr')
assert f'zynqmp_verified_img_addr={ver_addr}' in output
assert 'Error' not in output
diff --git a/test/py/u_boot_utils.py b/test/py/utils.py
similarity index 88%
rename from test/py/u_boot_utils.py
rename to test/py/utils.py
index 9e161fb..ca80e4b 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/utils.py
@@ -55,7 +55,7 @@
"""Generate and store information about a persistent file containing
random data."""
- def __init__(self, u_boot_console, fn, size):
+ def __init__(self, ubman, fn, size):
"""Create or process the persistent file.
If the file does not exist, it is generated.
@@ -66,7 +66,7 @@
the current test run.
Args:
- u_boot_console: A console connection to U-Boot.
+ ubman: A console connection to U-Boot.
fn: The filename (without path) to create.
size: The desired size of the file in bytes.
@@ -76,14 +76,14 @@
self.fn = fn
- self.abs_fn = u_boot_console.config.persistent_data_dir + '/' + fn
+ self.abs_fn = ubman.config.persistent_data_dir + '/' + fn
if os.path.exists(self.abs_fn):
- u_boot_console.log.action('Persistent data file ' + self.abs_fn +
+ ubman.log.action('Persistent data file ' + self.abs_fn +
' already exists')
self.content_hash = md5sum_file(self.abs_fn)
else:
- u_boot_console.log.action('Generating ' + self.abs_fn +
+ ubman.log.action('Generating ' + self.abs_fn +
' (random, persistent, %d bytes)' % size)
data = os.urandom(size)
with open(self.abs_fn, 'wb') as fh:
@@ -157,11 +157,11 @@
return
raise Exception('File can still be opened')
-def run_and_log(u_boot_console, cmd, ignore_errors=False, stdin=None, env=None):
+def run_and_log(ubman, cmd, ignore_errors=False, stdin=None, env=None):
"""Run a command and log its output.
Args:
- u_boot_console: A console connection to U-Boot.
+ ubman: A console connection to U-Boot.
cmd: The command to run, as an array of argv[], or a string.
If a string, note that it is split up so that quoted spaces
will not be preserved. E.g. "fred and" becomes ['"fred', 'and"']
@@ -177,25 +177,25 @@
"""
if isinstance(cmd, str):
cmd = cmd.split()
- runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
+ runner = ubman.log.get_runner(cmd[0], sys.stdout)
output = runner.run(cmd, ignore_errors=ignore_errors, stdin=stdin, env=env)
runner.close()
return output
-def run_and_log_expect_exception(u_boot_console, cmd, retcode, msg):
+def run_and_log_expect_exception(ubman, cmd, retcode, msg):
"""Run a command that is expected to fail.
This runs a command and checks that it fails with the expected return code
and exception method. If not, an exception is raised.
Args:
- u_boot_console: A console connection to U-Boot.
+ ubman: A console connection to U-Boot.
cmd: The command to run, as an array of argv[].
retcode: Expected non-zero return code from the command.
msg: String that should be contained within the command's output.
"""
try:
- runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
+ runner = ubman.log.get_runner(cmd[0], sys.stdout)
runner.run(cmd)
except Exception:
assert retcode == runner.exit_status
@@ -207,7 +207,7 @@
runner.close()
ram_base = None
-def find_ram_base(u_boot_console):
+def find_ram_base(ubman):
"""Find the running U-Boot's RAM location.
Probe the running U-Boot to determine the address of the first bank
@@ -218,22 +218,22 @@
actively read once.
Args:
- u_boot_console: A console connection to U-Boot.
+ ubman: A console connection to U-Boot.
Returns:
The address of U-Boot's first RAM bank, as an integer.
"""
global ram_base
- if u_boot_console.config.buildconfig.get('config_cmd_bdi', 'n') != 'y':
+ if ubman.config.buildconfig.get('config_cmd_bdi', 'n') != 'y':
pytest.skip('bdinfo command not supported')
if ram_base == -1:
pytest.skip('Previously failed to find RAM bank start')
if ram_base is not None:
return ram_base
- with u_boot_console.log.section('find_ram_base'):
- response = u_boot_console.run_command('bdinfo')
+ with ubman.log.section('find_ram_base'):
+ response = ubman.run_command('bdinfo')
for l in response.split('\n'):
if '-> start' in l or 'memstart =' in l:
ram_base = int(l.split('=')[1].strip(), 16)
@@ -311,11 +311,11 @@
statement
Usage:
- with persistent_file_helper(u_boot_console.log, filename):
+ with persistent_file_helper(ubman.log, filename):
code to generate the file, if it's missing.
Args:
- u_boot_log: u_boot_console.log.
+ u_boot_log: ubman.log.
filename: The filename of the generated file.
Returns:
@@ -324,11 +324,11 @@
return PersistentFileHelperCtxMgr(u_boot_log, filename)
-def crc32(u_boot_console, address, count):
+def crc32(ubman, address, count):
"""Helper function used to compute the CRC32 value of a section of RAM.
Args:
- u_boot_console: A U-Boot console connection.
+ ubman: A U-Boot console connection.
address: Address where data starts.
count: Amount of data to use for calculation.
@@ -336,10 +336,10 @@
CRC32 value
"""
- bcfg = u_boot_console.config.buildconfig
+ bcfg = ubman.config.buildconfig
has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
assert has_cmd_crc32, 'Cannot compute crc32 without CONFIG_CMD_CRC32.'
- output = u_boot_console.run_command('crc32 %08x %x' % (address, count))
+ output = ubman.run_command('crc32 %08x %x' % (address, count))
m = re.search('==> ([0-9a-fA-F]{8})$', output)
assert m, 'CRC32 operation failed.'
diff --git a/tools/qconfig.py b/tools/qconfig.py
index 259adbe..c96a305 100755
--- a/tools/qconfig.py
+++ b/tools/qconfig.py
@@ -1453,7 +1453,7 @@
print('\nCONFIG options used as Proper in Makefiles but without a non-xPL_ variant:')
not_found = check_not_found(all_uses, MODE_PROPER)
show_uses(not_found)
- proper_not_found |= {not_found.keys()}
+ proper_not_found |= not_found.keys()
# Scan the source code
all_uses, _ = scan_src_files(src_list)
@@ -1471,7 +1471,7 @@
print('\nCONFIG options used as Proper in source but without a non-xPL_ variant:')
not_found = check_not_found(all_uses, MODE_PROPER)
show_uses(not_found)
- proper_not_found |= {not_found.keys()}
+ proper_not_found |= not_found.keys()
print('\nCONFIG options used as SPL but without an xPL_ variant:')
for item in sorted(spl_not_found):
diff --git a/tools/sfspl.c b/tools/sfspl.c
index c76420c..516e96e 100644
--- a/tools/sfspl.c
+++ b/tools/sfspl.c
@@ -70,11 +70,14 @@
printf("Truncated file\n");
return EXIT_FAILURE;
}
+ if ((size_t)size > hdr_size + file_size)
+ printf("File too long, expected %u bytes\n",
+ hdr_size + file_size);
if (hdr->version != DEFAULT_VERSION) {
printf("Unknown file format version\n");
return EXIT_FAILURE;
}
- crc_check = crc32(0, &buf[hdr_size], size - hdr_size);
+ crc_check = crc32(0, &buf[hdr_size], file_size);
if (crc_check != crc) {
printf("Incorrect CRC32\n");
return EXIT_FAILURE;