// SPDX-License-Identifier: (GPL-2.0+ OR MIT) | |
/* | |
* Copyright (C) 2022 Marek Vasut <marex@denx.de> | |
*/ | |
#include "imx8mp-u-boot.dtsi" | |
/ { | |
aliases { | |
eeprom0 = &eeprom0; | |
eeprom1 = &eeprom1; | |
mmc0 = &usdhc2; /* MicroSD */ | |
mmc1 = &usdhc3; /* eMMC */ | |
mmc2 = &usdhc1; /* SDIO */ | |
}; | |
config { | |
dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>; | |
}; | |
wdt-reboot { | |
compatible = "wdt-reboot"; | |
wdt = <&wdog1>; | |
u-boot,dm-spl; | |
}; | |
}; | |
&buck4 { | |
u-boot,dm-spl; | |
}; | |
&buck5 { | |
u-boot,dm-spl; | |
}; | |
&eqos { | |
/delete-property/ assigned-clocks; | |
/delete-property/ assigned-clock-parents; | |
/delete-property/ assigned-clock-rates; | |
}; | |
&gpio1 { | |
u-boot,dm-spl; | |
}; | |
&gpio2 { | |
u-boot,dm-spl; | |
}; | |
&gpio3 { | |
u-boot,dm-spl; | |
}; | |
&gpio4 { | |
u-boot,dm-spl; | |
}; | |
&gpio5 { | |
u-boot,dm-spl; | |
}; | |
&i2c3 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_i2c3 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_i2c3_gpio { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_pmic { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_uart1 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc2 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc2_100mhz { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc2_200mhz { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc2_vmmc { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc3 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc3_100mhz { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc3_100mhz { | |
u-boot,dm-spl; | |
}; | |
&pmic { | |
u-boot,dm-spl; | |
regulators { | |
u-boot,dm-spl; | |
}; | |
}; | |
®_usdhc2_vmmc { | |
u-boot,dm-spl; | |
}; | |
&uart1 { | |
u-boot,dm-spl; | |
}; | |
/* SDIO WiFi */ | |
&usdhc1 { | |
status = "disabled"; | |
}; | |
&usdhc2 { | |
u-boot,dm-spl; | |
}; | |
&usdhc3 { | |
u-boot,dm-spl; | |
}; | |
&wdog1 { | |
u-boot,dm-spl; | |
}; |