nds32: ftmac100 support cache enable.
Enable cache and ftmac100 performance can be improved.
Signed-off-by: rick <rick@andestech.com>
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index f9f9999..0d98d03 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -119,18 +119,45 @@
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
/*
- * MMU_CTL NTC0 Cacheable/Write-Back
+ * MMU_CTL NTC0 Non-cacheable
*/
+ li $r0, ~0x6
+ mfsr $r1, $mr0
+ and $r1, $r1, $r0
+ mtsr $r1, $mr0
+
li $r0, ~0x3
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+/*
+ * MMU_CTL NTC0 Cacheable/Write-Back
+ */
li $r0, 0x4
mfsr $r1, $mr0
or $r1, $r1, $r0
mtsr $r1, $mr0
#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+/*
+ * MMU_CTL NTC1 Non-cacheable
+ */
+ li $r0, ~0x18
+ mfsr $r1, $mr0
+ and $r1, $r1, $r0
+ mtsr $r1, $mr0
+/*
+ * MMU_CTL NTM1 mapping for partition 0
+ */
+ li $r0, ~0x6000
+ mfsr $r1, $mr0
+ and $r1, $r1, $r0
+ mtsr $r1, $mr0
+#endif
+#endif
#if !defined(CONFIG_SYS_ICACHE_OFF)
li $r0, 0x1
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
index b2c4d0e..e8ee961 100644
--- a/arch/nds32/include/asm/io.h
+++ b/arch/nds32/include/asm/io.h
@@ -48,6 +48,27 @@
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ if(paddr <PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
+ paddr = paddr | 0x40000000;
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline void *unmap_sysmem(const void *vaddr)
+{
+ phys_addr_t paddr = (phys_addr_t)vaddr;
+ paddr = paddr & ~0x40000000;
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+ return (phys_addr_t)(uintptr_t)ptr;
+}
+#endif
+
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{