src/arm64/ti/k3-j722s.dtsi - filogic/uboot - Gitiles

 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 /*
  * Device Tree Source for J722S SoC Family
  *
  * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
  */

 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/ti,sci_pm_domain.h>

 #include "k3-pinctrl.h"

 / {
 	model = "Texas Instruments K3 J722S SoC";
 	compatible = "ti,j722s";
 	interrupt-parent = <&gic500>;
 	#address-cells = <2>;
 	#size-cells = <2>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu-map {
 			cluster0: cluster0 {
 				core0 {
 					cpu = <&cpu0>;
 				};

 				core1 {
 					cpu = <&cpu1>;
 				};

 				core2 {
 					cpu = <&cpu2>;
 				};

 				core3 {
 					cpu = <&cpu3>;
 				};
 			};
 		};

 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			reg = <0x000>;
 			device_type = "cpu";
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
 			clocks = <&k3_clks 135 0>;
 		};

 		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			reg = <0x001>;
 			device_type = "cpu";
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
 			clocks = <&k3_clks 136 0>;
 		};

 		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			reg = <0x002>;
 			device_type = "cpu";
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
 			clocks = <&k3_clks 137 0>;
 		};

 		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			reg = <0x003>;
 			device_type = "cpu";
 			enable-method = "psci";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <64>;
 			i-cache-sets = <256>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <64>;
 			d-cache-sets = <128>;
 			next-level-cache = <&l2_0>;
 			clocks = <&k3_clks 138 0>;
 		};
 	};

 	l2_0: l2-cache0 {
 		compatible = "cache";
 		cache-unified;
 		cache-level = <2>;
 		cache-size = <0x80000>;
 		cache-line-size = <64>;
 		cache-sets = <512>;
 	};

 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
 			method = "smc";
 		};

 		psci: psci {
 			compatible = "arm,psci-1.0";
 			method = "smc";
 		};
 	};

 	a53_timer0: timer-cl0-cpu0 {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
 			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
 	};

 	pmu: pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 	};

 	cbass_main: bus@f0000 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;

 		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
 			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
 			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
 			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
 			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
 			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
 			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
 			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */
 			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
 			 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
 			 <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
 			 <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
 			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
 			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
 			 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
 			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
 			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
 			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
 			 <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */
 			 <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
 			 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
 			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
 			 <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
 			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
 			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
 			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
 			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
 			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
 			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
 			 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */
 			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */
 			 <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */
 			 <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */
 			 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */
 			 <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */
 			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
 			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
 			 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */

 			 /* MCU Domain Range */
 			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
 			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
 			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
 			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
 			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,

 			 /* Wakeup Domain Range */
 			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
 			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
 			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
 			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
 			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;

 		cbass_mcu: bus@4000000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
 				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
 				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
 				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
 				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
 			bootph-all;
 		};

 		cbass_wakeup: bus@b00000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
 				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
 				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
 				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
 				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
 			bootph-all;
 		};
 	};

 	#include "k3-am62p-j722s-common-thermal.dtsi"
 };

 /* Include peripherals shared with AM62P */
 #include "k3-am62p-j722s-common-main.dtsi"
 #include "k3-am62p-j722s-common-mcu.dtsi"
 #include "k3-am62p-j722s-common-wakeup.dtsi"

 /* Include J722S specific peripherals */
 #include "k3-j722s-main.dtsi"
	// SPDX-License-Identifier: GPL-2.0-only OR MIT
	/*
	* Device Tree Source for J722S SoC Family
	*
	* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/soc/ti,sci_pm_domain.h>

	#include "k3-pinctrl.h"

	/ {
	model = "Texas Instruments K3 J722S SoC";
	compatible = "ti,j722s";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu-map {
	cluster0: cluster0 {
	core0 {
	cpu = <&cpu0>;
	};

	core1 {
	cpu = <&cpu1>;
	};

	core2 {
	cpu = <&cpu2>;
	};

	core3 {
	cpu = <&cpu3>;
	};
	};
	};

	cpu0: cpu@0 {
	compatible = "arm,cortex-a53";
	reg = <0x000>;
	device_type = "cpu";
	enable-method = "psci";
	i-cache-size = <0x8000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	next-level-cache = <&l2_0>;
	clocks = <&k3_clks 135 0>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a53";
	reg = <0x001>;
	device_type = "cpu";
	enable-method = "psci";
	i-cache-size = <0x8000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	next-level-cache = <&l2_0>;
	clocks = <&k3_clks 136 0>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a53";
	reg = <0x002>;
	device_type = "cpu";
	enable-method = "psci";
	i-cache-size = <0x8000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	next-level-cache = <&l2_0>;
	clocks = <&k3_clks 137 0>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a53";
	reg = <0x003>;
	device_type = "cpu";
	enable-method = "psci";
	i-cache-size = <0x8000>;
	i-cache-line-size = <64>;
	i-cache-sets = <256>;
	d-cache-size = <0x8000>;
	d-cache-line-size = <64>;
	d-cache-sets = <128>;
	next-level-cache = <&l2_0>;
	clocks = <&k3_clks 138 0>;
	};
	};

	l2_0: l2-cache0 {
	compatible = "cache";
	cache-unified;
	cache-level = <2>;
	cache-size = <0x80000>;
	cache-line-size = <64>;
	cache-sets = <512>;
	};

	firmware {
	optee {
	compatible = "linaro,optee-tz";
	method = "smc";
	};

	psci: psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};
	};

	a53_timer0: timer-cl0-cpu0 {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: bus@f0000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;

	ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
	<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
	<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
	<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
	<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
	<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
	<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
	<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
	<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */
	<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
	<0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
	<0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
	<0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
	<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
	<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
	<0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
	<0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
	<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
	<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
	<0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */
	<0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
	<0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
	<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
	<0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
	<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
	<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
	<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
	<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
	<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
	<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
	<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */
	<0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */
	<0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */
	<0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */
	<0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */
	<0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */
	<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
	<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
	<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */

	/* MCU Domain Range */
	<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
	<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
	<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
	<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
	<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,

	/* Wakeup Domain Range */
	<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
	<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
	<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
	<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
	<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;

	cbass_mcu: bus@4000000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
	<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
	<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
	<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
	<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
	bootph-all;
	};

	cbass_wakeup: bus@b00000 {
	compatible = "simple-bus";
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
	<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
	<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
	<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
	<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
	bootph-all;
	};
	};

	#include "k3-am62p-j722s-common-thermal.dtsi"
	};

	/* Include peripherals shared with AM62P */
	#include "k3-am62p-j722s-common-main.dtsi"
	#include "k3-am62p-j722s-common-mcu.dtsi"
	#include "k3-am62p-j722s-common-wakeup.dtsi"

	/* Include J722S specific peripherals */
	#include "k3-j722s-main.dtsi"