src/arm64/amd/amd-seattle-cpus.dtsi

// SPDX-License-Identifier: GPL-2.0

/ {
	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};
				core1 {
					cpu = <&CPU3>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&CPU6>;
				};
				core1 {
					cpu = <&CPU7>;
				};
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_0>;

		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x1>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x100>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_1>;
		};

		CPU3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x101>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_1>;
		};

		CPU4: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x200>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_2>;
		};

		CPU5: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x201>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_2>;
		};

		CPU6: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x300>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_3>;
		};

		CPU7: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x301>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_3>;
		};
	};

	L2_0: l2-cache0 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L2_1: l2-cache1 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L2_2: l2-cache2 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L2_3: l2-cache3 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L3: l3-cache {
		cache-level = <3>;
		cache-size = <0x800000>;
		cache-line-size = <64>;
		cache-sets = <8192>;
		cache-unified;
	};

	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <0x0 0x7 0x4>,
			     <0x0 0x8 0x4>,
			     <0x0 0x9 0x4>,
			     <0x0 0xa 0x4>,
			     <0x0 0xb 0x4>,
			     <0x0 0xc 0x4>,
			     <0x0 0xd 0x4>,
			     <0x0 0xe 0x4>;
		interrupt-affinity = <&CPU0>,
				     <&CPU1>,
				     <&CPU2>,
				     <&CPU3>,
				     <&CPU4>,
				     <&CPU5>,
				     <&CPU6>,
				     <&CPU7>;
	};
};