global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 8f72ef5..d21d82f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -132,11 +132,11 @@
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+ cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+ pin, prn, strmhz(buf, CFG_SYS_CLK));
return 0;
}
@@ -284,7 +284,7 @@
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -370,7 +370,7 @@
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -394,7 +394,7 @@
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 9d4a10f..99eb61f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -36,31 +36,31 @@
{
fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
@@ -214,9 +214,9 @@
init_fbcs();
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG =
- CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG =
+ CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
@@ -335,21 +335,21 @@
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+ sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
- out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+ out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
+ out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
/* Setup Ports: */
- out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
- out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
- out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
- out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
- out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
- out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
- out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+ out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
+ out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
+ out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
+ out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
+ out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
+ out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
+ out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
/* Memory Controller: */
out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
@@ -472,8 +472,8 @@
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@@ -560,8 +560,8 @@
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
- MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
- MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+ MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@@ -573,17 +573,17 @@
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CONFIG_SYS_PJPAR
- MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#ifdef CFG_SYS_PJPAR
+ MCFGPIO_PJPAR = CFG_SYS_PJPAR;
#endif
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CONFIG_SYS_PASPAR
- MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#ifdef CFG_SYS_PASPAR
+ MCFGPIO_PASPAR = CFG_SYS_PASPAR;
#endif
-#ifdef CONFIG_SYS_PEHLPAR
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#ifdef CFG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
#endif
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
@@ -600,15 +600,15 @@
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-#ifdef CONFIG_SYS_PUAPAR
- MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#ifdef CFG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
#endif
#if defined(CONFIG_SYS_DDRD)
MCFGPIO_DDRD = CONFIG_SYS_DDRD;
#endif
-#ifdef CONFIG_SYS_DDRUA
- MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#ifdef CFG_SYS_DDRUA
+ MCFGPIO_DDRUA = CFG_SYS_DDRUA;
#endif
/* FlexBus Chipselect */
@@ -652,10 +652,10 @@
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
}
return 0;
}
@@ -678,12 +678,12 @@
* which is their primary function.
* ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c
index 045908a..6c76282 100644
--- a/arch/m68k/cpu/mcf52x2/speed.c
+++ b/arch/m68k/cpu/mcf52x2/speed.c
@@ -23,19 +23,19 @@
#if defined(CONFIG_M5208)
pll_t *pll = (pll_t *) MMAP_PLL;
- out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
- out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+ out_8(&pll->odr, CFG_SYS_PLL_ODR);
+ out_8(&pll->fdr, CFG_SYS_PLL_FDR);
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef CONFIG_SYS_PLL_BYPASS
+#ifndef CFG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@ -43,7 +43,7 @@
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = CONFIG_SYS_PLLCR;
+ pllcr = CFG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -52,7 +52,7 @@
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
+#endif /* #ifndef CFG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -68,7 +68,7 @@
;
#endif
- gd->cpu_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CLK;
#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 6dddbe7..d48d019 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -35,7 +35,7 @@
*/
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
@@ -81,9 +81,9 @@
.text
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(CFG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@@ -100,53 +100,53 @@
#if defined(CONFIG_M5208)
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
+#ifdef CFG_SYS_MBAR2
/* Get MBAR2 address */
- move.l #(CONFIG_SYS_MBAR2 + 1), %d0
+ move.l #(CFG_SYS_MBAR2 + 1), %d0
/* Set MBAR2 */
movec %d0, #0xc0e
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
/*
* Setup code in SRAM to initialize FLASHBAR,
* if start from internal Flash
*/
- move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
- move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
+ move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
+ move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
- jmp CONFIG_SYS_INIT_RAM_ADDR
+ jmp CFG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@@ -154,9 +154,9 @@
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
#endif
#endif
@@ -165,22 +165,22 @@
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
- move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
+ move.l #CFG_SYS_INT_FLASH_BASE, %d0
#else
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@@ -195,7 +195,7 @@
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,