global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index e44656d..6d87908 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -92,7 +92,7 @@
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
out_be16(&wdp->mr, wdog_module);
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 87effa7..10be738 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -47,36 +47,36 @@
out_be16(&wdog->cr, 0);
#endif
- out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+ out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+ out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
- out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
- out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
- out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -108,8 +108,8 @@
#endif
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
icache_enable();
diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c
index f41f977..6b08a12 100644
--- a/arch/m68k/cpu/mcf523x/speed.c
+++ b/arch/m68k/cpu/mcf523x/speed.c
@@ -29,7 +29,7 @@
while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
;
- gd->bus_clk = CONFIG_SYS_CLK;
+ gd->bus_clk = CFG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 4c9c96d..d2a21c3 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -91,10 +91,10 @@
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -116,7 +116,7 @@
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 8f72ef5..d21d82f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -132,11 +132,11 @@
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+ cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+ pin, prn, strmhz(buf, CFG_SYS_CLK));
return 0;
}
@@ -284,7 +284,7 @@
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -370,7 +370,7 @@
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -394,7 +394,7 @@
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 9d4a10f..99eb61f 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -36,31 +36,31 @@
{
fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
@@ -214,9 +214,9 @@
init_fbcs();
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG =
- CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG =
+ CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
@@ -335,21 +335,21 @@
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+ sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
- out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+ out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
+ out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
/* Setup Ports: */
- out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
- out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
- out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
- out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
- out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
- out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
- out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+ out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
+ out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
+ out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
+ out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
+ out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
+ out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
+ out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
/* Memory Controller: */
out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
@@ -472,8 +472,8 @@
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@@ -560,8 +560,8 @@
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
- MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
- MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+ MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@@ -573,17 +573,17 @@
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CONFIG_SYS_PJPAR
- MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#ifdef CFG_SYS_PJPAR
+ MCFGPIO_PJPAR = CFG_SYS_PJPAR;
#endif
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CONFIG_SYS_PASPAR
- MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#ifdef CFG_SYS_PASPAR
+ MCFGPIO_PASPAR = CFG_SYS_PASPAR;
#endif
-#ifdef CONFIG_SYS_PEHLPAR
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#ifdef CFG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
#endif
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
@@ -600,15 +600,15 @@
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-#ifdef CONFIG_SYS_PUAPAR
- MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#ifdef CFG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
#endif
#if defined(CONFIG_SYS_DDRD)
MCFGPIO_DDRD = CONFIG_SYS_DDRD;
#endif
-#ifdef CONFIG_SYS_DDRUA
- MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#ifdef CFG_SYS_DDRUA
+ MCFGPIO_DDRUA = CFG_SYS_DDRUA;
#endif
/* FlexBus Chipselect */
@@ -652,10 +652,10 @@
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
}
return 0;
}
@@ -678,12 +678,12 @@
* which is their primary function.
* ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c
index 045908a..6c76282 100644
--- a/arch/m68k/cpu/mcf52x2/speed.c
+++ b/arch/m68k/cpu/mcf52x2/speed.c
@@ -23,19 +23,19 @@
#if defined(CONFIG_M5208)
pll_t *pll = (pll_t *) MMAP_PLL;
- out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
- out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+ out_8(&pll->odr, CFG_SYS_PLL_ODR);
+ out_8(&pll->fdr, CFG_SYS_PLL_FDR);
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef CONFIG_SYS_PLL_BYPASS
+#ifndef CFG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@ -43,7 +43,7 @@
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = CONFIG_SYS_PLLCR;
+ pllcr = CFG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -52,7 +52,7 @@
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
+#endif /* #ifndef CFG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -68,7 +68,7 @@
;
#endif
- gd->cpu_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CLK;
#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 6dddbe7..d48d019 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -35,7 +35,7 @@
*/
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
@@ -81,9 +81,9 @@
.text
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(CFG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@@ -100,53 +100,53 @@
#if defined(CONFIG_M5208)
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
+#ifdef CFG_SYS_MBAR2
/* Get MBAR2 address */
- move.l #(CONFIG_SYS_MBAR2 + 1), %d0
+ move.l #(CFG_SYS_MBAR2 + 1), %d0
/* Set MBAR2 */
movec %d0, #0xc0e
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
/*
* Setup code in SRAM to initialize FLASHBAR,
* if start from internal Flash
*/
- move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
- move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
+ move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
+ move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
- jmp CONFIG_SYS_INIT_RAM_ADDR
+ jmp CFG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@@ -154,9 +154,9 @@
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
#endif
#endif
@@ -165,22 +165,22 @@
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
- move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
+ move.l #CFG_SYS_INT_FLASH_BASE, %d0
#else
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@@ -195,7 +195,7 @@
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
index 0659bf6..53a25d8 100644
--- a/arch/m68k/cpu/mcf530x/cpu.c
+++ b/arch/m68k/cpu/mcf530x/cpu.c
@@ -33,7 +33,7 @@
char buf[32];
printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CPU_CLK));
+ strmhz(buf, CFG_SYS_CPU_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index 8352940..dad47d8 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -40,35 +40,35 @@
{
csm_t *csm = (csm_t *)(MMAP_CSM);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
- defined(CONFIG_SYS_CS0_CTRL))
- out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
- out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \
+ defined(CFG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CFG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
- defined(CONFIG_SYS_CS1_CTRL))
- out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
- out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \
+ defined(CFG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CFG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
- defined(CONFIG_SYS_CS2_CTRL))
- out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
- out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \
+ defined(CFG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CFG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
- defined(CONFIG_SYS_CS3_CTRL))
- out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
- out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \
+ defined(CFG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CFG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
defined(CONFIG_SYS_CS4_CTRL))
diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
index 03d9abe..c8d0790 100644
--- a/arch/m68k/cpu/mcf530x/speed.c
+++ b/arch/m68k/cpu/mcf530x/speed.c
@@ -16,8 +16,8 @@
int get_clocks(void)
{
#if defined(CONFIG_M5307)
- gd->bus_clk = CONFIG_SYS_CLK;
- gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+ gd->bus_clk = CFG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CPU_CLK;
#endif
return 0;
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index 644c372..dbe2b54 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -39,7 +39,7 @@
/* Flash offset is 0 until we setup CS0 */
.long 0x00000000
#if defined(CONFIG_M5307) && \
- (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
@@ -92,10 +92,10 @@
move.w #0x2700,%sr
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
move.c %d0, %RAMBAR
/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
@@ -110,7 +110,7 @@
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
@@ -125,7 +125,7 @@
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 1dadffd..8a48d73 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -131,7 +131,7 @@
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
out_be16(&wdp->mr, wdog_module / 8192);
#else
diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c
index 1311f39..844d2cd 100644
--- a/arch/m68k/cpu/mcf532x/cpu_init.c
+++ b/arch/m68k/cpu/mcf532x/cpu_init.c
@@ -37,34 +37,34 @@
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -102,8 +102,8 @@
rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
- out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
- out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
+ out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT);
+ out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP);
#endif
#ifdef CONFIG_MCFFEC
@@ -236,36 +236,36 @@
/* Port configuration */
out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
/* Latch chipselect */
setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -327,7 +327,7 @@
clrbits_8(&gpio->par_feci2c, 0x00ff);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
-#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+#elif defined(CFG_SYS_UART2_ALT3_GPIO)
clrbits_be16(&gpio->par_ssi, 0x0f00);
setbits_be16(&gpio->par_ssi,
GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c
index dac2229..32ffac08 100644
--- a/arch/m68k/cpu/mcf532x/speed.c
+++ b/arch/m68k/cpu/mcf532x/speed.c
@@ -252,7 +252,7 @@
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
- gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
+ gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_SYS_I2C_FSL
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 2672891..72a2f99 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -98,11 +98,11 @@
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -131,7 +131,7 @@
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9b3f9f0..1ce2448 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -29,30 +29,30 @@
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_SERIAL_BOOT)
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
/* Latch chipselect */
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -208,14 +208,14 @@
/* FlexBus Chipselect */
init_fbcs();
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
* also move to the new location.
*/
- if (CONFIG_SYS_CS0_BASE != 0)
- setvbr(CONFIG_SYS_CS0_BASE);
+ if (CFG_SYS_CS0_BASE != 0)
+ setvbr(CFG_SYS_CS0_BASE);
#endif
icache_enable();
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index aea8f30..a083c3d 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -27,10 +27,10 @@
#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
+ CFG_SYS_INIT_RAM_ADDR)
#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
+ CFG_SYS_INIT_RAM_ADDR)
#endif
.text
@@ -123,18 +123,18 @@
#ifdef CONFIG_SYS_NAND_BOOT
/* for assembly stack */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
#endif
#ifdef CONFIG_CF_SBF
- move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
+ move.l #CFG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
@@ -145,7 +145,7 @@
move.l %d0, (%a2)
/* invalidate and disable cache */
- move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+ move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
@@ -153,17 +153,17 @@
movec %d0, %ACR2
movec %d0, %ACR3
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #(CFG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #(CFG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+ move.l #(CFG_SYS_CS0_MASK), (%a1)
#endif
#endif /* CONFIG_CF_SBF */
@@ -216,8 +216,8 @@
move.l (%a1)+, %d5
move.l (%a1), %a4
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
- move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
+ move.l #(CFG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
@@ -334,14 +334,14 @@
movec %d0, %ACR2
movec %d0, %ACR3
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #(CFG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #(CFG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+ move.l #(CFG_SYS_CS0_MASK), (%a1)
#endif
/* NAND port configuration */
@@ -442,10 +442,10 @@
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
@@ -456,7 +456,7 @@
move.l %d0, (%a2)
/* invalidate and disable cache */
- move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+ move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
@@ -464,7 +464,7 @@
movec %d0, %ACR2
movec %d0, %ACR3
#else
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
@@ -472,7 +472,7 @@
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index ceb462f..c05356f 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -135,28 +135,28 @@
#endif /* CONFIG_CF_V4 */
-#ifndef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_ICACR 0
+#ifndef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_ICACR 0
#endif
-#ifndef CONFIG_SYS_CACHE_DCACR
-#ifdef CONFIG_SYS_CACHE_ICACR
-#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
+#ifndef CFG_SYS_CACHE_DCACR
+#ifdef CFG_SYS_CACHE_ICACR
+#define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR
#else
-#define CONFIG_SYS_CACHE_DCACR 0
+#define CFG_SYS_CACHE_DCACR 0
#endif
#endif
-#ifndef CONFIG_SYS_CACHE_ACR0
-#define CONFIG_SYS_CACHE_ACR0 0
+#ifndef CFG_SYS_CACHE_ACR0
+#define CFG_SYS_CACHE_ACR0 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR1
-#define CONFIG_SYS_CACHE_ACR1 0
+#ifndef CFG_SYS_CACHE_ACR1
+#define CFG_SYS_CACHE_ACR1 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR2
-#define CONFIG_SYS_CACHE_ACR2 0
+#ifndef CFG_SYS_CACHE_ACR2
+#define CFG_SYS_CACHE_ACR2 0
#endif
#ifndef CONFIG_SYS_CACHE_ACR3
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 672aa0b..dab8b26 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -14,7 +14,7 @@
#include <asm/m520x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
@@ -37,7 +37,7 @@
#include <asm/m5235.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
@@ -59,7 +59,7 @@
#include <asm/immap_5249.h>
#include <asm/m5249.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
@@ -82,7 +82,7 @@
#include <asm/m5249.h>
#include <asm/m5253.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
@@ -105,7 +105,7 @@
#include <asm/m5271.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
@@ -128,7 +128,7 @@
#include <asm/m5272.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
@@ -152,7 +152,7 @@
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (192)
@@ -175,7 +175,7 @@
#include <asm/m5282.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
@@ -198,7 +198,7 @@
#include <asm/m5307.h>
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
- (CONFIG_SYS_UART_PORT * 0x40))
+ (CFG_SYS_UART_PORT * 0x40))
#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS (64)
@@ -223,7 +223,7 @@
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
@@ -246,7 +246,7 @@
#include <asm/m5329.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
@@ -271,12 +271,12 @@
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#if (CONFIG_SYS_UART_PORT < 4)
+#if (CFG_SYS_UART_PORT < 4)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
- (CONFIG_SYS_UART_PORT * 0x4000))
+ (CFG_SYS_UART_PORT * 0x4000))
#else
#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
- ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+ ((CFG_SYS_UART_PORT - 4) * 0x4000))
#endif
#define MMAP_DSPI MMAP_DSPI0
@@ -320,7 +320,7 @@
#define FEC1_TX_INIT 31
#endif
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
@@ -339,7 +339,7 @@
#ifdef CONFIG_PCI
#define CFG_SYS_PCI_BAR0 (0x40000000)
#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
-#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
+#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M547x */
diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h
index bb12374..7c7443b 100644
--- a/arch/m68k/include/asm/immap_520x.h
+++ b/arch/m68k/include/asm/immap_520x.h
@@ -9,32 +9,32 @@
#ifndef __IMMAP_520X__
#define __IMMAP_520X__
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000)
+#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000)
+#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000)
+#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000)
+#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h
index 27d905e..a1825c2 100644
--- a/arch/m68k/include/asm/immap_5235.h
+++ b/arch/m68k/include/asm/immap_5235.h
@@ -9,42 +9,42 @@
#ifndef __IMMAP_5235__
#define __IMMAP_5235__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h
index b599ca6..aa4c3ef 100644
--- a/arch/m68k/include/asm/immap_5249.h
+++ b/arch/m68k/include/asm/immap_5249.h
@@ -8,13 +8,13 @@
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400)
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/qspi.h>
diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h
index 883782a..1ab7243 100644
--- a/arch/m68k/include/asm/immap_5253.h
+++ b/arch/m68k/include/asm/immap_5253.h
@@ -9,20 +9,20 @@
#ifndef __IMMAP_5253__
#define __IMMAP_5253__
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_I2C0 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_CAN0 (CFG_SYS_MBAR + 0x00010000)
+#define MMAP_CAN1 (CFG_SYS_MBAR + 0x00011000)
-#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C)
-#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
-#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
+#define MMAP_PAR (CFG_SYS_MBAR2 + 0x0000019C)
+#define MMAP_I2C1 (CFG_SYS_MBAR2 + 0x00000440)
+#define MMAP_UART2 (CFG_SYS_MBAR2 + 0x00000C00)
#include <asm/coldfire/ata.h>
#include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h
index 27d7861..a5bf18c 100644
--- a/arch/m68k/include/asm/immap_5271.h
+++ b/arch/m68k/include/asm/immap_5271.h
@@ -9,42 +9,42 @@
#ifndef __IMMAP_5271__
#define __IMMAP_5271__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h
index cd7b672..c5c3cc7 100644
--- a/arch/m68k/include/asm/immap_5272.h
+++ b/arch/m68k/include/asm/immap_5272.h
@@ -8,24 +8,24 @@
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
-#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0)
-#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220)
-#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840)
-#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_CFG (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000020)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x000000A0)
+#define MMAP_PWM (CFG_SYS_MBAR + 0x000000C0)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x000000E0)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_TMR0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_TMR1 (CFG_SYS_MBAR + 0x00000220)
+#define MMAP_TMR2 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_TMR3 (CFG_SYS_MBAR + 0x00000260)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_PLIC (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840)
+#define MMAP_USB (CFG_SYS_MBAR + 0x00001000)
#include <asm/coldfire/pwm.h>
diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h
index 8b1a08b..9b8d71d 100644
--- a/arch/m68k/include/asm/immap_5275.h
+++ b/arch/m68k/include/asm/immap_5275.h
@@ -10,44 +10,44 @@
#ifndef __IMMAP_5275__
#define __IMMAP_5275__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
-#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h
index d7c68f5..f810a4d 100644
--- a/arch/m68k/include/asm/immap_5282.h
+++ b/arch/m68k/include/asm/immap_5282.h
@@ -8,42 +8,42 @@
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
-#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
-#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000)
-#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
-#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
-#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000)
-#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000)
-#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000)
-#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000)
-#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
-#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
+#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000)
+#define MMAP_QADC (CFG_SYS_MBAR + 0x00190000)
+#define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000)
+#define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000)
+#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000)
+#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h
index 29e6086..e1f7858 100644
--- a/arch/m68k/include/asm/immap_5301x.h
+++ b/arch/m68k/include/asm/immap_5301x.h
@@ -9,46 +9,46 @@
#ifndef __IMMAP_5301X__
#define __IMMAP_5301X__
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
-#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
-#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
-#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
-#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000)
-#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000)
-#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000)
-#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000)
-#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000)
-#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000)
-#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
-#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
-#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000)
-#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000)
-#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000)
+#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
index 930e089..d6442d9 100644
--- a/arch/m68k/include/asm/immap_5307.h
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -7,15 +7,15 @@
#ifndef __IMMAP_5307__
#define __IMMAP_5307__
-#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
-#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
-#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244)
+#define MMAP_SIM (CFG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CFG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC (CFG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244)
typedef struct sim {
u8 rsr;
diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h
index 9303629..afafb4e 100644
--- a/arch/m68k/include/asm/m5249.h
+++ b/arch/m68k/include/asm/m5249.h
@@ -14,14 +14,14 @@
/*
* useful definitions for reading/writing MBAR offset memory
*/
-#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
-#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
-#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
+#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x))
+#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y
/*
* Size of internal RAM
diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h
index 7ebeddb..e63b42c 100644
--- a/arch/m68k/include/asm/m5271.h
+++ b/arch/m68k/include/asm/m5271.h
@@ -11,12 +11,12 @@
#ifndef _MCF5271_H_
#define _MCF5271_H_
-#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
-#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
-#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
-#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
-#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x))
+#define mbar_readShort(x) *((volatile unsigned short *) (CFG_SYS_MBAR + x))
+#define mbar_readByte(x) *((volatile unsigned char *) (CFG_SYS_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y
#define MCF_FMPLL_SYNCR 0x120000
#define MCF_FMPLL_SYNSR 0x120004
diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h
index 0c91cf4..180f203 100644
--- a/arch/m68k/include/asm/m5282.h
+++ b/arch/m68k/include/asm/m5282.h
@@ -108,112 +108,112 @@
/* General Purpose I/O Module GPIO */
-#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
-#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
-#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
-#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
-#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
-#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
-#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
-#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
-#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
-#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
-#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
-#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
-#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
-#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
-#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
-#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
-#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
-#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
+#define MCFGPIO_PORTA (*(vu_char *) (CFG_SYS_MBAR+0x100000))
+#define MCFGPIO_PORTB (*(vu_char *) (CFG_SYS_MBAR+0x100001))
+#define MCFGPIO_PORTC (*(vu_char *) (CFG_SYS_MBAR+0x100002))
+#define MCFGPIO_PORTD (*(vu_char *) (CFG_SYS_MBAR+0x100003))
+#define MCFGPIO_PORTE (*(vu_char *) (CFG_SYS_MBAR+0x100004))
+#define MCFGPIO_PORTF (*(vu_char *) (CFG_SYS_MBAR+0x100005))
+#define MCFGPIO_PORTG (*(vu_char *) (CFG_SYS_MBAR+0x100006))
+#define MCFGPIO_PORTH (*(vu_char *) (CFG_SYS_MBAR+0x100007))
+#define MCFGPIO_PORTJ (*(vu_char *) (CFG_SYS_MBAR+0x100008))
+#define MCFGPIO_PORTDD (*(vu_char *) (CFG_SYS_MBAR+0x100009))
+#define MCFGPIO_PORTEH (*(vu_char *) (CFG_SYS_MBAR+0x10000A))
+#define MCFGPIO_PORTEL (*(vu_char *) (CFG_SYS_MBAR+0x10000B))
+#define MCFGPIO_PORTAS (*(vu_char *) (CFG_SYS_MBAR+0x10000C))
+#define MCFGPIO_PORTQS (*(vu_char *) (CFG_SYS_MBAR+0x10000D))
+#define MCFGPIO_PORTSD (*(vu_char *) (CFG_SYS_MBAR+0x10000E))
+#define MCFGPIO_PORTTC (*(vu_char *) (CFG_SYS_MBAR+0x10000F))
+#define MCFGPIO_PORTTD (*(vu_char *) (CFG_SYS_MBAR+0x100010))
+#define MCFGPIO_PORTUA (*(vu_char *) (CFG_SYS_MBAR+0x100011))
-#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
-#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
-#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
-#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
-#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
-#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
-#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
-#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
-#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
-#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
-#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
-#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
-#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
-#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
-#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
-#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
-#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
-#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
+#define MCFGPIO_DDRA (*(vu_char *) (CFG_SYS_MBAR+0x100014))
+#define MCFGPIO_DDRB (*(vu_char *) (CFG_SYS_MBAR+0x100015))
+#define MCFGPIO_DDRC (*(vu_char *) (CFG_SYS_MBAR+0x100016))
+#define MCFGPIO_DDRD (*(vu_char *) (CFG_SYS_MBAR+0x100017))
+#define MCFGPIO_DDRE (*(vu_char *) (CFG_SYS_MBAR+0x100018))
+#define MCFGPIO_DDRF (*(vu_char *) (CFG_SYS_MBAR+0x100019))
+#define MCFGPIO_DDRG (*(vu_char *) (CFG_SYS_MBAR+0x10001A))
+#define MCFGPIO_DDRH (*(vu_char *) (CFG_SYS_MBAR+0x10001B))
+#define MCFGPIO_DDRJ (*(vu_char *) (CFG_SYS_MBAR+0x10001C))
+#define MCFGPIO_DDRDD (*(vu_char *) (CFG_SYS_MBAR+0x10001D))
+#define MCFGPIO_DDREH (*(vu_char *) (CFG_SYS_MBAR+0x10001E))
+#define MCFGPIO_DDREL (*(vu_char *) (CFG_SYS_MBAR+0x10001F))
+#define MCFGPIO_DDRAS (*(vu_char *) (CFG_SYS_MBAR+0x100020))
+#define MCFGPIO_DDRQS (*(vu_char *) (CFG_SYS_MBAR+0x100021))
+#define MCFGPIO_DDRSD (*(vu_char *) (CFG_SYS_MBAR+0x100022))
+#define MCFGPIO_DDRTC (*(vu_char *) (CFG_SYS_MBAR+0x100023))
+#define MCFGPIO_DDRTD (*(vu_char *) (CFG_SYS_MBAR+0x100024))
+#define MCFGPIO_DDRUA (*(vu_char *) (CFG_SYS_MBAR+0x100025))
-#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+#define MCFGPIO_PORTAP (*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_PORTBP (*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_PORTCP (*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_PORTDP (*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_PORTEP (*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_PORTFP (*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_PORTGP (*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_PORTHP (*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_PORTJP (*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_PORTELP (*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_PORTASP (*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_SYS_MBAR+0x100039))
-#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
-#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
-#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
-#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
-#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
-#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
-#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
-#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
-#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
-#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
-#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
-#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
-#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
-#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
-#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
-#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
-#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
-#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+#define MCFGPIO_SETA (*(vu_char *) (CFG_SYS_MBAR+0x100028))
+#define MCFGPIO_SETB (*(vu_char *) (CFG_SYS_MBAR+0x100029))
+#define MCFGPIO_SETC (*(vu_char *) (CFG_SYS_MBAR+0x10002A))
+#define MCFGPIO_SETD (*(vu_char *) (CFG_SYS_MBAR+0x10002B))
+#define MCFGPIO_SETE (*(vu_char *) (CFG_SYS_MBAR+0x10002C))
+#define MCFGPIO_SETF (*(vu_char *) (CFG_SYS_MBAR+0x10002D))
+#define MCFGPIO_SETG (*(vu_char *) (CFG_SYS_MBAR+0x10002E))
+#define MCFGPIO_SETH (*(vu_char *) (CFG_SYS_MBAR+0x10002F))
+#define MCFGPIO_SETJ (*(vu_char *) (CFG_SYS_MBAR+0x100030))
+#define MCFGPIO_SETDD (*(vu_char *) (CFG_SYS_MBAR+0x100031))
+#define MCFGPIO_SETEH (*(vu_char *) (CFG_SYS_MBAR+0x100032))
+#define MCFGPIO_SETEL (*(vu_char *) (CFG_SYS_MBAR+0x100033))
+#define MCFGPIO_SETAS (*(vu_char *) (CFG_SYS_MBAR+0x100034))
+#define MCFGPIO_SETQS (*(vu_char *) (CFG_SYS_MBAR+0x100035))
+#define MCFGPIO_SETSD (*(vu_char *) (CFG_SYS_MBAR+0x100036))
+#define MCFGPIO_SETTC (*(vu_char *) (CFG_SYS_MBAR+0x100037))
+#define MCFGPIO_SETTD (*(vu_char *) (CFG_SYS_MBAR+0x100038))
+#define MCFGPIO_SETUA (*(vu_char *) (CFG_SYS_MBAR+0x100039))
-#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
-#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
-#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
-#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
-#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
-#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
-#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
-#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
-#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
-#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
-#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
-#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
-#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
-#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
-#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
-#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
-#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
-#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
+#define MCFGPIO_CLRA (*(vu_char *) (CFG_SYS_MBAR+0x10003C))
+#define MCFGPIO_CLRB (*(vu_char *) (CFG_SYS_MBAR+0x10003D))
+#define MCFGPIO_CLRC (*(vu_char *) (CFG_SYS_MBAR+0x10003E))
+#define MCFGPIO_CLRD (*(vu_char *) (CFG_SYS_MBAR+0x10003F))
+#define MCFGPIO_CLRE (*(vu_char *) (CFG_SYS_MBAR+0x100040))
+#define MCFGPIO_CLRF (*(vu_char *) (CFG_SYS_MBAR+0x100041))
+#define MCFGPIO_CLRG (*(vu_char *) (CFG_SYS_MBAR+0x100042))
+#define MCFGPIO_CLRH (*(vu_char *) (CFG_SYS_MBAR+0x100043))
+#define MCFGPIO_CLRJ (*(vu_char *) (CFG_SYS_MBAR+0x100044))
+#define MCFGPIO_CLRDD (*(vu_char *) (CFG_SYS_MBAR+0x100045))
+#define MCFGPIO_CLREH (*(vu_char *) (CFG_SYS_MBAR+0x100046))
+#define MCFGPIO_CLREL (*(vu_char *) (CFG_SYS_MBAR+0x100047))
+#define MCFGPIO_CLRAS (*(vu_char *) (CFG_SYS_MBAR+0x100048))
+#define MCFGPIO_CLRQS (*(vu_char *) (CFG_SYS_MBAR+0x100049))
+#define MCFGPIO_CLRSD (*(vu_char *) (CFG_SYS_MBAR+0x10004A))
+#define MCFGPIO_CLRTC (*(vu_char *) (CFG_SYS_MBAR+0x10004B))
+#define MCFGPIO_CLRTD (*(vu_char *) (CFG_SYS_MBAR+0x10004C))
+#define MCFGPIO_CLRUA (*(vu_char *) (CFG_SYS_MBAR+0x10004D))
-#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
-#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
-#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
-#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
-#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
-#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
-#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
-#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
-#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
-#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
-#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
+#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100050))
+#define MCFGPIO_PFPAR (*(vu_char *) (CFG_SYS_MBAR+0x100051))
+#define MCFGPIO_PEPAR (*(vu_short *)(CFG_SYS_MBAR+0x100052))
+#define MCFGPIO_PJPAR (*(vu_char *) (CFG_SYS_MBAR+0x100054))
+#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100055))
+#define MCFGPIO_PASPAR (*(vu_short *)(CFG_SYS_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_SYS_MBAR+0x100058))
+#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_SYS_MBAR+0x100059))
+#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
@@ -310,25 +310,25 @@
/* System Conrol Module SCM */
-#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
-#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
-#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
-#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
-#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
+#define MCFSCM_RAMBAR (*(vu_long *) (CFG_SYS_MBAR+0x00000008))
+#define MCFSCM_CRSR (*(vu_char *) (CFG_SYS_MBAR+0x00000010))
+#define MCFSCM_CWCR (*(vu_char *) (CFG_SYS_MBAR+0x00000011))
+#define MCFSCM_LPICR (*(vu_char *) (CFG_SYS_MBAR+0x00000012))
+#define MCFSCM_CWSR (*(vu_char *) (CFG_SYS_MBAR+0x00000013))
-#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
-#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
-#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
-#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
-#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
-#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
-#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
-#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
-#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
-#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
-#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
-#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
-#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
+#define MCFSCM_MPARK (*(vu_long *) (CFG_SYS_MBAR+0x0000001C))
+#define MCFSCM_MPR (*(vu_char *) (CFG_SYS_MBAR+0x00000020))
+#define MCFSCM_PACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000024))
+#define MCFSCM_PACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000025))
+#define MCFSCM_PACR2 (*(vu_char *) (CFG_SYS_MBAR+0x00000026))
+#define MCFSCM_PACR3 (*(vu_char *) (CFG_SYS_MBAR+0x00000027))
+#define MCFSCM_PACR4 (*(vu_char *) (CFG_SYS_MBAR+0x00000028))
+#define MCFSCM_PACR5 (*(vu_char *) (CFG_SYS_MBAR+0x0000002A))
+#define MCFSCM_PACR6 (*(vu_char *) (CFG_SYS_MBAR+0x0000002B))
+#define MCFSCM_PACR7 (*(vu_char *) (CFG_SYS_MBAR+0x0000002C))
+#define MCFSCM_PACR8 (*(vu_char *) (CFG_SYS_MBAR+0x0000002E))
+#define MCFSCM_GPACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000030))
+#define MCFSCM_GPACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
@@ -337,8 +337,8 @@
/* Reset Controller Module RCM */
-#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
-#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
+#define MCFRESET_RCR (*(vu_char *) (CFG_SYS_MBAR+0x00110000))
+#define MCFRESET_RSR (*(vu_char *) (CFG_SYS_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
@@ -360,9 +360,9 @@
/* Chip Configuration Module CCM */
-#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
-#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
-#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
+#define MCFCCM_CCR (*(vu_short *)(CFG_SYS_MBAR+0x00110004))
+#define MCFCCM_RCON (*(vu_short *)(CFG_SYS_MBAR+0x00110008))
+#define MCFCCM_CIR (*(vu_short *)(CFG_SYS_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
@@ -377,18 +377,18 @@
/* Clock Module */
-#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
-#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
+#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_SYS_MBAR+0x120000))
+#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_SYS_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
-#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
-#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
-#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
-#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
-#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
+#define MCFSDRAMC_DCR (*(vu_short *)(CFG_SYS_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_SYS_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_SYS_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000054))
#define MCFSDRAMC_DCR_NAM (0x2000)
#define MCFSDRAMC_DCR_COC (0x1000)
@@ -418,60 +418,60 @@
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
-#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
-#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
-#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
-#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
+#define MCFWTM_WCR (*(vu_short *)(CFG_SYS_MBAR+0x00140000))
+#define MCFWTM_WMR (*(vu_short *)(CFG_SYS_MBAR+0x00140002))
+#define MCFWTM_WCNTR (*(vu_short *)(CFG_SYS_MBAR+0x00140004))
+#define MCFWTM_WSR (*(vu_short *)(CFG_SYS_MBAR+0x00140006))
/*********************************************************************
* General Purpose Timer (GPT) Module
*********************************************************************/
-#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
-#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
-#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
-#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
-#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
-#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
-#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
-#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
-#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
-#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
-#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
-#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
-#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
-#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
-#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
-#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
-#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
-#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
-#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
-#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
-#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
-#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
+#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1A001E))
-#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
-#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
-#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
-#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
-#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
-#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
-#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
-#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
-#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
-#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
-#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
-#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
-#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
-#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
-#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
-#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
-#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
-#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
-#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
-#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
-#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
-#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
+#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1B001E))
/* Bit level definitions and macros */
#define MCFGPT_GPTIOS_IOS3 (0x08)
@@ -556,7 +556,7 @@
/* Coldfire Flash Module CFM */
-#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
+#define MCFCFM_MCR (*(vu_short *)(CFG_SYS_MBAR+0x1D0000))
#define MCFCFM_MCR_LOCK (0x0400)
#define MCFCFM_MCR_PVIE (0x0200)
#define MCFCFM_MCR_AEIE (0x0100)
@@ -564,23 +564,23 @@
#define MCFCFM_MCR_CCIE (0x0040)
#define MCFCFM_MCR_KEYACC (0x0020)
-#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
+#define MCFCFM_CLKD (*(vu_char *)(CFG_SYS_MBAR+0x1D0002))
-#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
+#define MCFCFM_SEC (*(vu_long*) (CFG_SYS_MBAR+0x1D0008))
#define MCFCFM_SEC_KEYEN (0x80000000)
#define MCFCFM_SEC_SECSTAT (0x40000000)
-#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
-#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
-#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
-#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
+#define MCFCFM_PROT (*(vu_long*) (CFG_SYS_MBAR+0x1D0010))
+#define MCFCFM_SACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0014))
+#define MCFCFM_DACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0018))
+#define MCFCFM_USTAT (*(vu_char*) (CFG_SYS_MBAR+0x1D0020))
#define MCFCFM_USTAT_CBEIF 0x80
#define MCFCFM_USTAT_CCIF 0x40
#define MCFCFM_USTAT_PVIOL 0x20
#define MCFCFM_USTAT_ACCERR 0x10
#define MCFCFM_USTAT_BLANK 0x04
-#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
+#define MCFCFM_CMD (*(vu_char*) (CFG_SYS_MBAR+0x1D0024))
#define MCFCFM_CMD_ERSVER 0x05
#define MCFCFM_CMD_PGERSVER 0x06
#define MCFCFM_CMD_PGM 0x20
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index 7eca672..0b4629f 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -16,7 +16,7 @@
{
struct bd_info *bd = gd->bd;
- bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
+ bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
@@ -38,7 +38,7 @@
struct bd_info *bd = gd->bd;
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
-#if defined(CONFIG_SYS_MBAR)
+#if defined(CFG_SYS_MBAR)
bdinfo_print_num_l("mbar", bd->bi_mbar_base);
#endif
bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index aa2b93e..4ddda69 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -34,18 +34,18 @@
*cf_icache_status = 1;
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
- __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+ __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
#if defined(CONFIG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
#endif
#else
- __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
- __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
#endif
- __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR));
}
void icache_disable(void)
@@ -72,9 +72,9 @@
{
u32 temp;
- temp = CONFIG_SYS_ICACHE_INV;
+ temp = CFG_SYS_ICACHE_INV;
if (*cf_icache_status)
- temp |= CONFIG_SYS_CACHE_ICACR;
+ temp |= CFG_SYS_CACHE_ICACR;
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
}
@@ -89,15 +89,15 @@
*cf_dcache_status = 1;
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
- __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
- __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+ __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
+ __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
#if defined(CONFIG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
#endif
#endif
- __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+ __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR));
}
void dcache_disable(void)
@@ -124,11 +124,11 @@
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
u32 temp;
- temp = CONFIG_SYS_DCACHE_INV;
+ temp = CFG_SYS_DCACHE_INV;
if (*cf_dcache_status)
- temp |= CONFIG_SYS_CACHE_DCACR;
+ temp |= CFG_SYS_CACHE_DCACR;
if (*cf_icache_status)
- temp |= CONFIG_SYS_CACHE_ICACR;
+ temp |= CFG_SYS_CACHE_ICACR;
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
#endif