ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
index ce6469d..50d9748 100644
--- a/board/exbitgen/exbitgen.c
+++ b/board/exbitgen/exbitgen.c
@@ -94,28 +94,28 @@
tot_size = 0;
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index c2dae56..7a9726f 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -382,7 +382,7 @@
/*----------------------------------------------------------- */
/* Set SDTR1 */
/*----------------------------------------------------------- */
- addi r5,0,mem_sdtr1
+ addi r5,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r5
mtdcr SDRAM0_CFGDATA,r4
@@ -413,7 +413,7 @@
/* Set SDRAM bank 0 register and adjust r6 for next bank */
/*------------------------------------------------------ */
- addi r7,0,mem_mb0cf
+ addi r7,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@@ -424,7 +424,7 @@
cmpi 0, r12, 2
bne b1skip
- addi r7,0,mem_mb1cf
+ addi r7,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@@ -432,7 +432,7 @@
/* Set SDRAM bank 2 register and adjust r6 for next bank */
/*------------------------------------------------------ */
-b1skip: addi r7,0,mem_mb2cf
+b1skip: addi r7,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@@ -443,7 +443,7 @@
cmpi 0, r12, 2
bne b3skip
- addi r7,0,mem_mb3cf
+ addi r7,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
b3skip:
@@ -456,7 +456,7 @@
addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
bl rtr_2
rtr_1: addis r7, 0, 0x03F8
-rtr_2: addi r4,0,mem_rtr
+rtr_2: addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
@@ -476,7 +476,7 @@
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */
/*----------------------------------------------------------- */
- addi r4,0,mem_mcopt1
+ addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x80C0 /* set DC_EN=1 */
ori r4,r4,0x0000