ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 0543bad..e61b5de 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -131,11 +131,11 @@
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -143,20 +143,20 @@
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
- mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
- mfsdram(mem_mcsts, reg);
+ mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 8513f43..d776eda 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -241,11 +241,11 @@
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -253,20 +253,20 @@
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
- mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
- mfsdram (mem_mcsts, reg);
+ mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 731d441..1ec13eb 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -237,7 +237,7 @@
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
- mtsdram(mem_tr1, (0x80800800 | i));
+ mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
@@ -289,15 +289,15 @@
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(mem_clktr, 0x40000000); /* ?? */
- mtsdram(mem_wddctr, 0x40000000); /* ?? */
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
+ mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
- mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+ mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -305,29 +305,29 @@
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
+ mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
- mtsdram(mem_tr0, 0x410a4012); /* ?? */
- mtsdram(mem_rtr, 0x04080000); /* ?? */
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
+ mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
+ mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x80000000); /* Enable */
+ mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
for (;;) {
- mfsdram(mem_mcsts, reg);
+ mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
- mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
+ mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
}
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 7913071..1656e8a 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -198,7 +198,7 @@
unsigned long tmp;
/* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00062001);
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
@@ -212,25 +212,25 @@
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
/* write SDRAM timing for 100MHz. */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x0086400D);
/* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x05F00000);
udelay (200);
/* sdram controller.*/
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x90800000);
udelay (200);
/* initially, disable ECC on all banks */
udelay (200);
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff;
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, tmp);
return;
@@ -282,15 +282,15 @@
}
printf ("Enable ECC..");
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
;
udelay (400);
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000;
mtdcr (SDRAM0_CFGDATA, tmp);
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 740e3ac..d6d65cf 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -135,28 +135,28 @@
tot_size = 0;
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
diff --git a/board/csb272/init.S b/board/csb272/init.S
index 15b26f8..a6b0d40 100644
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -175,26 +175,26 @@
* Disable memory controller to allow
* values to be changed.
*/
- WDCR_SDRAM(mem_mcopt1, 0x00000000)
+ WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/*
* Configure Memory Banks
*/
- WDCR_SDRAM(mem_mb0cf, 0x00084001)
- WDCR_SDRAM(mem_mb1cf, 0x00000000)
- WDCR_SDRAM(mem_mb2cf, 0x00000000)
- WDCR_SDRAM(mem_mb3cf, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
+ WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/*
* Set up SDTR1 (SDRAM Timing Register)
*/
- WDCR_SDRAM(mem_sdtr1, 0x00854009)
+ WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/*
* Set RTR (Refresh Timing Register)
*/
- WDCR_SDRAM(mem_rtr, 0x10000000)
- /* WDCR_SDRAM(mem_rtr, 0x05f00000) */
+ WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
+ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst
@@ -210,7 +210,7 @@
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
- WDCR_SDRAM(mem_mcopt1,0x80800000)
+ WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done:
blr /* Return to calling function */
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index 0c7760a..20d34ad 100644
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -103,28 +103,28 @@
tot_size = 0;
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
diff --git a/board/csb472/init.S b/board/csb472/init.S
index 105cb71..b31bd04 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -171,26 +171,26 @@
* Disable memory controller to allow
* values to be changed.
*/
- WDCR_SDRAM(mem_mcopt1, 0x00000000)
+ WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/*
* Configure Memory Banks
*/
- WDCR_SDRAM(mem_mb0cf, 0x00062001)
- WDCR_SDRAM(mem_mb1cf, 0x00000000)
- WDCR_SDRAM(mem_mb2cf, 0x00000000)
- WDCR_SDRAM(mem_mb3cf, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
+ WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/*
* Set up SDTR1 (SDRAM Timing Register)
*/
- WDCR_SDRAM(mem_sdtr1, 0x00854009)
+ WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/*
* Set RTR (Refresh Timing Register)
*/
- WDCR_SDRAM(mem_rtr, 0x10000000)
- /* WDCR_SDRAM(mem_rtr, 0x05f00000) */
+ WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
+ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst
@@ -206,7 +206,7 @@
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
- WDCR_SDRAM(mem_mcopt1,0x80800000)
+ WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done:
blr /* Return to calling function */
diff --git a/board/eric/init.S b/board/eric/init.S
index 16ab11e..c18663a 100644
--- a/board/eric/init.S
+++ b/board/eric/init.S
@@ -228,7 +228,7 @@
/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */
- addi r4,0,mem_mb0cf
+ addi r4,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB0CF@h
ori r4,r4,MB0CF@l
@@ -238,7 +238,7 @@
/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */
- addi r4,0,mem_mb1cf
+ addi r4,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB1CF@h
ori r4,r4,MB1CF@l
@@ -248,7 +248,7 @@
/* Set MB2CF for bank 2. off */
/*------------------------------------------------------------------- */
- addi r4,0,mem_mb2cf
+ addi r4,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB2CF@h
ori r4,r4,MB2CF@l
@@ -258,7 +258,7 @@
/* Set MB3CF for bank 3. off */
/*------------------------------------------------------------------- */
- addi r4,0,mem_mb3cf
+ addi r4,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB3CF@h
ori r4,r4,MB3CF@l
@@ -305,14 +305,14 @@
/*------------------------------------------------------------------- */
/* Set SDTR1 */
/*------------------------------------------------------------------- */
- addi r4,0,mem_sdtr1
+ addi r4,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r6
/*------------------------------------------------------------------- */
/* Set RTR */
/*------------------------------------------------------------------- */
- addi r4,0,mem_rtr
+ addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
@@ -332,7 +332,7 @@
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */
/*------------------------------------------------------------------- */
- addi r4,0,mem_mcopt1
+ addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x8080 /* set DC_EN=1 */
ori r4,r4,0x0000
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
index ce6469d..50d9748 100644
--- a/board/exbitgen/exbitgen.c
+++ b/board/exbitgen/exbitgen.c
@@ -94,28 +94,28 @@
tot_size = 0;
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index c2dae56..7a9726f 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -382,7 +382,7 @@
/*----------------------------------------------------------- */
/* Set SDTR1 */
/*----------------------------------------------------------- */
- addi r5,0,mem_sdtr1
+ addi r5,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r5
mtdcr SDRAM0_CFGDATA,r4
@@ -413,7 +413,7 @@
/* Set SDRAM bank 0 register and adjust r6 for next bank */
/*------------------------------------------------------ */
- addi r7,0,mem_mb0cf
+ addi r7,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@@ -424,7 +424,7 @@
cmpi 0, r12, 2
bne b1skip
- addi r7,0,mem_mb1cf
+ addi r7,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@@ -432,7 +432,7 @@
/* Set SDRAM bank 2 register and adjust r6 for next bank */
/*------------------------------------------------------ */
-b1skip: addi r7,0,mem_mb2cf
+b1skip: addi r7,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@@ -443,7 +443,7 @@
cmpi 0, r12, 2
bne b3skip
- addi r7,0,mem_mb3cf
+ addi r7,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
b3skip:
@@ -456,7 +456,7 @@
addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
bl rtr_2
rtr_1: addis r7, 0, 0x03F8
-rtr_2: addi r4,0,mem_rtr
+rtr_2: addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
@@ -476,7 +476,7 @@
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */
/*----------------------------------------------------------- */
- addi r4,0,mem_mcopt1
+ addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x80C0 /* set DC_EN=1 */
ori r4,r4,0x0000
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index 8afffdc..092a3d8 100644
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -116,16 +116,16 @@
{
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
- mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
- mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
- mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
- mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
- mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
- mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
+ mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL );
+ mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL );
+ mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL );
+ mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL );
+ mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL );
+ mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL );
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
- mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
+ mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
}
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
index bb6f85e..88fdd84 100644
--- a/board/jse/sdram.c
+++ b/board/jse/sdram.c
@@ -35,59 +35,59 @@
/* Configure the SDRAMS */
/* disable memory controller */
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, mem_besra);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, mem_besrb);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtdcr (SDRAM0_CFGADDR, mem_eccerr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x010a4016);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00084001);
/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, 0x04084001);
/* Memory Bank 2 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Memory Bank 3 Config == BE=0 */
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* refresh timer = 0x400 */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x04000000);
/* Power management idle timer set to the default. */
- mtdcr (SDRAM0_CFGADDR, mem_pmit);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
mtdcr (SDRAM0_CFGDATA, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x80e00000);
return SDRAM_LEN;
@@ -108,7 +108,7 @@
#ifdef DEBUG
printf ("SDRAM Controller Registers --\n");
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_CFG : 0x%08x\n", val);
@@ -116,19 +116,19 @@
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_STATUS: 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B0CR : 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B1CR : 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_TR : 0x%08x\n", val);
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_RTR : 0x%08x\n", val);
#endif
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index b87df01..ae8eade 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -348,7 +348,7 @@
/* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
sdram_tim |= ((unsigned long) (cal_val)) << 23;
@@ -369,7 +369,7 @@
/* insert SZ value; */
tmp |= ((unsigned long) sdram_table[i].sz << 17);
/* get SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_bank |= (baseaddr | tmp | 0x01);
@@ -380,7 +380,7 @@
#endif
/* write SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, sdram_tim);
#ifdef SDRAM_DEBUG
@@ -390,22 +390,22 @@
#endif
/* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, sdram_bank);
if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
/* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x07F00000;
} else {
/* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x05F00000;
}
/* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, tmp);
/* enable ECC if used */
#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
@@ -415,18 +415,18 @@
#ifdef SDRAM_DEBUG
serial_puts ("disable ECC.. ");
#endif
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff; /* disable all banks */
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
/* set up SDRAM Controller with ECC enabled */
#ifdef SDRAM_DEBUG
serial_puts ("setup SDRAM Controller.. ");
#endif
mtdcr (SDRAM0_CFGDATA, tmp);
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
#ifdef SDRAM_DEBUG
@@ -447,7 +447,7 @@
serial_puts ("enable ECC\n");
#endif
udelay (400);
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000; /* enable bank 0 */
mtdcr (SDRAM0_CFGDATA, tmp);
@@ -456,9 +456,9 @@
#endif
{
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
}
@@ -631,13 +631,13 @@
ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the
bank registers */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
@@ -648,7 +648,7 @@
} else
ds = 1;
}
- mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
if (!tmp)
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index c2d6c6f..792eccc 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -361,7 +361,7 @@
SDRAM_err ("unsupported SDRAM");
/* get SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
/* tmp |= ((unsigned long)cal_val) << 23; */
@@ -385,7 +385,7 @@
#endif
/* write SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, tmp);
baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2;
@@ -418,7 +418,7 @@
SDRAM_err ("unsupported SDRAM");
} /* endswitch */
/* get SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
@@ -434,11 +434,11 @@
sdram_size += bank_size;
/* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 1 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_size = 0;
@@ -459,11 +459,11 @@
serial_puts ("\n");
#endif
/* write SDRAM bank 1 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 2 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
@@ -482,11 +482,11 @@
sdram_size += bank_size;
/* write SDRAM bank 2 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 3 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
#ifdef SDRAM_DEBUG
@@ -509,12 +509,12 @@
#endif
/* write SDRAM bank 3 register */
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
if (tmemclk < NSto10PS (16))
@@ -523,13 +523,13 @@
tmp |= 0x03F80000;
/* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, tmp);
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
@@ -619,13 +619,13 @@
/* since the DRAM controller is allready set up,
* calculate the size with the bank registers
*/
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c
index f7baed6..2f21fbb 100644
--- a/board/netstal/common/fixed_sdram.c
+++ b/board/netstal/common/fixed_sdram.c
@@ -29,17 +29,17 @@
u32 value;
printf("SDRAM Controller Registers --\n");
- mfsdram(mem_mcopt1, value);
+ mfsdram(SDRAM0_CFG, value);
printf(" SDRAM0_CFG : 0x%08x\n", value);
- mfsdram(mem_status, value);
+ mfsdram(SDRAM0_STATUS, value);
printf(" SDRAM0_STATUS: 0x%08x\n", value);
- mfsdram(mem_mb0cf, value);
+ mfsdram(SDRAM0_B0CR, value);
printf(" SDRAM0_B0CR : 0x%08x\n", value);
- mfsdram(mem_mb1cf, value);
+ mfsdram(SDRAM0_B1CR, value);
printf(" SDRAM0_B1CR : 0x%08x\n", value);
- mfsdram(mem_sdtr1, value);
+ mfsdram(SDRAM0_TR, value);
printf(" SDRAM0_TR : 0x%08x\n", value);
- mfsdram(mem_rtr, value);
+ mfsdram(SDRAM0_RTR, value);
printf(" SDRAM0_RTR : 0x%08x\n", value);
}
#endif
@@ -50,53 +50,53 @@
printf(__FUNCTION__);
#endif
/* disable memory controller */
- mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(SDRAM0_CFG, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtsdram(mem_besra, 0xffffffff);
+ mtsdram(SDRAM0_BESR0, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtsdram(mem_besrb, 0xffffffff);
+ mtsdram(SDRAM0_BESR1, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
- mtsdram(mem_ecccf, 0x00000000);
+ mtsdram(SDRAM0_ECCCFG, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtsdram(mem_eccerr, 0xffffffff);
+ mtsdram(SDRAM0_ECCESR, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
*/
- mtsdram(mem_sdtr1, 0x008a4015);
+ mtsdram(SDRAM0_TR, 0x008a4015);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
* and refresh timer
*/
switch (dram_size >> 20) {
case 32:
- mtsdram(mem_mb0cf, 0x00062001);
- mtsdram(mem_rtr, 0x07F00000);
+ mtsdram(SDRAM0_B0CR, 0x00062001);
+ mtsdram(SDRAM0_RTR, 0x07F00000);
break;
case 64:
- mtsdram(mem_mb0cf, 0x00084001);
- mtsdram(mem_rtr, 0x04100000);
+ mtsdram(SDRAM0_B0CR, 0x00084001);
+ mtsdram(SDRAM0_RTR, 0x04100000);
break;
case 128:
- mtsdram(mem_mb0cf, 0x000A4001);
- mtsdram(mem_rtr, 0x04100000);
+ mtsdram(SDRAM0_B0CR, 0x000A4001);
+ mtsdram(SDRAM0_RTR, 0x04100000);
break;
default:
printf("Invalid memory size of %d MB given\n", dram_size >> 20);
}
/* Power management idle timer set to the default. */
- mtsdram(mem_pmit, 0x07c00000);
+ mtsdram(SDRAM0_PMIT, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
- mtsdram(mem_mcopt1, 0x90800000);
+ mtsdram(SDRAM0_CFG, 0x90800000);
#ifdef DEBUG
printf("%s: done\n", __FUNCTION__);
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index d8b0564..e1c6146 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -266,11 +266,11 @@
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -278,20 +278,20 @@
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
- mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
- mfsdram (mem_mcsts, reg);
+ mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index e7772c5..63927f7 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -577,7 +577,7 @@
}
#ifdef SC3_DEBUGOUT
-static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
+static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
#endif
phys_size_t initdram (int board_type)
@@ -591,7 +591,7 @@
puts("\nSDRAM configuration:\n");
- mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
ul1 = mfdcr(SDRAM0_CFGDATA);
if (!(ul1 & 0x80000000)) {
@@ -604,7 +604,7 @@
mems += printSDRAMConfig (i, ul1);
}
- mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
ul1 = mfdcr(SDRAM0_CFGDATA);
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
@@ -614,14 +614,14 @@
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n");
- mtdcr (SDRAM0_CFGADDR, mem_rtr);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
ul1 = mfdcr(SDRAM0_CFGDATA);
printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
- mtdcr(SDRAM0_CFGADDR,mem_pmit);
+ mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
ul2=mfdcr(SDRAM0_CFGDATA);
- mtdcr(SDRAM0_CFGADDR,mem_mcopt1);
+ mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
ul1=mfdcr(SDRAM0_CFGDATA);
if (ul1 & 0x20000000)
@@ -658,7 +658,7 @@
else
puts(" -Memory lines only at write cycles active outputs\n");
- mtdcr (SDRAM0_CFGADDR, mem_status);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
ul1 = mfdcr (SDRAM0_CFGDATA);
if (ul1 & 0x80000000)
puts(" -SDRAM Controller ready\n");
@@ -670,19 +670,19 @@
return (mems * 1024 * 1024);
#else
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
ul1 = mfdcr (SDRAM0_CFGDATA);
mems = printSDRAMConfig (0, ul1);
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
ul1 = mfdcr (SDRAM0_CFGDATA);
mems += printSDRAMConfig (1, ul1);
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
ul1 = mfdcr(SDRAM0_CFGDATA);
mems += printSDRAMConfig (2, ul1);
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
ul1 = mfdcr(SDRAM0_CFGDATA);
mems += printSDRAMConfig (3, ul1);
diff --git a/board/w7o/init.S b/board/w7o/init.S
index 090b07a..5477f98 100644
--- a/board/w7o/init.S
+++ b/board/w7o/init.S
@@ -182,7 +182,7 @@
* Disable memory controller to allow
* values to be changed.
*/
- addi r3, 0, mem_mcopt1
+ addi r3, 0, SDRAM0_CFG
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0
ori r4, r4, 0x0
@@ -192,7 +192,7 @@
* Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
* All other banks are disabled.
*/
- addi r3, 0, mem_mb0cf
+ addi r3, 0, SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
@@ -222,7 +222,7 @@
/*
* Set up SDTR1
*/
- addi r3, 0, mem_sdtr1
+ addi r3, 0, SDRAM0_TR
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
ori r4, r4, 0x400D
@@ -231,7 +231,7 @@
/*
* Set RTR
*/
- addi r3, 0, mem_rtr
+ addi r3, 0, SDRAM0_RTR
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
mtdcr SDRAM0_CFGDATA, r4
@@ -250,7 +250,7 @@
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
- addi r3, 0, mem_mcopt1
+ addi r3, 0, SDRAM0_CFG
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
index 00a9f98..a818808 100644
--- a/board/w7o/w7o.c
+++ b/board/w7o/w7o.c
@@ -170,16 +170,16 @@
int size = 0;
/* Get bank Size registers */
- mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
regs[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
regs[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
regs[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
regs[3] = mfdcr (SDRAM0_CFGDATA);
/* compute the size, add each bank if enabled */