commit 68295d6c71c90d91a6910c4cef1cefb744988f10
author developer <developer@mediatek.com> Tue Dec 17 16:39:20 2024 +0800
committer Tom Rini <trini@konsulko.com> Tue Dec 31 10:58:52 2024 -0600
tree 39974cd0d4da04722a61a1066cd77a8cdd678635
parent 85cbb0d19f592ae068f5f174d31751c89ecf378d

arm: dts: mt7629: fix sgmii clock selection for ethernet

Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
sgmiisys1 work correctly.

arch/arm/dts/mt7629.dtsi

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index 7dea780..cd8277d 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -314,8 +314,10 @@
 				"sgmii2_cdr_ref", "sgmii2_cdr_fb",
 				"sgmii_ck", "eth2pll";
 		assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
-				  <&topckgen CLK_TOP_F10M_REF_SEL>;
+				  <&topckgen CLK_TOP_F10M_REF_SEL>,
+				  <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
 		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+					 <&topckgen CLK_TOP_SYSPLL4_D16>,
 					 <&topckgen CLK_TOP_SGMIIPLL_D2>;
 		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 		resets = <&ethsys ETHSYS_FE_RST>;