| commit | 85cbb0d19f592ae068f5f174d31751c89ecf378d | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue Dec 17 16:39:16 2024 +0800 |
| committer | Tom Rini <trini@konsulko.com> | Tue Dec 31 10:58:52 2024 -0600 |
| tree | b26eba1216b3f46c633331048d27588a1739053c | |
| parent | 226dc38760e39b30f1ffae43ac2c0bf46dfd62fb [diff] |
clk: mediatek: mt7629: fix parent clock of some top clock muxes According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL shares the same parent selection with CLK_TOP_IRRX_SEL, while the present parent selection for CLK_TOP_F10M_REF_SEL is actually used for CLK_TOP_SGMII_REF_1_SEL.