| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2020 NXP |
| */ |
| |
| #ifndef __IMX8ULP_EVK_H |
| #define __IMX8ULP_EVK_H |
| |
| #include <linux/sizes.h> |
| #include <asm/arch/imx-regs.h> |
| |
| #define CONFIG_SYS_BOOTM_LEN (SZ_64M) |
| #define CONFIG_SPL_MAX_SIZE (148 * 1024) |
| #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SPL_STACK 0x22050000 |
| #define CONFIG_SPL_BSS_START_ADDR 0x22048000 |
| #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ |
| #define CONFIG_SYS_SPL_MALLOC_START 0x22040000 |
| #define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */ |
| |
| #define CONFIG_MALLOC_F_ADDR 0x22040000 |
| |
| #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ |
| |
| #endif |
| |
| #define COUNTER_FREQUENCY 1000000 /* 1MHz */ |
| |
| /* ENET Config */ |
| #if defined(CONFIG_FEC_MXC) |
| #define PHY_ANEG_TIMEOUT 20000 |
| |
| #define CONFIG_FEC_MXC_PHYADDR 1 |
| |
| #define IMX_FEC_BASE 0x29950000 |
| #endif |
| |
| #ifdef CONFIG_DISTRO_DEFAULTS |
| #define BOOT_TARGET_DEVICES(func) \ |
| func(MMC, mmc, 0) |
| |
| #include <config_distro_bootcmd.h> |
| #else |
| #define BOOTENV |
| #endif |
| |
| /* Initial environment variables */ |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| BOOTENV \ |
| "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
| "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
| "image=Image\0" \ |
| "console=ttyLP1,115200 earlycon\0" \ |
| "fdt_addr_r=0x83000000\0" \ |
| "boot_fit=no\0" \ |
| "fdtfile=imx8ulp-evk.dtb\0" \ |
| "initrd_addr=0x83800000\0" \ |
| "bootm_size=0x10000000\0" \ |
| "mmcpart=1\0" \ |
| "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ |
| |
| /* Link Definitions */ |
| |
| #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
| #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 |
| #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| |
| #define CONFIG_MMCROOT "/dev/mmcblk2p2" |
| |
| #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| #define PHYS_SDRAM 0x80000000 |
| #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ |
| |
| /* Monitor Command Prompt */ |
| #define CONFIG_SYS_CBSIZE 2048 |
| #define CONFIG_SYS_MAXARGS 64 |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| |
| /* Using ULP WDOG for reset */ |
| #define WDOG_BASE_ADDR WDG3_RBASE |
| #endif |