| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| |
| #ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H |
| #define _DT_BINDINGS_RESET_MT6735_INFRACFG_H |
| |
| #define MT6735_INFRA_RST0_EMI_REG 0 |
| #define MT6735_INFRA_RST0_DRAMC0_AO 1 |
| #define MT6735_INFRA_RST0_AP_CIRQ_EINT 2 |
| #define MT6735_INFRA_RST0_APXGPT 3 |
| #define MT6735_INFRA_RST0_SCPSYS 4 |
| #define MT6735_INFRA_RST0_KP 5 |
| #define MT6735_INFRA_RST0_PMIC_WRAP 6 |
| #define MT6735_INFRA_RST0_CLDMA_AO_TOP 7 |
| #define MT6735_INFRA_RST0_USBSIF_TOP 8 |
| #define MT6735_INFRA_RST0_EMI 9 |
| #define MT6735_INFRA_RST0_CCIF 10 |
| #define MT6735_INFRA_RST0_DRAMC0 11 |
| #define MT6735_INFRA_RST0_EMI_AO_REG 12 |
| #define MT6735_INFRA_RST0_CCIF_AO 13 |
| #define MT6735_INFRA_RST0_TRNG 14 |
| #define MT6735_INFRA_RST0_SYS_CIRQ 15 |
| #define MT6735_INFRA_RST0_GCE 16 |
| #define MT6735_INFRA_RST0_M4U 17 |
| #define MT6735_INFRA_RST0_CCIF1 18 |
| #define MT6735_INFRA_RST0_CLDMA_TOP_PD 19 |
| |
| #endif |