| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC. |
| * |
| * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries |
| * |
| * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/dma/at91.h> |
| #include <dt-bindings/pinctrl/at91.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clk/at91.h> |
| |
| /{ |
| model = "Microchip SAM9X60 SoC"; |
| compatible = "microchip,sam9x60"; |
| interrupt-parent = <&aic>; |
| |
| aliases { |
| serial0 = &dbgu; |
| gpio0 = &pioA; |
| gpio1 = &pioB; |
| gpio2 = &pioC; |
| gpio3 = &pioD; |
| spi0 = &qspi; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ARM9260_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,arm926ej-s"; |
| clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>; |
| clock-names = "cpu", "master", "xtal"; |
| }; |
| }; |
| |
| clocks { |
| slow_rc_osc: slow_rc_osc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <18500>; |
| }; |
| |
| main_rc: main_rc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <12000000>; |
| }; |
| |
| slow_xtal: slow_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| main_xtal: main_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| ahb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| usb0: gadget@500000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "microchip,sam9x60-udc"; |
| reg = <0x500000 0x100000>, |
| <0xf803c000 0x400>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE 8>; |
| clock-names = "pclk", "hclk"; |
| assigned-clocks = <&pmc PMC_TYPE_CORE 8>; |
| assigned-clock-rates = <480000000>; |
| status = "disabled"; |
| }; |
| |
| usb1: usb@600000 { |
| compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| reg = <0x00600000 0x100000>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>; |
| clock-names = "ohci_clk", "hclk", "uhpck"; |
| status = "disabled"; |
| }; |
| |
| usb2: usb@700000 { |
| compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| reg = <0x00700000 0x100000>; |
| clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>; |
| clock-names = "usb_clk", "ehci_clk"; |
| assigned-clocks = <&pmc PMC_TYPE_CORE 8>; |
| assigned-clock-rates = <480000000>; |
| status = "disabled"; |
| }; |
| |
| ebi: ebi@10000000 { |
| compatible = "microchip,sam9x60-ebi"; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| atmel,smc = <&smc>; |
| microchip,sfr = <&sfr>; |
| reg = <0x10000000 0x60000000>; |
| ranges = <0x0 0x0 0x10000000 0x10000000 |
| 0x1 0x0 0x20000000 0x10000000 |
| 0x2 0x0 0x30000000 0x10000000 |
| 0x3 0x0 0x40000000 0x10000000 |
| 0x4 0x0 0x50000000 0x10000000 |
| 0x5 0x0 0x60000000 0x10000000>; |
| clocks = <&pmc PMC_TYPE_CORE 11>; |
| status = "disabled"; |
| |
| nand_controller: nand-controller { |
| compatible = "microchip,sam9x60-nand-controller"; |
| ecc-engine = <&pmecc>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges; |
| status = "disabled"; |
| }; |
| }; |
| |
| sdhci0: sdhci-host@80000000 { |
| compatible = "microchip,sam9x60-sdhci"; |
| reg = <0x80000000 0x300>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; |
| clock-names = "hclock", "multclk"; |
| assigned-clocks = <&pmc PMC_TYPE_GCK 12>; |
| assigned-clock-rates = <100000000>; |
| assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ |
| bus-width = <4>; |
| }; |
| |
| sdhci1: sdhci-host@90000000 { |
| compatible = "microchip,sam9x60-sdhci"; |
| reg = <0x90000000 0x300>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; |
| clock-names = "hclock", "multclk"; |
| assigned-clocks = <&pmc PMC_TYPE_GCK 26>; |
| assigned-clock-rates = <100000000>; |
| assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ |
| bus-width = <4>; |
| }; |
| |
| apb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| qspi: spi@f0014000 { |
| compatible = "microchip,sam9x60-qspi"; |
| reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; |
| reg-names = "qspi_base", "qspi_mmap"; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */ |
| clock-names = "pclk", "qspick"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pit64b0: timer@f0028000 { |
| compatible = "microchip,sam9x60-pit64b"; |
| reg = <0xf0028000 0xec>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; |
| clock-names = "pclk", "gclk"; |
| }; |
| |
| flx0: flexcom@f801c600 { |
| compatible = "atmel,sama5d2-flexcom"; |
| reg = <0xf801c000 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xf801c000 0x800>; |
| status = "disabled"; |
| }; |
| |
| macb0: ethernet@f802c000 { |
| compatible = "cdns,sam9x60-macb", "cdns,macb"; |
| reg = <0xf802c000 0x100>; |
| clock-names = "hclk", "pclk"; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; |
| status = "disabled"; |
| }; |
| |
| sfr: sfr@f8050000 { |
| compatible = "microchip,sam9x60-sfr", "syscon"; |
| reg = <0xf8050000 0x100>; |
| }; |
| |
| pmecc: ecc-engine@ffffe000 { |
| compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; |
| reg = <0xffffe000 0x300>, |
| <0xffffe600 0x100>; |
| }; |
| |
| smc: smc@ffffea00 { |
| compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; |
| reg = <0xffffea00 0x100>; |
| }; |
| |
| aic: interrupt-controller@fffff100 { |
| compatible = "microchip,sam9x60-aic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0xfffff100 0x100>; |
| atmel,external-irqs = <31>; |
| }; |
| |
| dbgu: serial@fffff200 { |
| compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; |
| reg = <0xfffff200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; |
| clock-names = "usart"; |
| }; |
| |
| pinctrl: pinctrl@fffff400 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "microchip,sam9x60-pinctrl", "simple-mfd"; |
| ranges = <0xfffff400 0xfffff400 0x800>; |
| |
| /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ |
| atmel,mux-mask = < |
| /* A B C */ |
| 0xffffffff 0xffe03fff 0xef00019d /* pioA */ |
| 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ |
| 0xffffffff 0xffffffff 0xf83fffff /* pioC */ |
| 0x003fffff 0x003f8000 0x00000000 /* pioD */ |
| >; |
| |
| pioA: gpio@fffff400 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff400 0x200>; |
| interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; |
| }; |
| |
| pioB: gpio@fffff600 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff600 0x200>; |
| interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #gpio-lines = <26>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; |
| }; |
| |
| pioC: gpio@fffff800 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff800 0x200>; |
| interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; |
| }; |
| |
| pioD: gpio@fffffa00 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffffa00 0x200>; |
| interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #gpio-lines = <22>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; |
| }; |
| }; |
| |
| pmc: pmc@fffffc00 { |
| compatible = "microchip,sam9x60-pmc"; |
| reg = <0xfffffc00 0x200>; |
| #clock-cells = <2>; |
| clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>; |
| clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; |
| status = "okay"; |
| }; |
| |
| reset_controller: rstc@fffffe00 { |
| compatible = "microchip,sam9x60-rstc"; |
| reg = <0xfffffe00 0x10>; |
| clocks = <&clk32 0>; |
| }; |
| |
| pit: timer@fffffe40 { |
| compatible = "atmel,at91sam9260-pit"; |
| reg = <0xfffffe40 0x10>; |
| clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */ |
| }; |
| |
| clk32: sckc@fffffe50 { |
| compatible = "microchip,sam9x60-sckc"; |
| reg = <0xfffffe50 0x4>; |
| clocks = <&slow_rc_osc>, <&slow_xtal>; |
| #clock-cells = <1>; |
| }; |
| }; |
| }; |
| |
| onewire_tm: onewire { |
| compatible = "w1-gpio"; |
| status = "disabled"; |
| }; |
| }; |