| /* SPDX-License-Identifier: GPL-2.0+ */ | |
| /* | |
| * Copyright 2022 NXP | |
| */ | |
| #ifndef __ASM_ARCH_IMX9_REGS_H__ | |
| #define __ASM_ARCH_IMX9_REGS_H__ | |
| #define ARCH_MXC | |
| #define IOMUXC_BASE_ADDR 0x443C0000UL | |
| #define CCM_BASE_ADDR 0x44450000UL | |
| #define CCM_CCGR_BASE_ADDR 0x44458000UL | |
| #define SYSCNT_CTRL_BASE_ADDR 0x44290000 | |
| #define ANATOP_BASE_ADDR 0x44480000UL | |
| #define WDG3_BASE_ADDR 0x42490000UL | |
| #define WDG4_BASE_ADDR 0x424a0000UL | |
| #define WDG5_BASE_ADDR 0x424b0000UL | |
| #endif |